Shared resource management and synchronization method and system in communication mode that single chip is connected with multiple hosts

Abstract

The invention provides a shared resource management and synchronization method and system in a communication mode that a single chip is connected with multiple hosts, and the system comprises a network communication board card and a plurality of hosts connected with the network communication board card, thereby forming a multi-host system. When a single chip is simultaneously connected with a plurality of hosts for network deployment and use, the management configuration authority of the chip / FPGA can be allocated and synchronized, the shared use authority, conflict mechanism and dynamic update of public resources are managed and configured, and the access and use efficiency of the shared resources in the mode that the single chip is connected with the plurality of hosts is improved. And the states of multiple hosts can be decoupled, and the control hosts can be dynamically updated based on the on-line states of the hosts, so that the influence of a single-point fault on the access of other hosts to on-chip shared resources is avoided.

Description

Technical Field

[0001] The present invention relates to the field of network communication technology, and in particular to a shared resource management and synchronization method in a multi-host network communication mode based on single-chip network communication board connection, and a shared resource management system. Background Art

[0002] With the rapid development of embedded products, higher and higher requirements are placed on the performance of network communications. 10G / 25G Ethernet technology has become an important network communication technology for the next generation of embedded products due to its scalability and convenient deployment. However, 10G / 25G high-speed network communication boards, especially FPGA products, have disadvantages such as high power consumption and high cost. The large-scale deployment of this product will bring high deployment costs and power consumption and heat dissipation problems of the whole machine. If a single network communication board can be deployed in a way that can be used by multiple hosts, the communication cost of a single host can be shared, the system integration can be improved, and the overall cost of deploying high-speed network communication boards can be greatly reduced. At the same time, not all services and hosts require high-bandwidth networks during system operation. Providing multiple host interfaces through network communication boards can make a single chip / FPGA serve multiple hosts a cost-effective deployment solution.

[0003] When a single chip is connected to multiple hosts, the chip / FPGA will become a shared resource for multiple hosts. How to configure and manage public resources and avoid conflicts in configuration management of public resources between multiple hosts becomes a problem in multi-host deployment. For example, in the TSN network, time synchronization service only requires one host to cooperate with the network chip to complete time synchronization. Other hosts can directly use the time synchronization service to avoid multiple hosts adjusting the network chip time at the same time, which will cause synchronization problems. Moreover, in a multi-host system, the failure of a single host should not affect the normal communication of other hosts. A certain degree of independence must be guaranteed between hosts and between hosts and chips. When a host fails, how to redistribute the management configuration rights of the chip / FPGA is also a problem. Summary of the invention

[0004] The purpose of the present invention is to provide a shared resource management system in a multi-host communication mode based on a single-chip network communication board connection, so as to realize the allocation and synchronization of chip / FPGA management configuration permissions when a single chip is simultaneously connected to multiple host networks for deployment and use, manage and configure the shared use permissions, conflict mechanisms and dynamic updates of public resources, and improve the access and use efficiency of shared resources in a single-chip multi-host mode.

[0005] The present invention also aims to provide a shared resource management and synchronization method in a multi-host communication mode based on a single-chip network communication board connection, in which a single chip / FPGA connected to multiple hosts is synchronously configured, managed and controlled by a control host, and the control host maintains common resources, thereby avoiding the synchronization overhead of a single operation and improving the management and control efficiency; and the status of multiple hosts is decoupled, and the control host can be dynamically updated based on the online status of each host, thereby avoiding the impact of single point failures on other hosts' access to shared resources on the chip.

[0006] According to a first aspect of the present invention, a shared resource management system in a multi-host communication mode based on a single-chip network communication card connection is provided, comprising a network communication card and a plurality of hosts connected to the network communication card, forming a multi-host system; The network communication board adopts the main control network chip and FPGA integrated architecture, and provides shared resources for multiple hosts through the main control network chip and FPGA. The shared resources include public services provided by the main control network chip and public resources provided by FPGA; the network communication board is configured with multiple PCIE interfaces and Ethernet MAC modules; The host is connected to the network communication board via a PCIE interface, and can operate the register of the FPGA to implement the configuration management of the FPGA, so that the FPGA can complete the corresponding functions; and exchanges data messages with the network communication board 100 based on the DMA method to realize network communication; The FPGA is provided with a control host ID register for recording the ID of the multiple hosts configured as the control host, the control host is configured with control authority over the FPGA to complete the configuration management of the FPGA, and when the control host goes offline / exits abnormally, the value of the control host ID register is modified to 0 to release the control authority of the FPGA; At any time, there is only one host among the multiple hosts that can become the control host by modifying the value of the control host ID register to the host ID when the value of the control host ID register is 0; The FPGA is also provided with a plurality of lock registers, each lock register being configured to identify the access control of the corresponding shared resource; each host implements the access control to the shared resource through the state of the lock register corresponding to the shared resource and the read-write arbitration.

[0007] According to a second aspect of the present invention, a shared resource management and synchronization method in a single-chip-connected-to-multiple-host communication mode based on the aforementioned shared resource management system is also proposed, comprising the following steps: (1) Network communication board is powered on and running: The network communication board is powered on and runs. The FPGA runs the corresponding logic version according to the configuration file in FLASH, waits for the host to connect and perform management configuration. (2) The host is powered on and running: After the first host is powered on, it scans the PCIE interface and obtains the ID information of the host in the multi-host system by reading the host ID register. After receiving the read request, the FPGA returns the host ID information according to the PCIE interface connected to the host. The host ID can be any non-zero value. The host reads the control host ID register and writes its host ID into the control host ID register based on the control host ID register being 0, identifying it as the control host, obtaining the control authority of the FPGA, and being able to perform configuration management of the FPGA and control access to shared resources. After other hosts in the multi-host system are powered on, the FPGA returns the host ID information based on the PCIE interface connected to the host. Different PCIE interfaces return different host IDs. Other hosts identify themselves as slaves based on the value of the control host ID and record the control host ID. (3) Host access to shared resources of network communication board When a host needs to control access to the shared resources provided by the network communication board, it first writes the host ID into the lock register of the shared resource to be accessed. The FPGA determines whether the lock register is 0. If it is 0, it means that no host currently occupies the shared resource. The FPGA arbitrates the access requests of multiple hosts to the lock register through the read-write arbitration module, and writes a host ID into the lock register according to the arbitration result, indicating that the host has obtained the access right to the shared resource. The host reads the lock register of the shared resource to be accessed and determines whether it is the same as its own host ID: if it is the same, it indicates that the host has obtained the access right to the shared resource to be accessed; if it is different, it indicates that the shared resource is being accessed by other hosts, and it will continue to try to access the lock register after waiting for a predetermined time; When a host obtains the access right to the shared resource to be accessed, when the host controls access to the shared resource, the FPGA determines whether the host ID of the access request is the same as the host ID of the lock register of the shared resource to be accessed: if they are the same, the host is allowed to access the shared resource; if they are different, the access request is ignored; After the host completes resource access, the FPGA clears the lock register of the shared resource to be accessed to 0, indicating that the control access to the shared resource has ended; (4) The host updates the shared resources of the network communication board When a host needs to update the shared resources provided by the network communication board, first determine whether the host is a control host: If the host is determined to be a control host, the FPGA further checks whether the register write request is initiated from the control host: if it is a register write request initiated from the control host, the FPGA configuration is modified according to the register write request to complete the update of the FPGA configuration file; if it is not a write request initiated from the control host, the register write request is ignored; If it is determined that the host is not the control host, the control host ID register is further read. If the value of the control host ID register is not 0, the host sends a register write request to the control host, and the control host checks the consistency of the configuration file and modifies the FPGA configuration file according to the register write request; if the value of the control host ID register is 0, the host ID is written to the control host ID register to identify the host as the control host and obtain the control authority of the FPGA, and then further check whether the register write request is initiated from the control host: if it is a register write request initiated from the control host, the FPGA configuration is modified according to the register write request to complete the update of the FPGA configuration file; if it is a write request not initiated from the control host, the register write request is ignored.

[0008] As an optional implementation, the method further includes the following steps: When the control host goes offline / exits abnormally, the value of the control host ID register is changed to 0 to release the chip control right.

[0009] As an optional implementation, when the control host goes offline / exits abnormally, the value of the control host ID register is modified to 0 to release the chip control right, including: When any of the multiple hosts actively goes offline, if the host determines that it is the control host based on the value of the control host ID register: the value of the control host ID register is set to 0, releasing the FPGA control right; If the host exits abnormally, the FPGA detects that the host is disconnected. The FPGA further determines whether the lost host is the control host based on the value of the control host ID register: if the lost host is the control host, the value of the control host ID register is updated to 0 based on the value of the control host ID register; if the lost host is not the control host, the control host ID register is not modified.

[0010] Compared with the prior art, the shared resource management system and management method in a multi-host communication mode based on a single-chip network communication board connection structure of the present invention have the following significant advantages: 1. Avoiding access conflicts of public resources. When FPGA is shared by multiple hosts, some resources are used by multiple hosts. If shared resources are to be configured, a synchronization mechanism is required between multiple hosts. The shared resource management system in a multi-host communication mode based on a single-chip network communication board connection proposed by the present invention provides a convenient synchronization access mechanism to avoid access conflicts of public resources. Moreover, the occupancy of public resources is transparent, and the occupant of public resources can be reflected by the value of the lock register, which is convenient for locating synchronization problems. 2. Avoiding repeated operation of public services. Public services only need to run on a single host. For example, time synchronization services only need one host to run and adjust the FPGA clock. If multiple hosts run at the same time, not only will there be a waste of operating resources, but there will also be repeated adjustments, and the resulting clock jitter will affect the clock synchronization performance and function. The shared resource management system in a multi-host communication mode based on a single-chip network communication board connection proposed by the present invention can avoid repeated operation of public services by selecting a control host. Only the control host maintains public services. In addition, the control host has absolute control over a certain public service during operation, avoiding the synchronization overhead of a single operation, and improving management and control efficiency; 3. The shared resource management system in the multi-host communication mode based on the single-chip network communication board connection proposed by the present invention can decouple the status of multiple hosts by selecting the control host. When the FPGA is shared by multiple hosts, the status of a single host should not affect the use of the FPGA by other hosts. If a certain host is fixed as the control host, the operation of other hosts must be based on the operation of the control host. Only after the control host is started can the FPGA be used. If the control host fails, other hosts cannot use it. However, this solution can dynamically update the control host based on the online status of each host, avoiding the impact of single-point failure on other systems.

[0011] It should be understood that all combinations of the aforementioned concepts and the additional concepts described in more detail below can be considered as part of the inventive subject matter of the present disclosure as long as such concepts are not mutually inconsistent. In addition, all combinations of the claimed subject matter are considered as part of the inventive subject matter of the present disclosure.

[0012] The foregoing and other aspects, embodiments and features of the present invention can be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the present invention, such as the features and / or beneficial effects of the exemplary embodiments, will be apparent from the following description or learned from the practice of the specific embodiments according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are not intended to be drawn to scale. In the accompanying drawings, each identical or nearly identical component shown in each figure may be represented by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the present invention will now be described by way of example and with reference to the accompanying drawings.

[0014] Figure 1 It is a schematic diagram of the connection between a network communication board and a host according to an embodiment of the present invention.

[0015] Figure 2 4 is a schematic diagram of a host startup process according to an embodiment of the present invention.

[0016] Figure 3 The flowchart of the host starting to obtain the right to control the host according to an embodiment of the present invention.

[0017] Figure 4 The flowchart of controlling access of a host to a public resource according to an embodiment of the present invention.

[0018] Figure 5 is a flow chart of a control host and a non-control host updating a common resource according to an embodiment of the present invention.

[0019] Figure 6 is a flow chart of a host shutdown process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to better understand the technical content of the present invention, specific embodiments are given and described as follows in conjunction with the accompanying drawings.

[0021] Various aspects of the present invention are described in this disclosure with reference to the accompanying drawings, in which many illustrative embodiments are shown. The embodiments of the present disclosure are not necessarily intended to include all aspects of the present invention. It should be understood that the various concepts and embodiments introduced above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed by the present invention are not limited to any implementation. In addition, some aspects disclosed by the present invention can be used alone or in any appropriate combination with other aspects disclosed by the present invention.

[0022] {Example 1} Combination Figure 1 to Figure 6 As shown, a shared resource management system in a single-chip multi-host communication mode according to an embodiment of the present invention includes a network communication board 100 and a plurality of hosts 200 connected to the network communication board 100, forming a multi-host system.

[0023] The network communication board 100 adopts a main control network chip and FPGA integrated architecture (abbreviated as chip / FPGA for ease of explanation), and provides shared resources for multiple hosts through the chip / FPGA. The shared resources include public services provided by the main control network chip and public resources provided by the FPGA.

[0024] The network communication board 100 is configured with multiple PCIE interfaces and an Ethernet MAC module.

[0025] In a multi-host system, each host 200 is connected to the network communication board 100 via a PCIE interface, and can operate the registers of the FPGA to realize the configuration management of the FPGA, so that the FPGA can complete the corresponding functions; and exchange data packets with the network communication board 100 based on the DMA method to realize network communication. As an example, combining Figure 1 As shown, the chip / FPGA configuration of the network communication board 100 is as follows: -Integrated PCIE processing unit, communicates with the host through PCIE interface; -Integrated Ethernet MAC module, connected to Ethernet network via SFP; -The chip completes the protocol conversion from PCIE to MAC interface, as well as other additional Ethernet hardware offload transactions, such as PTP time synchronization, TSN AV / BV queue management, etc.

[0026] In the embodiment of the present invention, each host is an actual service processing unit or information collection unit, and needs to communicate with other hosts via Ethernet. As an example, the configuration of the host is as follows: -Physically connected to the chip / FPGA via the PCIE interface, the chip / FPGA registers are operated by the driver software to achieve the purpose of configuration management, so that the chip / FPGA can complete the corresponding additional functions; -Exchange data messages with the chip / FPGA through DMA to achieve network communication.

[0027] As an optional embodiment, the host system can be connected to the FPGA / chip through a PCIE adapter board and a PCIE extension cable, or the host and the FPGA / chip can be interconnected through a PCIE expansion board.

[0028] Combination Figure 1 The architecture shown involves, first, the chip or FPGA is powered on to load and run the corresponding logic version, waiting for the host system to connect and manage the configuration.

[0029] Then, after the first host in the multi-host system is powered on, it scans the PCIE interface, allocates the register space for PCIE configuration management to the FPGA, and loads the corresponding driver based on the PCIE device information to complete the management configuration of the FPGA; the configured FPGA board can complete the protocol processing and unloading functions of network communication. The host system communicates with the FPGA through the driver, and the FPGA converts it into an Ethernet frame and sends it to the remote Ethernet device.

[0030] After the other host systems are powered on, they perform PCIE scanning and allocate register space for PCIE configuration management to the FPGA. Since the shared resources between FPGA hosts have been managed and configured by the first host as the control host, other hosts only need to configure the DMA memory related to network communication and can directly complete the network communication process through the FPGA.

[0031] In an embodiment of the present invention, the FPGA is provided with a control host ID register for recording the ID of the host configured as the control host among multiple hosts 200. The control host is configured with control authority over the FPGA to complete the configuration management of the FPGA, and when the control host goes offline / exits abnormally, the value of the control host ID register is modified to 0 to release the control right of the FPGA.

[0032] Furthermore, at any time, only one of the multiple hosts 200 can become a controlling host by modifying the value of the controlling host ID register to the host ID when the value of the controlling host ID register is 0.

[0033] In an embodiment of the present invention, the FPGA is also provided with a plurality of lock registers, each lock register being configured to identify access control of the corresponding shared resource; each host 200 implements access control to the shared resource through the state of the lock register corresponding to the shared resource and read-write arbitration.

[0034] As an optional embodiment, multiple lock registers may be provided to correspond to public services or common resources of different shared resources, and may be configured with different granularities and different locking periods according to the design requirements of the multi-host system.

[0035] For example, a lock register is set for a specific resource, such as fast access to a public peripheral controlled by an FPGA, and the locking and unlocking process can be performed in each access cycle.

[0036] For example, a lock register is set for a certain service, such as the time synchronization service provided by the chip. The host can obtain the lock register when it starts, and hold the lock during the host activity and is responsible for the time synchronization service. In this way, there is no need to frequently obtain and release the lock register during the entire process, which improves the access control efficiency of the FPGA.

[0037] For example, a lock register can also be used to identify the control authority of the entire FPGA (i.e., the control host ID register). When the host starts, it reads the control host ID register. If it is empty (the register value is 0), it can write its own host ID into the lock register and identify itself as the control host. The control host can configure all registers of the FPGA and is responsible for configuring and managing public resources and services. When a non-control host accesses public resources, it sends a resource access write request to the control host, which checks the configuration consistency and completes the update operation.

[0038] {Example 2} Combination Figure 2 , Figure 3 As shown, after each host in the plurality of hosts 200 is started, the host ID register is read to obtain the host ID of the host in the multi-host system, and the host ID is configured as a unique identifier of the host; In response to a request to read the host ID register, the FPGA returns a host ID according to the PCIE interface to which the host is connected. The host ID is any non-zero value, and different PCIE interfaces return different host IDs.

[0039] Furthermore, when any one of the multiple hosts 200 is started, it reads the control host ID register and writes its host ID into the control host ID register if the control host ID register is 0, identifying it as a control host to configure the registers of the FPGA and configure and manage common resources and services.

[0040] Combination Figure 3 When any one of the multiple hosts 200 is started, it reads the control host ID register, and if the control host ID register is not 0, it is identified as a slave and the control host ID in the control host ID register is recorded.

[0041] {Example 3} Combination Figure 4 As shown, when any one of the multiple hosts 200 needs to access the shared resources provided by the network communication board 100, it is configured to proceed in the following manner: The host ID is written into the lock register of the shared resource to be accessed. The FPGA determines whether the lock register is 0. If it is 0, it means that no host currently occupies the shared resource. The FPGA arbitrates the access requests of multiple hosts to the lock register through the read-write arbitration module, and writes a host ID into the lock register according to the arbitration result, indicating that the host has obtained the access right to the shared resource. The host reads the lock register of the shared resource to be accessed and determines whether it is the same as its own host ID: if it is the same, it indicates that the host has obtained the access right to the shared resource to be accessed; if it is different, it indicates that the shared resource is being accessed by other hosts, and it will continue to try to access the lock register after waiting for a predetermined time; When a host obtains the access right to the shared resource to be accessed, when the host controls access to the shared resource, the FPGA determines whether the host ID of the access request is the same as the host ID of the lock register of the shared resource to be accessed: if they are the same, the host is allowed to access the shared resource; if they are different, the access request is ignored; After the host completes resource access, the FPGA clears the lock register of the shared resource to be accessed to 0, indicating the end of control access to the shared resource.

[0042] {Example 4} Combination Figure 5 As shown, when a non-control host among the multiple hosts 200 needs to update a shared resource, it sends a resource write request to the control host. After the control host checks the consistency of the configuration file, the control host completes writing the configuration file into the FPGA to implement the resource update operation.

[0043] As an optional embodiment, when a host needs to update the shared resources provided by the network communication board 100, first determine whether the host is a control host: If the host is determined to be a control host, the FPGA further checks whether the register write request is initiated from the control host: if it is a register write request initiated from the control host, the FPGA configuration is modified according to the register write request to complete the update of the FPGA configuration file; if it is not a write request initiated from the control host, the register write request is ignored; If it is determined that the host is not the control host, the control host ID register is further read. If the value of the control host ID register is not 0, the host sends a register write request to the control host, and the control host checks the consistency of the configuration file and modifies the FPGA configuration file according to the register write request; if the value of the control host ID register is 0, the host ID is written to the control host ID register to identify the host as the control host and obtain the control authority of the FPGA, and then further check whether the register write request is initiated from the control host: if it is a register write request initiated from the control host, the FPGA configuration is modified according to the register write request to complete the update of the FPGA configuration file; if it is a write request not initiated from the control host, the register write request is ignored.

[0044] {Example 5} Combination Figure 6 As shown in the figure, when the control host goes offline / exits abnormally, the value of the control host ID register is changed to 0, releasing the chip control right, including: When any one of the multiple hosts 200 actively goes offline, if the host determines that it is the control host based on the value of the control host ID register: the value of the control host ID register is set to 0, and the FPGA control right is released; If the host exits abnormally, the FPGA detects that the host is disconnected. The FPGA further determines whether the lost host is the control host based on the value of the control host ID register: if the lost host is the control host, the value of the control host ID register is updated to 0 based on the value of the control host ID register; if the lost host is not the control host, the control host ID register is not modified.

[0045] {Example 6} Combination Figure 1 as well as Figure 2 to Figure 6 The exemplary implementation process shown in the figure, according to this embodiment, also proposes a shared resource management and synchronization method in a single-chip connected multi-host communication mode, including the following steps: (1) The network communication board 100 is powered on and runs: The network communication board 100 is powered on and runs, and the FPGA runs the corresponding logic version according to the configuration file in the FLASH, waiting for the host to connect and perform management configuration; (2) Host 200 is powered on and runs: After the first host is powered on, it scans the PCIE interface and obtains the ID information of the host in the multi-host system by reading the host ID register. After receiving the read request, the FPGA returns the host ID information according to the PCIE interface connected to the host. The host ID can be any non-zero value. The host reads the control host ID register and writes its host ID into the control host ID register based on the control host ID register being 0, identifying it as the control host, obtaining the control authority of the FPGA, and being able to perform configuration management of the FPGA and control access to shared resources. After other hosts in the multi-host system are powered on, the FPGA returns the host ID information based on the PCIE interface connected to the host. Different PCIE interfaces return different host IDs. Other hosts identify themselves as slaves based on the value of the control host ID and record the control host ID. (3) The host accesses the shared resources of the network communication board 100 When a host needs to control access to the shared resources provided by the network communication board 100, the host ID is first written into the lock register of the shared resource to be accessed. The FPGA determines whether the lock register is 0. If it is 0, it means that no host currently occupies the shared resource. The FPGA arbitrates the access requests of multiple hosts to the lock register through the read-write arbitration module, and writes a host ID into the lock register according to the arbitration result, indicating that the host has obtained the access right to the shared resource. The host reads the lock register of the shared resource to be accessed and determines whether it is the same as its own host ID: if it is the same, it indicates that the host has obtained the access right to the shared resource to be accessed; if it is different, it indicates that the shared resource is being accessed by other hosts, and it will continue to try to access the lock register after waiting for a predetermined time; When a host obtains the access right to the shared resource to be accessed, when the host controls access to the shared resource, the FPGA determines whether the host ID of the access request is the same as the host ID of the lock register of the shared resource to be accessed: if they are the same, the host is allowed to access the shared resource; if they are different, the access request is ignored; After the host completes resource access, the FPGA clears the lock register of the shared resource to be accessed to 0, indicating that the control access to the shared resource has ended; (4) The host updates the shared resources of the network communication board 100 When a host needs to update the shared resources provided by the network communication board 100, it is first determined whether the host is a control host: If the host is determined to be a control host, the FPGA further checks whether the register write request is initiated from the control host: if it is a register write request initiated from the control host, the FPGA configuration is modified according to the register write request to complete the update of the FPGA configuration file; if it is not a write request initiated from the control host, the register write request is ignored; If it is determined that the host is not the control host, the control host ID register is further read. If the value of the control host ID register is not 0, the host sends a register write request to the control host, and the control host checks the consistency of the configuration file and modifies the FPGA configuration file according to the register write request; if the value of the control host ID register is 0, the host ID is written to the control host ID register to identify the host as the control host and obtain the control authority of the FPGA, and then further check whether the register write request is initiated from the control host: if it is a register write request initiated from the control host, the FPGA configuration is modified according to the register write request to complete the update of the FPGA configuration file; if it is a write request not initiated from the control host, the register write request is ignored.

[0046] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.

Claims

1. A shared resource management system in a single-chip multi-host communication mode, characterized in that: It comprises a network communication board (100) and a plurality of hosts (200) connected to the network communication board (100), forming a multi-host system; The network communication board (100) adopts a main control network chip and FPGA integrated architecture, and provides shared resources for multiple hosts through the main control network chip and FPGA, wherein the shared resources include public services provided by the main control network chip and public resources provided by the FPGA; the network communication board (100) is configured with multiple PCIE interfaces and Ethernet MAC modules; The host is connected to the network communication board (100) via a PCIE interface, and can operate the register of the FPGA to implement configuration management of the FPGA, so that the FPGA completes corresponding functions; and exchanges data messages with the network communication board (100) based on the DMA method to implement network communication; The FPGA is provided with a control host ID register for recording the ID of the multiple hosts (200) configured as the control host, the control host is configured with control authority over the FPGA to complete configuration management of the FPGA, and when the control host goes offline / exits abnormally, the value of the control host ID register is modified to 0 to release the control authority of the FPGA; At any time, one and only one of the plurality of hosts (200) can become a control host by modifying the value of the control host ID register to the host ID when the value of the control host ID register is 0; The FPGA is also provided with a plurality of lock registers, each lock register being configured to identify access control of a corresponding shared resource; each host (200) implements access control of a shared resource through the state of the lock register corresponding to the shared resource and read-write arbitration.

2. The shared resource management system in a single-chip-connected-multiple-host communication mode according to claim 1, characterized in that: After each of the plurality of hosts (200) is started, the host ID register is read to obtain the host ID of the host in the multi-host system, wherein the host ID is configured as a unique identifier of the host; In response to a request to read the host ID register, the FPGA returns a host ID according to the PCIE interface to which the host is connected. The host ID is any non-zero value, and different PCIE interfaces return different host IDs.

3. The shared resource management system in a single-chip-connected-multiple-host communication mode according to claim 1, characterized in that: When any one of the plurality of hosts (200) is started up, it reads the control host ID register and writes its host ID into the control host ID register based on the control host ID register being 0, thereby identifying it as a control host, so as to configure the registers of the FPGA and configure and manage common resources and services.

4. The shared resource management system in a single-chip-connected-multiple-host communication mode according to claim 3, characterized in that: When any one of the plurality of hosts (200) is started up, it reads the control host ID register, and if the control host ID register is not 0, it is identified as a slave and the control host ID in the control host ID register is recorded.

5. The shared resource management system in a single-chip-connected-multiple-host communication mode according to claim 1, characterized in that: When any one of the plurality of hosts (200) needs to access the shared resources provided by the network communication board (100), it is configured to perform the operation in the following manner: The host ID is written into the lock register of the shared resource to be accessed. The FPGA determines whether the lock register is 0. If it is 0, it means that no host currently occupies the shared resource. The FPGA arbitrates the access requests of multiple hosts to the lock register through the read-write arbitration module, and writes a host ID into the lock register according to the arbitration result, indicating that the host has obtained the access right to the shared resource. The host reads the lock register of the shared resource to be accessed and determines whether it is the same as its own host ID: if it is the same, it indicates that the host has obtained the access right to the shared resource to be accessed; if it is different, it indicates that the shared resource is being accessed by other hosts, and it will continue to try to access the lock register after waiting for a predetermined time; When a host obtains the access right to the shared resource to be accessed, when the host controls access to the shared resource, the FPGA determines whether the host ID of the access request is the same as the host ID of the lock register of the shared resource to be accessed: if they are the same, the host is allowed to access the shared resource; if they are different, the access request is ignored; After the host completes resource access, the FPGA clears the lock register of the shared resource to be accessed to 0, indicating the end of control access to the shared resource.

6. The shared resource management system in a single-chip-connected-multiple-host communication mode according to claim 1, characterized in that: When a non-control host among the multiple hosts (200) needs to update a shared resource, a resource write request is sent to the control host. After the control host checks the consistency of the configuration file, the control host completes writing the configuration file into the FPGA to implement a resource update operation.

7. The shared resource management system in a single-chip-connected-multiple-host communication mode according to claim 1, characterized in that: When the control host goes offline / exits abnormally, the value of the control host ID register is modified to 0, releasing the chip control right, including: When any one of the multiple hosts (200) actively goes offline, if the host determines that it is the control host based on the value of the control host ID register: the value of the control host ID register is set to 0, and the FPGA control right is released; If the host exits abnormally, the FPGA detects that the host is disconnected. The FPGA further determines whether the lost host is the control host based on the value of the control host ID register: if the lost host is the control host, the value of the control host ID register is updated to 0 based on the value of the control host ID register; if the lost host is not the control host, the control host ID register is not modified.

8. A shared resource management and synchronization method in a single-chip-connected multi-host communication mode based on a shared resource management system in a single-chip-connected multi-host communication mode according to any one of claims 1 to 7, characterized in that: The following steps are involved: (1) The network communication board (100) is powered on and runs: The network communication board (100) is powered on and runs, and the FPGA runs the corresponding logic version according to the configuration file in the FLASH, waits for the host to connect and perform management configuration; (2) The host (200) is powered on and runs: After the first host is powered on, it scans the PCIE interface and obtains the ID information of the host in the multi-host system by reading the host ID register. After receiving the read request, the FPGA returns the host ID information according to the PCIE interface connected to the host. The host ID can be any non-zero value. The host reads the control host ID register and writes its host ID into the control host ID register based on the control host ID register being 0, identifying it as the control host, obtaining the control authority of the FPGA, and being able to perform configuration management of the FPGA and control access to shared resources. After other hosts in the multi-host system are powered on, the FPGA returns the host ID information based on the PCIE interface to which the host is connected. Different PCIE interfaces return different host IDs. Other hosts identify themselves as slaves based on the value of the control host ID and record the control host ID; (3) The host accesses the shared resources of the network communication board (100) When a host needs to control access to a shared resource provided by a network communication board (100), the host ID is first written into a lock register of the shared resource to be accessed, and the FPGA determines whether the lock register is 0. If it is 0, it indicates that no host currently occupies the shared resource. The FPGA arbitrates access requests of multiple hosts to the lock register through a read-write arbitration module, and writes a host ID into the lock register according to the arbitration result, indicating that the host has obtained the right to access the shared resource; The host reads the lock register of the shared resource to be accessed and determines whether it is the same as its own host ID: if it is the same, it indicates that the host has obtained the access right to the shared resource to be accessed; if it is different, it indicates that the shared resource is being accessed by other hosts, and it will continue to try to access the lock register after waiting for a predetermined time; When a host obtains the access right to the shared resource to be accessed, when the host controls access to the shared resource, the FPGA determines whether the host ID of the access request is the same as the host ID of the lock register of the shared resource to be accessed: if they are the same, the host is allowed to access the shared resource; if they are different, the access request is ignored; After the host completes resource access, the FPGA clears the lock register of the shared resource to be accessed to 0, indicating that the control access to the shared resource has ended; (4) The host updates the shared resources of the network communication board (100) When a host needs to update the shared resources provided by the network communication board (100), it first determines whether the host is a control host: If the host is determined to be a control host, the FPGA further checks whether the register write request is initiated from the control host: if it is a register write request initiated from the control host, the FPGA configuration is modified according to the register write request to complete the update of the FPGA configuration file; if it is not a write request initiated from the control host, the register write request is ignored; If the host is not the control host, the control host ID register is further read. If the value of the control host ID register is non-0, the host sends a register write request to the control host, which checks the consistency of the configuration file and modifies the FPGA configuration file according to the register write request. If the value of the control host ID register is 0, the host ID is written to the control host ID register to identify the host as the control host and obtain the control authority of the FPGA, and then further check whether the register write request is initiated from the control host: If the register write request is initiated from the control host, the configuration of the FPGA is modified according to the register write request to complete the update of the FPGA configuration file; if the write request is not initiated from the control host, the register write request is ignored.

9. The shared resource management and synchronization method in a single-chip-connected-to-multiple-hosts communication mode according to claim 8, characterized in that: The method further comprises the following steps: When the control host goes offline / exits abnormally, the value of the control host ID register is changed to 0 to release the chip control right.

10. The shared resource management and synchronization method in a single-chip-connected-to-multiple-hosts communication mode according to claim 8, characterized in that: When the control host goes offline / exits abnormally, the value of the control host ID register is modified to 0, and the chip control right is released, including: When any one of the multiple hosts (200) actively goes offline, if the host determines that it is the control host based on the value of the control host ID register: the value of the control host ID register is set to 0, and the FPGA control right is released; If the host exits abnormally, the FPGA detects that the host is disconnected. The FPGA further determines whether the lost host is the control host based on the value of the control host ID register: if the lost host is the control host, the value of the control host ID register is updated to 0 based on the value of the control host ID register; if the lost host is not the control host, the control host ID register is not modified.

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