Slope control circuit, chip and electronic equipment

Abstract

The invention belongs to the technical field of electronic circuits, and provides a slope control circuit, a chip and electronic equipment. The circuit comprises a coupling module, a first switch module, a second switch module, a Miller compensation module and a logic module, and the logic module is connected with the coupling module, the second switch module, the Miller compensation module, a controller and a grid electrode of a first field effect transistor. The first switch module is connected with the second switch module, the Miller compensation module and the drain electrode of the first field effect transistor. The logic module outputs a first voltage signal, a second voltage signal and a third voltage signal according to a first level signal output by the controller; the coupling module outputs a coupling signal according to the first voltage signal, so that the first field effect transistor enters a saturation region; the Miller compensation module reduces the rising speed of the grid voltage of the first field effect transistor after the first field effect transistor enters the saturation region; the first switch module is switched on according to the second level signal, so that the second switch module is switched on according to the second voltage signal and the third voltage signal.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits, and in particular, relates to a slope control circuit, a chip and an electronic device. Background Art

[0002] In integrated circuit applications, the chips or MCUs (Microcontroller Units) working together at each level and the slave chips need to transmit data through I / O (Input / Output) ports. 2 Taking IC (Inter-Integrated Circuit) communication as an example, data transmission between devices connected to the bus is achieved through serial data line (SDA) and serial clock line (SCL). The output stage of the device connected to the bus adopts an open-drain structure.

[0003] When the open drain of the I / O port is cut off, the power supply charges the parasitic capacitance through the pull-up resistor and pulls the bus high. Usually, the RC time constant is large, the rising edge is relatively gentle, and the rising slope is small. When the open drain of the I / O port is turned on, the bus is pulled low through the pull-down tube. In order to ensure the accuracy of the data, the low-level voltage of the I / O port must be less than 0.4V, which makes the on-resistance of the I / O port very small, then the RC time constant is small, the falling edge is relatively steep, and the falling slope is large, resulting in a large difference in the slope of the rising edge and the falling edge, serious asymmetry of the waveform, and shift in the signal duty cycle. At the same time, due to the parasitic inductance and capacitance between the MCU and the slave chip, when the SDA falls too fast, the voltage on the bus will undershoot and oscillate, which may cause damage to the MCU. In addition, due to the I 2 The C protocol stipulates that both the fast mode and the high-speed mode output stage need to have a slope control circuit. Therefore, how to propose a slope control circuit is an urgent problem to be solved. Summary of the invention

[0004] The embodiments of the present application provide a slope control circuit, chip and electronic device, which can solve the problem that the SDA decreases too fast, causing the bus voltage to undershoot and oscillate, and the slope difference between the rising edge and the falling edge is large.

[0005] In a first aspect, an embodiment of the present application provides a slope control circuit, comprising a coupling module, a first switch module, a second switch module, a Miller compensation module and a logic module, wherein the logic module is respectively connected to the coupling module, the second switch module, the Miller compensation module, a controller and a gate of a first field effect transistor in an I / O port, and the first switch module is respectively connected to the second switch module, the Miller compensation module and a drain of the first field effect transistor; The logic module is used to output a first voltage signal, a second voltage signal and a third voltage signal according to a first level signal output by the controller; the coupling module is used to output a coupling signal according to the first voltage signal, so that the first field effect transistor enters a saturation region; the Miller compensation module is used to reduce a rising speed of a gate voltage of the first field effect transistor after the first field effect transistor enters a saturation region; the first switch module is used to be turned on according to a second level signal, so that the second switch module is turned on according to the second voltage signal and the third voltage signal.

[0006] In a possible implementation of the first aspect, the coupling module includes a first capacitor and a second capacitor, the first end of the first capacitor is connected to the logic module, the second end of the first capacitor is respectively connected to the first end of the second capacitor, the Miller compensation module, the second switch module, the logic module and the gate of the first field effect transistor, and the second end of the second capacitor is grounded.

[0007] In a possible implementation of the first aspect, the first switch module includes a second field effect transistor and a first resistor, the first end of the first resistor is respectively connected to the Miller compensation module and the drain of the first field effect transistor, the second end of the first resistor is connected to the gate of the second field effect transistor, the drain of the second field effect transistor is connected to the second switch module, and the source of the second field effect transistor is grounded.

[0008] In a possible implementation of the first aspect, the second switch module includes a third field effect transistor, a gate of the third field effect transistor is respectively connected to the logic module, the coupling module, the Miller compensation module and the gate of the first field effect transistor, a source of the third field effect transistor is connected to the logic module, and a drain of the third field effect transistor is connected to the first switch module.

[0009] In a possible implementation of the first aspect, the Miller compensation module includes a third capacitor and a second resistor, the first end of the third capacitor is connected to the drain of the first field effect transistor, the second end of the third capacitor is connected to the first end of the second resistor, and the second end of the second resistor is respectively connected to the coupling module, the second switch module, the logic module and the gate of the first field effect transistor.

[0010] In a possible implementation manner of the first aspect, the logic module includes a first logic unit and a second logic unit, the first logic unit is connected to the second logic unit and the controller respectively, and the second logic unit is connected to the coupling module, the second switch module, the Miller compensation module, and the gate of the first field effect transistor respectively; The first logic unit is used to output a first logic signal according to a first level signal output by the controller; the second logic unit is used to output a first voltage signal, a second voltage signal and a third voltage signal according to the first logic signal.

[0011] In a possible implementation of the first aspect, the first logic unit includes a NAND gate and a NOR gate, the first input terminal and the second input terminal of the NAND gate are both used to connect to the controller, the output terminal of the NAND gate is connected to the input terminal of the NOR gate, and the output terminal of the NOR gate is connected to the second logic unit.

[0012] In a possible implementation manner of the first aspect, the second logic unit includes a fourth field effect transistor, a fifth field effect transistor, a third resistor and a fourth resistor, the gate of the fourth field effect transistor is respectively connected to the gate of the fifth field effect transistor and the first logic unit, the source of the fourth field effect transistor is connected to a power supply, the drain of the fourth field effect transistor is respectively connected to the coupling module and the first end of the third resistor, the second end of the third resistor is respectively connected to the second switch module and the first end of the fourth resistor, the second end of the fourth resistor is respectively connected to the drain of the fifth field effect transistor, the second switch module, the coupling module, the Miller compensation module and the gate of the first field effect transistor, and the source of the fifth field effect transistor is grounded.

[0013] In a second aspect, an embodiment of the present application provides a chip, comprising the slope control circuit described in any one of the first aspects.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, comprising the chip described in any one of the second aspects.

[0015] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: An embodiment of the present application provides a slope control circuit, including a coupling module, a first switch module, a second switch module, a Miller compensation module and a logic module, wherein the logic module is respectively connected to the coupling module, the second switch module, the Miller compensation module, a controller and a gate of a first field effect transistor in an I / O port, and the first switch module is respectively connected to the second switch module, the Miller compensation module and a drain of the first field effect transistor.

[0016] When the controller wants to transmit data through the bus, the logic module is used to output the first voltage signal, the second voltage signal and the third voltage signal according to the first level signal output by the controller. The coupling module is used to output the coupling signal according to the first voltage signal, so that the first field effect tube enters the saturation region. The Miller compensation module is used to reduce the rising speed of the gate voltage of the first field effect tube after the first field effect tube enters the saturation region, so as to extend the time that the first field effect tube is in the saturation region, thereby reducing the falling speed of SDA and making the falling slope smaller. At the same time, the first switch module is used to conduct according to the second level signal (the second level signal is the level signal on SDA), so that the second switch module is turned on according to the second voltage signal and the third voltage signal. After the second switch module is turned on, the current flowing into the coupling module will be shunted, so that the current flowing into the coupling module is reduced, resulting in a reduction in the charging current of the gate of the first field effect tube, thereby extending the time that the first field effect tube is in the saturation region, thereby reducing the falling speed of SDA and making the falling slope smaller.

[0017] From the above, it can be seen that the present application realizes the control of the falling slope of SDA by prolonging the time that the first field effect tube is in the saturation zone, thereby avoiding the problem of undershoot and oscillation of the bus voltage caused by the rapid decline speed of SDA, and also avoids the problem of large difference in the slope of the rising edge and the falling edge.

[0018] It can be understood that the beneficial effects of the second to third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0020] Figure 1 Is the device connected to I 2 C bus schematic diagram; Figure 2 It is a schematic diagram of the process of changing the bus signal to a high level; Figure 3 It is a schematic diagram of the process of pulling the bus signal low; Figure 4 This is a schematic diagram of the SDA flip model; Figure 5 This is a waveform diagram of SDA; Figure 6 This is the circuit block diagram of the SDA port; Figure 7is a principle block diagram of a slope control circuit provided in an embodiment of the present application; Figure 8 is a principle block diagram of a slope control circuit provided in another embodiment of the present application; Fig. 9 is a circuit connection diagram of a slope control circuit provided in an embodiment of the present application; Fig.10 It is a schematic diagram of the relationship between the conduction state of the first field effect tube and the falling slope of SDA in this application.

[0021] In the figure: 1. slope control circuit; 10. coupling module; 20. first switch module; 30. second switch module; 40. Miller compensation module; 50. logic module; 51. first logic unit; 52. second logic unit; 2. controller; 3. I / O port. DETAILED DESCRIPTION

[0022] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0023] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0024] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0025] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0026] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0027] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0028] In integrated circuit applications, chips at all levels or MCUs and slave chips need to transmit data through I / O ports. Figure 1 As shown, the most widely used I 2 C communication as an example, the data transmission between the devices connected to the bus is realized through the serial data line (SDA) and the serial clock line (SCL). The output stage of the device connected to the bus adopts an open-drain structure. When data transmission is performed, the bus is pulled down to a low level, such as Figure 3 As shown; when the bus is idle, SDA and SCL are pulled up by resistors R PU Pull the bus up to VDD, such as Figure 2 shown.

[0029] When the open drain of the I / O port is turned off, VDD is pulled up by the resistor R PU For parasitic capacitance C b Charging, pull the bus high, usually the RC time constant is large, the rising edge is relatively gentle, and the rising slope is small; when the open drain of the I / O port is turned on, the bus is pulled down through the pull-down tube. In order to ensure the accuracy of the data, the low-level voltage of the I / O port must be less than 0.4V, which makes the on-resistance of the I / O port very small, then the RC time constant is small, the falling edge is relatively steep, and the falling slope is large, resulting in a large difference in the slope of the rising edge and the falling edge, serious asymmetry of the waveform, and the signal duty cycle is offset. At the same time, due to the parasitic inductance and capacitance between the MCU and the slave chip, when the SDA falls too fast, the voltage on the bus will undershoot and oscillate, which may cause damage to the MCU. Usually a resistor Rs is connected in series with the open drain structure to reduce the impact of voltage changes on the bus on the I / O port, but this will increase the cost. And because I 2 The C protocol stipulates that both the fast mode and the high-speed mode output stage need to have a slope control circuit. Therefore, how to propose a slope control circuit is an urgent problem to be solved.

[0030] Based on this, the present application proposes a slope control circuit for adjusting the falling slope of the I / O port so that the falling time of the I / O port is only affected by the pull-up resistor R PU and parasitic capacitance C b This can reduce the impact of SDA falling too fast, causing the bus voltage to undershoot and oscillate, and avoid the problem of a large difference in the slope of the rising and falling edges.

[0031] The SDA flip model can be simplified as Figure 4 As shown, C b is the parasitic capacitance of the bus. When the first field effect transistor M1 is turned off, VDD is pulled up by the pull-up resistor R PU For parasitic capacitance C b For charging, the time calculation formula for the SDA rising edge is: ; ; ; in, is 0.3 times VDD, is 0.7 times of VDD, t1 is the time it takes for SDA to rise to 0.3 times of VDD, t2 is the time it takes for SDA to rise to 0.7 times of VDD, t r is the time of the SDA rising edge, 0.3 and 0.7 are I 2 The threshold value specified by the C protocol, e is the base of the natural logarithm.

[0032] From the above, we can see that the rising edge time is mainly affected by the pull-up resistor R PU and parasitic capacitance C b When the first field effect tube M1 is turned on, the falling speed of SDA is determined by the pull-down capability of the first field effect tube M1. 2 The C protocol stipulates that the maximum value of the low-level voltage VOL in fast mode is 0.4V, the pull-down current is 3mA, and the maximum on-resistance of the first field effect transistor M1 is 133Ω. Taking fast mode as an example, =200pF, =300ns, VDD=5V, calculate the pull-up resistor R PU Range: kΩ; kΩ; According to the common chip resistor values, the pull-up resistor R is finally selected. PU is 1.6kΩ, parasitic capacitance C b For 50pF, the rising edge time is about 67.76ns.

[0033] The circuit diagram of the SDA port (also known as the I / O port) is as follows Figure 6 As shown in the figure, when the MCU accesses the slave chip, the external signal enters the internal circuit of the slave chip through the PAD_SDA pin, and after filtering, the output SDA_DEG signal is sent to the digital circuit of the slave chip; when the slave chip sends data to the MCU, the controller of the slave chip outputs the SDA_OUT signal, and the SDA_OUT signal controls the first field effect transistor M1 to turn on after logic control processing, so as to pull down the bus. The falling slope of SDA is shown in Figure 5 As shown, from Figure 5 It can be seen that the falling slope of SDA is quite different from the rising slope of SDA, and the waveform of SDA is seriously asymmetric. The slope control circuit proposed in this application adjusts the falling slope of the I / O port by controlling the gate voltage of the first field effect transistor M1. The falling slope of SDA after adjustment is as follows: Figure 5 As shown in the dotted line part.

[0034] The slope control circuit proposed in this application is as follows Figure 7 As shown, the slope control circuit 1 includes a coupling module 10, a first switch module 20, a second switch module 30, a Miller compensation module 40 and a logic module 50. The logic module 50 is respectively connected to the coupling module 10, the second switch module 30, the Miller compensation module 40, the controller 2 and the gate of the first field effect transistor M1 in the I / O port 3, and the first switch module 20 is respectively connected to the second switch module 30, the Miller compensation module 40 and the drain of the first field effect transistor M1.

[0035] Specifically, when the controller 2 wants to transmit data through the bus, the controller 2 will output a first level signal to the logic module 50, wherein the first level signal is a low level. The logic module 50 is used to output a first voltage signal, a second voltage signal and a third voltage signal according to the first level signal, wherein the first voltage signal is greater than the second voltage signal, and the second voltage signal is greater than the third voltage signal. The coupling module 10 is used to output a coupling signal according to the first voltage signal so that the first field effect tube M1 enters the saturation region. The Miller compensation module 40 is used to reduce the rising speed of the gate voltage of the first field effect tube M1 after the first field effect tube M1 enters the saturation region, so as to extend the time that the first field effect tube M1 is in the saturation region, thereby reducing the falling speed of SDA and reducing the falling slope. At the same time, the first switch module 20 is used to be turned on according to the second level signal (the second level signal is the level signal on SDA, and the level signal on SDA is a high level at this time), so that the second switch module 30 is turned on according to the second voltage signal and the third voltage signal. After the second switch module 30 is turned on, the current flowing into the coupling module 10 will be shunted, so that the current flowing into the coupling module 10 is reduced, resulting in a reduction in the charging current of the gate of the first field effect transistor M1, thereby prolonging the time that the first field effect transistor M1 is in the saturation region, thereby reducing the falling speed of SDA and making the falling slope smaller.

[0036] From the above, it can be seen that the present application realizes the control of the falling slope of SDA by prolonging the time that the first field effect tube M1 is in the saturation zone, thereby avoiding the problem of undershoot and oscillation of the bus voltage caused by the rapid decline speed of SDA, and also avoids the problem of large difference in the slope of the rising edge and the falling edge.

[0037] It should be noted that the I / O port 3 is the I / O port of the chip, the controller 2 is arranged inside the chip, and the chip can be a slave chip or an MCU.

[0038] As the gate voltage of the first field effect tube M1 increases, the drain voltage (that is, the SDA voltage) decreases, and the first field effect tube M1 eventually enters the linear region. When the first field effect tube M1 enters the linear region, the second switch module 30 is disconnected, the effect of the Miller compensation module 40 disappears, and the charging current of the gate of the first field effect tube M1 increases (that is, the gate voltage of the first field effect tube M1 increases), and the falling slope of SDA increases. As the gate voltage of the first field effect tube M1 increases, the charging current flowing from the logic module 50 to the gate of the first field effect tube M1 decreases, and the rising speed of the gate voltage of the first field effect tube M1 slows down, and the falling slope of SDA decreases.

[0039] When the first field effect transistor M1 is in the saturation region, the SDA voltage starts to decrease. The present application mainly controls the SDA decreasing slope by extending the time when the first field effect transistor M1 is in the saturation region.

[0040] In some embodiments, Figure 8 As shown, the logic module 50 includes a first logic unit 51 and a second logic unit 52. The first logic unit 51 is connected to the second logic unit 52 and the controller 2 respectively, and the second logic unit 52 is connected to the coupling module 10, the second switch module 30, the Miller compensation module 40 and the gate of the first field effect transistor M1 respectively.

[0041] Specifically, when the controller 2 wants to transmit data through the bus, the controller 2 outputs a first level signal to the logic module 50, wherein the first level signal is a low level. The first logic unit 51 is used to output a first logic signal according to the first level signal, wherein the first logic signal is a low level. The second logic unit 52 is used to output a first voltage signal, a second voltage signal, and a third voltage signal according to the first logic signal.

[0042] In some embodiments, Fig. 9 As shown, the first logic unit 51 includes a NAND gate and a NOR gate, the first input and the second input of the NAND gate are both used to connect to the controller 2, the output of the NAND gate is connected to the input of the NOR gate, and the output of the NOR gate is connected to the second logic unit 52.

[0043] In some embodiments, Fig. 9 As shown, the second logic unit 52 includes a fourth field effect transistor M4, a fifth field effect transistor M5, a third resistor R3 and a fourth resistor R4, the gate of the fourth field effect transistor M4 is respectively connected to the gate of the fifth field effect transistor M5 and the output end of the NOR gate in the first logic unit 51, the source of the fourth field effect transistor M4 is connected to the power supply, the drain of the fourth field effect transistor M4 is respectively connected to the coupling module 10 and the first end of the third resistor R3, the second end of the third resistor R3 is respectively connected to the second switch module 30 and the first end of the fourth resistor R4, the second end of the fourth resistor R4 is respectively connected to the drain of the fifth field effect transistor M5, the second switch module 30, the coupling module 10, the Miller compensation module 40 and the gate of the first field effect transistor M1, and the source of the fifth field effect transistor M5 is grounded.

[0044] In some embodiments, the coupling module 10 includes a first capacitor C1 and a second capacitor C2, the first end of the first capacitor C1 is connected to the drain of the fourth field effect transistor M4 in the logic module 50, the second end of the first capacitor C1 is respectively connected to the first end of the second capacitor C2, the Miller compensation module 40, the second switch module 30, the second end of the fourth resistor R4 in the logic module 50 and the gate of the first field effect transistor M1, and the second end of the second capacitor C2 is grounded.

[0045] In some embodiments, the first switch module 20 includes a second field effect transistor M2 and a first resistor R1, the first end of the first resistor R1 is connected to the Miller compensation module 40 and the drain of the first field effect transistor M1 respectively, the second end of the first resistor R1 is connected to the gate of the second field effect transistor M2, the drain of the second field effect transistor M2 is connected to the second switch module 30, and the source of the second field effect transistor M2 is grounded. The first resistor R1 is an ESD (Electrostatic Discharge) resistor, which is used to protect the circuit from damage caused by electrostatic discharge.

[0046] In some embodiments, the second switch module 30 includes a third field effect transistor M3, the gate of the third field effect transistor M3 is respectively connected to the second end of the fourth resistor R4 in the logic module 50, the second end of the first capacitor C1 in the coupling module 10, the Miller compensation module 40 and the gate of the first field effect transistor M1, the source of the third field effect transistor M3 is connected to the second end of the third resistor R3 in the logic module 50, and the drain of the third field effect transistor M3 is connected to the drain of the second field effect transistor M2 in the first switch module 20.

[0047] In some embodiments, the Miller compensation module 40 includes a third capacitor C3 and a second resistor R2, wherein the first end of the third capacitor C3 is connected to the drain of the first field effect transistor M3, the second end of the third capacitor C3 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is respectively connected to the second end of the first capacitor C1 in the coupling module 10, the gate of the third field effect transistor M3 in the second switch module 30, the second end of the fourth resistor R4 in the logic module 50, and the gate of the first field effect transistor M1. Among them, the third capacitor C3 is a Miller capacitor, and the second resistor R2 is a zero adjustment resistor.

[0048] Combine the following Fig. 9 and Fig.10 The working principle of this application is explained again.

[0049] The SDA_OUT signal is a signal output by the controller 2, and the SDA_OUT signal includes a first level signal and a third level signal, wherein the first level signal is a low level and the third level signal is a high level. When the SDA_OUT signal is a high level, the voltages at points A and B are both low, and the voltage difference between the first capacitor C1 and the second capacitor C2 is 0. Since the signal on SDA is a high level (i.e., a second level signal), the second field effect transistor M2 is in a conducting state. When the SDA_OUT signal is a low level, it means that the controller 2 wants to perform data transmission, the voltage at point A rises to approximately equal to the power supply voltage VDD, the voltage at point B (i.e., the second voltage signal) is equal to the voltage at point A (i.e., the first voltage signal) minus the voltage drop across the third resistor R3, and the voltage at point C (i.e., the third voltage signal) is equal to the voltage at point B minus the voltage drop across the fourth resistor R4, then the third field effect transistor M3 is turned on. Since the voltage across the capacitor cannot change suddenly, the gate voltage of the first field effect tube M1 will be coupled to a certain voltage by the capacitor. In order to make the first field effect tube M1 turn on quickly, by designing the capacitance ratio of the first capacitor C1 and the second capacitor C2, the gate voltage of the first field effect tube M1 is coupled to the vicinity of the turn-on threshold voltage Vth, and the first field effect tube M1 enters the saturation region, and the SDA voltage begins to decrease. For the first field effect tube M1 in the saturation region, the Miller effect will amplify the intrinsic gain of the third capacitor C3 at the gate equivalently by times, so the gate equivalent capacitance of the first field effect tube M1 increases, resulting in a slow rise speed of the gate voltage of the first field effect tube M1; at the same time, the third field effect tube M3 will draw current from the third resistor R3 when it is turned on, resulting in a decrease in the charging current of the gate of the first field effect tube M1, and the time the first field effect tube M1 is in the saturation region will increase, and the slope of the SDA voltage decreases. As the gate voltage of the first field effect tube M1 increases, the drain voltage decreases, and the first field effect tube M1 eventually enters the linear region, the Miller effect disappears, the gate equivalent capacitance of the first field effect tube M1 decreases (that is, the rising speed of the gate voltage of the first field effect tube M1 is accelerated), and the third field effect tube M3 is turned off, and no current is drawn from the third resistor R3, then the charging current of the gate of the first field effect tube M1 increases, and the falling slope of SDA increases. The voltage at point A increases, the drain current of the fourth field effect tube M4 decreases, the rising rate of the gate voltage of the first field effect tube M1 slows down, and the falling slope of SDA decreases. When the first field effect tube M1 is in the saturation region, the SDA voltage begins to decrease. The present application mainly controls the falling slope of SDA by extending the time when the first field effect tube M1 is in the saturation region.

[0050] In summary, the slope control circuit provided in the embodiment of the present application realizes the adjustment of the slope of the falling edge of the I / O port by segmented control of the gate voltage of the first field effect transistor M1, thereby avoiding the problem of undershoot of the bus voltage due to too fast a falling speed and a large difference between the slopes of the rising edge and the falling edge, thereby ensuring that the duty cycle of the signal at the receiving end will not be offset.

[0051] The present application also provides a chip including the slope control circuit described above. Since the chip provided in the present application adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0052] Exemplarily, the chip includes a slave chip or an MCU.

[0053] The embodiment of the present application also provides an electronic device, including the chip described above. Since the electronic device provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0054] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0055] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A slope control circuit, characterized in that: It includes a coupling module, a first switch module, a second switch module, a Miller compensation module and a logic module, wherein the logic module is respectively connected to the coupling module, the second switch module, the Miller compensation module, a controller and a gate of a first field effect transistor in an I / O port, and the first switch module is respectively connected to the second switch module, the Miller compensation module and a drain of the first field effect transistor; The logic module is used to output a first voltage signal, a second voltage signal and a third voltage signal according to a first level signal output by the controller; the coupling module is used to output a coupling signal according to the first voltage signal, so that the first field effect transistor enters a saturation region; the Miller compensation module is used to reduce a rising speed of a gate voltage of the first field effect transistor after the first field effect transistor enters a saturation region; the first switch module is used to be turned on according to a second level signal, so that the second switch module is turned on according to the second voltage signal and the third voltage signal.

2. The slope control circuit according to claim 1, characterized in that: The coupling module includes a first capacitor and a second capacitor, the first end of the first capacitor is connected to the logic module, the second end of the first capacitor is respectively connected to the first end of the second capacitor, the Miller compensation module, the second switch module, the logic module and the gate of the first field effect transistor, and the second end of the second capacitor is grounded.

3. The slope control circuit according to claim 1, characterized in that: The first switch module includes a second field effect transistor and a first resistor, the first end of the first resistor is respectively connected to the Miller compensation module and the drain of the first field effect transistor, the second end of the first resistor is connected to the gate of the second field effect transistor, the drain of the second field effect transistor is connected to the second switch module, and the source of the second field effect transistor is grounded.

4. The slope control circuit according to claim 1, characterized in that: The second switch module includes a third field effect transistor, the gate of the third field effect transistor is respectively connected to the logic module, the coupling module, the Miller compensation module and the gate of the first field effect transistor, the source of the third field effect transistor is connected to the logic module, and the drain of the third field effect transistor is connected to the first switch module.

5. The slope control circuit according to claim 1, characterized in that: The Miller compensation module includes a third capacitor and a second resistor, the first end of the third capacitor is connected to the drain of the first field effect transistor, the second end of the third capacitor is connected to the first end of the second resistor, and the second end of the second resistor is respectively connected to the coupling module, the second switch module, the logic module and the gate of the first field effect transistor.

6. The slope control circuit according to claim 1, characterized in that: The logic module includes a first logic unit and a second logic unit, the first logic unit is connected to the second logic unit and the controller respectively, and the second logic unit is connected to the coupling module, the second switch module, the Miller compensation module and the gate of the first field effect transistor respectively; The first logic unit is used to output a first logic signal according to the first level signal output by the controller; The second logic unit is used to output a first voltage signal, a second voltage signal and a third voltage signal according to the first logic signal.

7. The slope control circuit according to claim 6, characterized in that: The first logic unit includes a NAND gate and a NOR gate, the first input and the second input of the NAND gate are both used to connect to the controller, the output of the NAND gate is connected to the input of the NOR gate, and the output of the NOR gate is connected to the second logic unit.

8. The slope control circuit according to claim 6, characterized in that: The second logic unit includes a fourth field effect transistor, a fifth field effect transistor, a third resistor and a fourth resistor. The gate of the fourth field effect transistor is respectively connected to the gate of the fifth field effect transistor and the first logic unit, the source of the fourth field effect transistor is connected to a power supply, the drain of the fourth field effect transistor is respectively connected to the coupling module and the first end of the third resistor, the second end of the third resistor is respectively connected to the second switch module and the first end of the fourth resistor, the second end of the fourth resistor is respectively connected to the drain of the fifth field effect transistor, the second switch module, the coupling module, the Miller compensation module and the gate of the first field effect transistor, and the source of the fifth field effect transistor is grounded.

9. A chip, characterized in that: The invention comprises the slope control circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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