Interrupt system verification method and device and storage medium

Abstract

The invention relates to an interrupt system verification method and device and a storage medium. The method comprises the following steps: acquiring a first standard file, wherein the first standard file comprises interrupt signal information; analyzing based on the first standard file to obtain a second standard file matched with the verification tool in the preset form, the second standard file comprising transmission path description of the interrupt signal; and performing interruption path correctness verification based on the second standard file by using a preset form verification tool to obtain an interruption path verification result. According to the embodiment of the invention, the method facilitates the maintenance and modification of the interrupt system, guarantees the iteration quality, enables different interrupt system verification items to be reused, can achieve the automatic interrupt system verification process, and improves the verification efficiency. The time overhead and machine resource overhead (including machine computing resources and machine storage resources) of interrupt system verification are greatly reduced, the workload is reduced, and the error probability is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an interrupt system verification method, device and storage medium. Background Art

[0002] In a modern system on chip (SoC), there are several subsystems that need to communicate with each other, so there are a large number of interrupt paths and corresponding control paths between them, which are usually controlled by the interrupt system. As the scale of integrated circuits becomes larger and larger, the number of such interrupt paths has increased from hundreds to tens of thousands or even more, and due to the layout and wiring of the chip backend, the complete path will be cut into multiple sub-paths, and recombined and cross-multiplexed, resulting in the entire interrupt system showing the characteristics of too many paths, complex paths and fragmentation.

[0003] Verification is a very important part of the integrated circuit development process. It is an essential step to check whether the designed circuit meets expectations. In the current development and verification process of the interrupt system, verification is generally performed based on the Universal Verification Methodology (UVM) of the SystemVerilog language. Test vectors are manually developed for all interrupt paths, which results in huge time and machine resource costs for verification. In addition, the verification quality is uncontrollable, prone to repetition, and error-prone. Summary of the invention

[0004] In view of this, the present disclosure proposes an interrupt system verification method, device and storage medium.

[0005] According to one aspect of the present disclosure, a method for verifying an interruption system is provided. The method comprises:

[0006] Obtaining a first standard file, wherein the first standard file includes interrupt signal information;

[0007] Parsing based on the first standard file to obtain a second standard file that matches a preset formal verification tool, the second standard file including a transmission path description of the interrupt signal;

[0008] The interruption path correctness is verified based on the second standard file using a preset formal verification tool to obtain an interruption path verification result.

[0009] In one possible implementation, the interrupt signal information includes any one or more of the interrupt signal source information, the intermediate node information used to route the interrupt signal, the original routing relationship information, the destination node information responding to the interrupt, and the interrupt signal enable and shielding information. The interrupt signal source information includes the interrupt signal identifier and the source node information generating the interrupt.

[0010] In a possible implementation manner, the interrupt signal information further includes security attribute information for indicating whether the original routing relationship information can be modified.

[0011] In a possible implementation, parsing is performed based on the first standard file to obtain a second standard file that matches a preset formal verification tool, including:

[0012] Parsing the interrupt signal information in the first standard file, determining the interrupt signal name of each interrupt signal and the register transfer level RTL path of each node associated with the interrupt signal, wherein each node associated with the interrupt signal includes a source node, an intermediate node and a destination node, and the register transfer level RTL path is used to indicate the position of the node in the system on chip SoC;

[0013] Parsing the interrupt signal information in the first standard file, determining the entire transmission path of each interrupt signal from the source node through the intermediate node to the destination node;

[0014] A second standard file is generated based on the interrupt signal name of each interrupt signal, the register transfer level RTL path of each node associated with the interrupt signal, and the entire transmission path of each interrupt signal from the source node to the destination node via the intermediate node.

[0015] In a possible implementation, parsing the interrupt signal information in the first standard file to determine the entire transmission path of each interrupt signal from the source node to the destination node via the intermediate node includes:

[0016] Parsing the interrupt signal information in the first standard file to obtain one or more transmission paths of each interrupt signal from the source node to the intermediate node;

[0017] The interrupt signal information in the first standard file is parsed to obtain one or more transmission paths of each interrupt signal from the intermediate node to the destination node.

[0018] In a possible implementation, a preset formal verification tool is used to verify the correctness of the interruption path based on the second standard file to obtain an interruption path verification result, including:

[0019] Generate multiple property assertions to be verified based on the second standard file using a preset formal verification tool;

[0020] Based on multiple attribute assertions to be verified, the correctness of the entire transmission path of the interrupt signal from the source node through the intermediate node to the destination node is verified to obtain the interrupt path verification result.

[0021] In a possible implementation, based on multiple attribute assertions to be verified, the correctness of all transmission paths of the interrupt signal from the source node through the intermediate node to the destination node is verified to obtain the interrupt path verification result, including:

[0022] In response to the inconsistency between the file description of the interrupt signal transmission path and the interrupt path implemented by the register transfer level RTL during the verification process, error information is generated, and the error information indicates the transmission path with the problem.

[0023] In a possible implementation, the method further includes:

[0024] The environment information for running the preset formal verification tool is configured, and the environment information includes the first standard file, the storage path of the script for running the preset formal verification tool, and the parameters used in the formal verification process.

[0025] In a possible implementation, the method further includes:

[0026] In response to the coverage switch being turned on, coverage information of the interrupt path is collected, and the coverage information is used for analysis in a subsequent acceptance phase.

[0027] According to another aspect of the present disclosure, a device for verifying an interruption system is provided. The device comprises:

[0028] An acquisition module, used for acquiring a first standard file, wherein the first standard file includes interrupt signal information;

[0029] A parsing module, configured to parse the first standard file to obtain a second standard file that matches a preset formal verification tool, wherein the second standard file includes a transmission path description of the interrupt signal;

[0030] The verification module is used to verify the correctness of the interruption path based on the second standard file using a preset formal verification tool to obtain an interruption path verification result.

[0031] In one possible implementation, the interrupt signal information includes any one or more of the interrupt signal source information, the intermediate node information used to route the interrupt signal, the original routing relationship information, the destination node information responding to the interrupt, and the interrupt signal enable and shielding information. The interrupt signal source information includes the interrupt signal identifier and the source node information generating the interrupt.

[0032] In a possible implementation manner, the interrupt signal information further includes security attribute information for indicating whether the original routing relationship information can be modified.

[0033] In a possible implementation, the parsing module is used to:

[0034] Parsing the interrupt signal information in the first standard file, determining the interrupt signal name of each interrupt signal and the register transfer level RTL path of each node associated with the interrupt signal, wherein each node associated with the interrupt signal includes a source node, an intermediate node and a destination node, and the register transfer level RTL path is used to indicate the position of the node in the system on chip SoC;

[0035] Parsing the interrupt signal information in the first standard file, determining the entire transmission path of each interrupt signal from the source node through the intermediate node to the destination node;

[0036] A second standard file is generated based on the interrupt signal name of each interrupt signal, the register transfer level RTL path of each node associated with the interrupt signal, and the entire transmission path of each interrupt signal from the source node to the destination node via the intermediate node.

[0037] In a possible implementation, parsing the interrupt signal information in the first standard file to determine the entire transmission path of each interrupt signal from the source node to the destination node via the intermediate node includes:

[0038] Parsing the interrupt signal information in the first standard file to obtain one or more transmission paths of each interrupt signal from the source node to the intermediate node;

[0039] The interrupt signal information in the first standard file is parsed to obtain one or more transmission paths of each interrupt signal from the intermediate node to the destination node.

[0040] In a possible implementation, the verification module is used to:

[0041] Generate multiple property assertions to be verified based on the second standard file using a preset formal verification tool;

[0042] Based on multiple attribute assertions to be verified, the correctness of the entire transmission path of the interrupt signal from the source node through the intermediate node to the destination node is verified to obtain the interrupt path verification result.

[0043] In a possible implementation, based on multiple attribute assertions to be verified, the correctness of all transmission paths of the interrupt signal from the source node through the intermediate node to the destination node is verified to obtain the interrupt path verification result, including:

[0044] In response to the inconsistency between the file description of the interrupt signal transmission path and the interrupt path implemented by the register transfer level RTL during the verification process, error information is generated, and the error information indicates the transmission path with the problem.

[0045] In a possible implementation, the device further includes:

[0046] The configuration module is used to configure the environment information for running the preset formal verification tool, the environment information including the first standard file, the storage path of the script for running the preset formal verification tool and the parameters used in the formal verification process.

[0047] In a possible implementation, the device further includes:

[0048] The collection module is used to collect the coverage information of the interrupt path in response to the coverage switch being turned on, and the coverage information is used for analysis in the subsequent acceptance link.

[0049] According to another aspect of the present disclosure, an interrupt system verification device is provided, comprising: a processor; a memory for storing processor executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0050] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

[0051] According to another aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0052] According to an embodiment of the present disclosure, by acquiring a first standard file including interrupt signal information, parsing based on the first standard file to obtain a second standard file matching a preset formal verification tool, which includes a description of the transmission path of the interrupt signal, it is convenient for maintenance and modification of the interrupt system, so that the quality of iteration is guaranteed, and different interrupt system verification projects can be reused with each other. By using a preset formal verification tool to verify the correctness of the interrupt path based on the second standard file, an interrupt path verification result is obtained, and an automated interrupt system verification process can be implemented. By using a formal verification tool, the number of test vectors in the verification process can be reduced, which greatly reduces the time overhead and machine resource overhead (including machine computing resources and machine storage resources) of the interrupt system verification, and reduces the workload and the probability of errors.

[0053] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0055] Figure 1 A schematic diagram showing an application scenario according to an embodiment of the present disclosure.

[0056] Figure 2 A flowchart of an interrupt system verification method according to an embodiment of the present disclosure is shown.

[0057] Figure 3 A schematic diagram showing an interruption path according to an embodiment of the present disclosure.

[0058] Figure 4 A schematic diagram showing an interruption path according to an embodiment of the present disclosure.

[0059] Figure 5 A flowchart of an interrupt system verification method according to an embodiment of the present disclosure is shown.

[0060] Figure 6 A structural diagram of an interruption system verification device according to an embodiment of the present disclosure is shown.

[0061] Figure 7 It is a block diagram of a device 1900 for interrupting system verification according to an exemplary embodiment. DETAILED DESCRIPTION

[0062] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0063] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0064] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0065] There are several subsystems on a modern SoC, and they need to communicate with each other, so there will be a large number of interrupt paths (the transmission path of the interrupt signal from the source node (i.e., the device or module that generates the interrupt) to the final processing node (i.e., the device or module that responds to the interrupt) in the SoC system) and corresponding control paths. These interrupt paths are usually controlled by the interrupt system. As the scale of integrated circuits becomes larger and larger, the number of such interrupt paths has increased from hundreds to tens of thousands or even more. In addition, due to the layout and wiring of the chip backend, the complete path will be cut into multiple sub-paths, and recombined and cross-multiplexed, resulting in the entire interrupt system showing the characteristics of too many paths, complex paths and fragmentation. Verification is a very important link in the development process of integrated circuits. It is an indispensable step to check whether the designed circuit meets expectations. In the current development and verification process of the interrupt system, it is generally verified based on the UVM of the SystemVerilog language, in which test vectors are manually developed for all interrupt paths, which makes the time and machine resource overhead of verification huge, and the verification quality is uncontrollable, easy to repeat and error-prone.

[0066] In view of this, the present disclosure provides an interrupt system verification method, device and storage medium. The method of the embodiment of the present disclosure obtains a first standard file including interrupt signal information, and parses the first standard file to obtain a second standard file matching a preset formal verification tool, which includes a description of the transmission path of the interrupt signal, facilitates the maintenance and modification of the interrupt system, ensures the quality of iteration, and enables different interrupt system verification projects to be reused with each other. By using a preset formal verification tool to verify the correctness of the interrupt path based on the second standard file, an interrupt path verification result is obtained, and an automated interrupt system verification process can be implemented. By using a formal verification tool, the number of test vectors in the verification process can be reduced, which greatly reduces the time overhead and machine resource overhead (including machine computing resources and machine storage resources) of the interrupt system verification, and reduces the workload and the probability of error.

[0067] Figure 1A schematic diagram of an application scenario according to an embodiment of the present disclosure is shown. Different from the functional test scenario after hardware implementation, the method of the embodiment of the present disclosure is used in the scenario of pre-silicon verification of the interrupt system of the SoC, that is, it is applied before the actual manufacture of the SoC hardware. Among them, the SoC may include a processor subsystem, a memory subsystem, etc. In order to achieve mutual cooperation, the subsystems of the SoC need to communicate with each other. A large number of interrupt paths between them can be controlled by the interrupt system (the interrupt system may include an interrupt routing module, a security attribute control module, an interrupt enable and shielding module, etc.). The method of the embodiment of the present disclosure is mainly used to verify the interrupt system to ensure that the interrupt signal can be correctly propagated throughout the SoC, and all related subsystems and connections work according to the design specifications. The correctness and integrity of the hardware design are ensured through the interrupt system verification process of the present disclosure.

[0068] like Figure 1 As shown, the interrupt verification system of the embodiment of the present disclosure may include a preset formal verification tool. By acquiring a first standard file corresponding to the interrupt system on the SoC, the interrupt verification system can convert the first standard file into a second standard file recognizable by the preset formal verification tool, so that the preset formal verification tool on the interrupt verification system can automatically generate a property assertion to be verified for interrupt system verification based on the second standard file, so as to verify the correctness of the interrupt path and obtain the interrupt path verification result.

[0069] The interrupt verification system can be used in a terminal device or a server, and the terminal device can be any one or more of a mobile phone, a foldable electronic device, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), and a vehicle-mounted device. The embodiment of the present disclosure does not impose any special restrictions on the specific type of the terminal device, and the terminal device can have a wired or wireless communication function.

[0070] The server can be located locally or in the cloud, and can be a physical device or a virtual device, such as a virtual machine, a container, etc., and has a wireless communication function, wherein the wireless communication function can be set in the chip (system) or other parts or components of the server. The wireless communication function can be realized, for example, through mobile communication technologies such as 2G / 3G / 4G / 5G, as well as Wi-Fi, Bluetooth, frequency modulation (FM), digital radio, satellite communication, etc. Communication can also be carried out through wired connection to achieve interaction with other devices.

[0071] Figure 2FIG. 1 is a flow chart showing a method for verifying an interruption system according to an embodiment of the present disclosure. The method can be used in the above-mentioned interruption verification system, such as Figure 2 As shown, the method may include:

[0072] Step S201, obtaining a first standard file.

[0073] The first standard file may be an interrupt path standard description format file defined in the present disclosure, which may include interrupt signal information. When there is a need for pre-silicon verification of the interrupt system of the SoC, the designer and the verification personnel may manually configure the first standard file. The interrupt path may be a transmission path of the interrupt signal on the SoC.

[0074] The interrupt signal information may include any one or more of the interrupt signal source information, the intermediate node information for routing the interrupt signal, the original routing relationship information, the destination node information for responding to the interrupt, and the interrupt signal enable and shield information. The interrupt signal source information may include the interrupt signal identifier and the source node information generating the interrupt. The interrupt signal identifier may be used to uniquely identify the interrupt signal.

[0075] Figure 3 FIG. 1 is a schematic diagram showing an interruption path according to an embodiment of the present disclosure. Figure 3 The interrupt path shown in FIG. 1 is used as an example for description.

[0076] The source node that generates the interrupt (e.g. Figure 3 A) can be any subsystem on the SoC, and the source node information can include the register transfer level (RTL) path of the source node. The RTL path of the source node can be used to describe the location of the source node in the SoC, and the location can reflect the hierarchical structure of the SoC.

[0077] Intermediate nodes (such as Figure 3 B, C, D, E, F) may be the above-mentioned interrupt routing module, which is used to aggregate interrupt signals from different subsystems and then route the interrupt signals to different destination nodes according to the software-defined configuration. The intermediate node information may include the name of the intermediate node and the RTL path of the intermediate node, and the RTL path of the intermediate node may be used to describe the location of the intermediate node in the SoC. For example Figure 3 The middle node B in may represent an interrupt controller, and the RTL path of the middle node B may be used to describe the location of the interrupt controller in the SoC, for example.

[0078] Destination node (e.g. Figure 3In the example, G and H may be an interrupt processing unit for responding to an interrupt signal, such as a central processing unit (CPU) core. The destination node information may include the name of the destination node and the RTL path of the destination node. The RTL path of the destination node may be used to describe the location of the destination node in the SoC, for example Figure 3 The destination node G in may represent a CPU core, and the RTL path of the destination node G may be used to describe the position of the CPU core in the SoC, for example.

[0079] The original routing relationship information can be used to indicate possible transmission paths by which the same interrupt signal can be routed to different destination nodes. For example, the interrupt signal can be transmitted from source node A to destination node G via intermediate nodes B and E (intermediate nodes B and E can also pass through one or more other intermediate nodes), and can be transmitted to destination nodes G and H via intermediate nodes C and F (intermediate nodes C and F can also pass through one or more other intermediate nodes). Figure 3 The original routing relationship information can be expressed by the combination between nodes. For example, the first standard file may include the combination [interrupt source signal, intermediate node 1 input, intermediate node 1 output 1, destination node 1, intermediate node 2 input, intermediate node 2 output 1, destination node 1, intermediate node 2 output 2, destination node 2, ..., intermediate node n input, destination node n]. For a schematic diagram of the interrupt path corresponding to the combination, see Figure 4 , see Figure 4 , showing a schematic diagram of an interruption path according to an embodiment of the present disclosure. Figure 4 As shown, each node may include one or more input interfaces of interrupt signals, and each node may also include one or more output interfaces of interrupt signals. The above combination may represent multiple possible transmission paths of interrupt signals, including a transmission path from a source node to a destination node 1 via an intermediate node 1, a transmission path from a source node to a destination node 1 via an intermediate node 2, a transmission path from a source node to a destination node 2 via an intermediate node 2, and so on. A transmission path from a source node to a destination node n via an intermediate node n, etc. Among them, output 1 and output 2 may represent different output interfaces of the corresponding intermediate nodes, respectively.

[0080] The interrupt signal enable and shield information can be used to indicate that the interrupt signal is enabled or shielded at each intermediate node. Enabled means that the interrupt signal can be routed to other nodes at the intermediate node, and shielded means that the interrupt signal will be blocked at the intermediate node and will not be routed to other nodes. The interrupt signal being enabled at each intermediate node can be represented in the first standard file as a value of 1 for the corresponding intermediate node, and the interrupt signal being shielded at each intermediate node can be represented in the first standard file as a value of 0 for the corresponding intermediate node.

[0081] The interrupt signal information may also include security attribute information for indicating whether the routing relationship information can be modified. For example, it may indicate whether the routing relationship information can be modified by security-authorized software.

[0082] Each line in the first standard file may correspond to an interrupt signal and include interrupt signal information.

[0083] According to the above, the first standard file summarizes the interrupt path information. However, when verifying, it is necessary to verify each possible interrupt transmission path. In order to ensure the feasibility and comprehensiveness of the verification process, the first standard file can be parsed and processed by the method described below in the embodiment of the present disclosure to obtain each possible transmission path of the corresponding interrupt signal.

[0084] Step S202: performing parsing based on the first standard file to obtain a second standard file that matches a preset formal verification tool.

[0085] The second standard file may include a description of the transmission path of the interrupt signal, for example, including each possible transmission path of the interrupt signal from the source node to the destination node via the intermediate node.

[0086] The preset formal verification tool is, for example, a Formal tool, which can be used to perform formal verification on the transmission path of the interrupt signal described in the second standard file. The Formal verification tool verifies whether each transmission path can operate correctly under all possible input conditions by using mathematical and logical methods. The second standard file can be a file in the standard comma-separated values ​​(CSV) format required by the Formal tool to describe the path.

[0087] The first standard file can be parsed by script, see Figure 5 , shows a flow chart of an interrupt system verification method according to an embodiment of the present disclosure. Figure 5 As shown, step S202 may include:

[0088] Step S501 , parsing the interrupt signal information in the first standard file, and determining the interrupt signal name of each interrupt signal and the RTL path of each node associated with the interrupt signal.

[0089] The RTL path can be used to indicate the location of a node in the SoC. Each node associated with an interrupt signal includes a source node, an intermediate node, and a destination node. The RTL path of the source node can be obtained by parsing the above source node information, the RTL path of the intermediate node can be obtained by parsing the above intermediate node information, and the RTL path of the destination node can be obtained by parsing the above destination node information.

[0090] Step S502: parsing the interrupt signal information in the first standard file to determine the entire transmission path of each interrupt signal from the source node through the intermediate node to the destination node.

[0091] In step S502, you can:

[0092] Parsing the interrupt signal information in the first standard file to obtain one or more transmission paths of each interrupt signal from the source node to the intermediate node;

[0093] The interrupt signal information in the first standard file is parsed to obtain one or more transmission paths of each interrupt signal from the intermediate node to the destination node.

[0094] With the above Figure 3 For example, according to the above routing relationship information, the path of the interrupt signal from the source node to the intermediate node may include A~B~...~E, A~C~...~F and A~D; and the transmission path of the interrupt signal from the intermediate node to the destination node may include E~G, F~G and D~H.

[0095] The above transmission paths may be screened according to the interrupt signal enable and shield information. For example, when the interrupt signal enable and shield information indicates that the interrupt signal is shielded by the intermediate node D, the transmission paths from the source node A to the intermediate node D and from the intermediate node D to the destination node F may be removed (e.g. Figure 3 (indicated in the figure).

[0096] Step S503 , generating a second standard file based on the interrupt signal name of each interrupt signal, the RTL path of each node associated with the interrupt signal, and the entire transmission path of each interrupt signal from the source node to the destination node via the intermediate node.

[0097] Each line in the second standard file may represent a transmission path corresponding to the interrupt signal.

[0098] Each line in the second standard file may include the following parameters: (NAME, ENABLE, SOURCE, DESTINATION, PATH_DELAY, ENABLE_HOLD, CLOCK). Among them, NAME is used to represent the interrupt signal identifier; ENABLE is used to indicate whether the register is enabled or shielded; SOURCE and DESTINATION can represent two nodes on the transmission path respectively, SOURCE can represent the source node or intermediate node on the transmission path, and DESTINATION can represent the intermediate node or destination node on the transmission path. For example, for the transmission path of the interrupt signal from the intermediate node E to the destination node G, SOURCE can represent the intermediate node E, and DESTINATION can represent the destination node G. ENABLE is 1, indicating that the transmission path from the SOURCE node to the DESTINATION node is enabled (that is, connected), and ENABLE is 0, indicating that the transmission path from the SOURCE node to the DESTINATION node is shielded (that is, disconnected); PATH_DELAY can represent the clock cycle required for transmission from the SOURCE node to the DESTINATION node; ENABLE_HOLD is used to indicate the clock cycle for maintaining the enable or shield indicated by ENABLE; CLOCK is used to indicate the source of the reference clock signal.

[0099] This can automatically generate the standard files required by formal verification tools, reducing workload and the possibility of errors.

[0100] The method may further include:

[0101] Configures the environment information used to run the preset formal verification tool.

[0102] The environment information may include a first standard file, a storage path of a script for running a preset formal verification tool, and parameters used in the formal verification process.

[0103] For example, a script may be used to automatically generate a folder for running the formal tool, wherein the name of the folder may be specified by a script parameter, and the folder may contain the first standard file and the script required to run the formal tool. Parameters required in the formal verification process may also be configured. The script may be used to automatically start the formal tool to execute step S203. Return to see Figure 2 :

[0104] Step S203: using a preset formal verification tool to verify the correctness of the interruption path based on the second standard file to obtain an interruption path verification result.

[0105] According to an embodiment of the present disclosure, by acquiring a first standard file including interrupt signal information, parsing based on the first standard file to obtain a second standard file matching a preset formal verification tool, which includes a description of the transmission path of the interrupt signal, it is convenient for maintenance and modification of the interrupt system, so that the quality of iteration is guaranteed, and different interrupt system verification projects can be reused with each other. By using a preset formal verification tool to verify the correctness of the interrupt path based on the second standard file, an interrupt path verification result is obtained, and an automated interrupt system verification process can be implemented. By using a formal verification tool, the number of test vectors in the verification process can be reduced, which greatly reduces the time overhead and machine resource overhead (including machine computing resources and machine storage resources) of the interrupt system verification, and reduces the workload and the probability of errors.

[0106] In step S203, you can:

[0107] Generate multiple property assertions to be verified based on the second standard file using a preset formal verification tool;

[0108] Based on multiple attribute assertions to be verified, the correctness of the entire transmission path of the interrupt signal from the source node through the intermediate node to the destination node is verified to obtain the interrupt path verification result.

[0109] Among them, SystemVerilog Assertions (SVA) can be used to check whether the behavior under the expected conditions is as expected, so as to verify the correctness of the corresponding transmission path. Multiple SVAs can be run in parallel.

[0110] For example, a plurality of attribute assertions to be verified may be generated based on the description of the interrupt signal transmission path in the second standard file, and the process of generating the plurality of attribute assertions to be verified may be implemented based on the prior art.

[0111] Formal verification tools can simultaneously generate multiple property assertions to be verified to verify the interrupt path, and different property assertions to be verified can run in parallel, greatly reducing the time required for interrupt system verification.

[0112] The correctness verification may be to verify whether the transmission path is connected, and the interruption path verification result may include error information, and the error information indicates the transmission path with problems. For example, the error information may indicate a disconnected transmission path.

[0113] During the correctness verification process, you can:

[0114] In response to the file description of the interrupt signal transmission path being inconsistent with the interrupt path implemented by the RTL during the verification process, error information is generated.

[0115] The file description of the interrupt signal transmission path may refer to the description of the interrupt signal transmission path in the second standard file, and the interrupt path implemented by RTL may be a code written based on a corresponding hardware description language (such as Verilog or VHDL, etc.).

[0116] During the verification process, multiple sets of random conditions can be generated and input into the RTL design to be verified (i.e., the interrupt path implemented by RTL), and multiple property assertions to be verified are detected to be passed, that is, to detect whether the interrupt signal designed under multiple random conditions can be correctly transmitted to the target node. If multiple assertions are passed (pass), it means that the interrupt signal can be detected at the destination node during the verification process, that is, the file description of the interrupt signal transmission path is consistent with the interrupt path implemented by RTL during the verification process; if there is a failed assertion, it means that the file description of the interrupt signal transmission path is inconsistent with the interrupt path implemented by RTL during the verification process, and an error message can be generated.

[0117] You can also choose to open a graphical interface to parse and visualize error information based on the parameter configuration of the Formal tool.

[0118] Random regression testing and coverage testing can also be performed on the interrupt system to ensure that all transmission paths in the second standard file have been verified for correctness, which can be used for analysis in subsequent acceptance stages.

[0119] In response to the coverage switch being turned on, the coverage information of the interrupt path can be collected, and the coverage information can be the test result of the coverage test, and the coverage information can be used for analysis in the subsequent acceptance link. The coverage switch can be turned on or off as needed to control whether to collect the coverage information of the interrupt path.

[0120] Figure 6 FIG. 2 shows a structural diagram of an interrupt system verification device according to an embodiment of the present disclosure. Figure 6 As shown, the device comprises:

[0121] An acquisition module 601 is used to acquire a first standard file, where the first standard file includes interrupt signal information;

[0122] The parsing module 602 is used to parse the first standard file to obtain a second standard file that matches a preset formal verification tool, wherein the second standard file includes a transmission path description of the interrupt signal;

[0123] The verification module 603 is used to verify the correctness of the interruption path based on the second standard file using a preset formal verification tool to obtain an interruption path verification result.

[0124] In one possible implementation, the interrupt signal information includes any one or more of the interrupt signal source information, the intermediate node information used to route the interrupt signal, the original routing relationship information, the destination node information responding to the interrupt, and the interrupt signal enable and shielding information. The interrupt signal source information includes the interrupt signal identifier and the source node information generating the interrupt.

[0125] In a possible implementation manner, the interrupt signal information further includes security attribute information for indicating whether the original routing relationship information can be modified.

[0126] In a possible implementation, the parsing module 602 is used to:

[0127] Parsing the interrupt signal information in the first standard file, determining the interrupt signal name of each interrupt signal and the register transfer level RTL path of each node associated with the interrupt signal, wherein each node associated with the interrupt signal includes a source node, an intermediate node and a destination node, and the register transfer level RTL path is used to indicate the position of the node in the system on chip SoC;

[0128] Parsing the interrupt signal information in the first standard file, determining the entire transmission path of each interrupt signal from the source node through the intermediate node to the destination node;

[0129] A second standard file is generated based on the interrupt signal name of each interrupt signal, the register transfer level RTL path of each node associated with the interrupt signal, and the entire transmission path of each interrupt signal from the source node to the destination node via the intermediate node.

[0130] In a possible implementation, parsing the interrupt signal information in the first standard file to determine the entire transmission path of each interrupt signal from the source node to the destination node via the intermediate node includes:

[0131] Parsing the interrupt signal information in the first standard file to obtain one or more transmission paths of each interrupt signal from the source node to the intermediate node;

[0132] The interrupt signal information in the first standard file is parsed to obtain one or more transmission paths of each interrupt signal from the intermediate node to the destination node.

[0133] In a possible implementation, the verification module 603 is used to:

[0134] Generate multiple property assertions to be verified based on the second standard file using a preset formal verification tool;

[0135] Based on multiple attribute assertions to be verified, the correctness of the entire transmission path of the interrupt signal from the source node through the intermediate node to the destination node is verified to obtain the interrupt path verification result.

[0136] In a possible implementation, based on multiple attribute assertions to be verified, the correctness of all transmission paths of the interrupt signal from the source node through the intermediate node to the destination node is verified to obtain the interrupt path verification result, including:

[0137] In response to the inconsistency between the file description of the interrupt signal transmission path and the interrupt path implemented by the register transfer level RTL during the verification process, error information is generated, and the error information indicates the transmission path with the problem.

[0138] In a possible implementation, the device further includes:

[0139] The configuration module is used to configure the environment information for running the preset formal verification tool, the environment information including the first standard file, the storage path of the script for running the preset formal verification tool and the parameters used in the formal verification process.

[0140] In a possible implementation, the device further includes:

[0141] The collection module is used to collect the coverage information of the interrupt path in response to the coverage switch being turned on, and the coverage information is used for analysis in the subsequent acceptance link.

[0142] According to an embodiment of the present disclosure, by acquiring a first standard file including interrupt signal information, parsing based on the first standard file to obtain a second standard file matching a preset formal verification tool, which includes a description of the transmission path of the interrupt signal, it is convenient for maintenance and modification of the interrupt system, so that the quality of iteration is guaranteed, and different interrupt system verification projects can be reused with each other. By using a preset formal verification tool to verify the correctness of the interrupt path based on the second standard file, an interrupt path verification result is obtained, and an automated interrupt system verification process can be implemented. By using a formal verification tool, the number of test vectors in the verification process can be reduced, which greatly reduces the time overhead and machine resource overhead (including machine computing resources and machine storage resources) of the interrupt system verification, and reduces the workload and the probability of errors.

[0143] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0144] The embodiment of the present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0145] The embodiment of the present disclosure also proposes an interrupt system verification device, comprising: a processor; a memory for storing processor executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0146] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0147] Figure 7 1 is a block diagram of an apparatus 1900 for interrupting system verification according to an exemplary embodiment. For example, the apparatus 1900 may be provided as a server or a terminal device. Figure 7 , the apparatus 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions, such as an application, that can be executed by the processing component 1922. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0148] The device 1900 may also include a power supply component 1926 configured to perform power management of the device 1900, a wired or wireless network interface 1950 configured to connect the device 1900 to a network, and an input / output interface 1958 (I / O interface). The device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server 2000. TM , MacOS X TM , Unix TM ,Linux TM , FreeBSD TM or similar.

[0149] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the device 1900 to perform the above method.

[0150] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0151] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0152] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0153] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0154] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0155] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0156] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0157] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0158] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for verifying an interruption system, characterized in that: The method comprises: Acquire a first standard file, wherein the first standard file includes interrupt signal information; Parsing the first standard file to obtain a second standard file that matches a preset formal verification tool, wherein the second standard file includes a transmission path description of an interrupt signal; The preset formal verification tool is used to verify the correctness of the interruption path based on the second standard file to obtain an interruption path verification result.

2. The method according to claim 1, characterized in that The interrupt signal information includes any one or more of interrupt signal source information, intermediate node information for routing interrupt signals, original routing relationship information, destination node information for responding to interrupts, and interrupt signal enable and shield information. The interrupt signal source information includes an interrupt signal identifier and source node information that generates an interrupt. 3 . The method according to claim 2 , wherein the interrupt signal information further comprises security attribute information for indicating whether the original routing relationship information can be modified.

4. The method according to claim 1, characterized in that The parsing based on the first standard file to obtain a second standard file matching a preset formal verification tool includes: Parsing the interrupt signal information in the first standard file, determining the interrupt signal name of each interrupt signal and the register transfer level RTL path of each node associated with the interrupt signal, wherein each node associated with the interrupt signal includes a source node, an intermediate node and a destination node, and the register transfer level RTL path is used to indicate the position of the node in the system on chip SoC; Parsing the interrupt signal information in the first standard file to determine the entire transmission path of each interrupt signal from a source node through an intermediate node to a destination node; The second standard file is generated based on the interrupt signal name of each interrupt signal, the register transfer level RTL path of each node associated with the interrupt signal, and the entire transmission path of each interrupt signal from the source node to the destination node via the intermediate node.

5. The method according to claim 4, characterized in that The step of parsing the interrupt signal information in the first standard file to determine the entire transmission path of each interrupt signal from a source node through an intermediate node to a destination node includes: Parsing the interrupt signal information in the first standard file to obtain one or more transmission paths of each interrupt signal from a source node to an intermediate node; The interrupt signal information in the first standard file is parsed to obtain one or more transmission paths of each interrupt signal from the intermediate node to the destination node.

6. The method according to claim 1, characterized in that The using the preset formal verification tool to perform interruption path correctness verification based on the second standard file to obtain an interruption path verification result includes: Using the preset formal verification tool to generate a plurality of attribute assertions to be verified based on the second standard file; Based on the multiple attribute assertions to be verified, the correctness of all transmission paths of the interrupt signal from the source node through the intermediate node to the destination node is verified to obtain an interrupt path verification result.

7. The method according to claim 6, characterized in that The correctness of all transmission paths of the interrupt signal from the source node through the intermediate node to the destination node is verified based on the multiple attribute assertions to be verified, and the interrupt path verification result is obtained, including: In response to the inconsistency between the file description of the interrupt signal transmission path and the interrupt path implemented by the register transfer level RTL during the verification process, error information is generated, wherein the error information indicates the transmission path with a problem.

8. The method according to claim 1, characterized in that The method further comprises: Environmental information for running the preset formal verification tool is configured, the environmental information including a first standard file, a storage path of a script for running the preset formal verification tool, and parameters used in a formal verification process.

9. The method according to claim 1, characterized in that: The method further comprises: In response to the coverage switch being turned on, coverage information of the interrupt path is collected, and the coverage information is used for analysis in a subsequent acceptance link.

10. An interrupt system verification device, characterized in that: The device comprises: An acquisition module, used for acquiring a first standard file, wherein the first standard file includes interrupt signal information; A parsing module, configured to parse the first standard file to obtain a second standard file that matches a preset formal verification tool, wherein the second standard file includes a transmission path description of an interrupt signal; The verification module is used to use the preset formal verification tool to verify the correctness of the interruption path based on the second standard file to obtain an interruption path verification result.

11. An interrupt system verification device, characterized in that: include: processor; a memory for storing processor-executable instructions; Wherein, the processor is configured to implement the method described in any one of claims 1 to 9 when executing the instructions stored in the memory.

12. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 9 is implemented.

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