Power anti-backflow device for power management chip

Abstract

The utility model discloses a power anti-backflow device for a power management chip, which is provided with a charging management module, an anti-backflow protection circuit and a power management module, and a main control unit receives the input voltage of a charging unit to control the power management module to adjust the charging power of the charging unit to charge a battery. The conversion unit can provide accurate and stable voltage for each module, when the charging unit is powered off, the anti-backflow protection circuit is used for providing anti-backflow protection for a battery, the power management module can provide higher output power, and the power supply adjusting unit comprises a first-stage power supply adjusting circuit and a second-stage power supply adjusting circuit. The first-stage power supply adjusting circuit can enable the circuit to obtain lower standby working current, the second-stage power supply adjusting circuit can reduce loss and obtain higher output voltage, the anti-backflow protection circuit can prevent the problems of reverse connection of a battery and backflow, and the working reliability and safety of the power supply management chip are effectively guaranteed.

Description

Technical Field

[0001] The utility model belongs to the technical field of electronic circuits, and in particular relates to a power backflow prevention device for a power management chip. Background Art

[0002] At present, the types of electronic devices are becoming more and more abundant. Various commonly used electronic devices need to use various adapters. Whether it is a mobile phone, a computer, a mobile power bank or a camera, almost all mobile devices need a dedicated charger. Since the voltage and power provided by different devices are different, this situation will exist for a long time within a certain range. In order to improve the convenience of using programmable electronic devices and improve the versatility of adapter use, thereby reducing the number of charging devices, devices with USB interfaces and power management chips are usually used for power input charging. When the system is working normally, the stable voltage source can also manage the charging of the backup battery power supply.

[0003] In the battery charging management system, fast charging and super charging are usually provided, that is, high power input is provided. There is a power path when the DC power supply charges the battery. When the battery is charged to a certain voltage value, it can already supply power to the load, and the battery acts as a power supply. At this time, if the output voltage (battery voltage) of the system is higher than the input voltage (charging power supply voltage), especially when the charging power supply is removed, if the power path during charging is not controlled, then current backflow may occur, that is, in addition to supplying power to the load, the battery power supply will also backflow current to the input end, which will affect the normal use of the system and the battery life. Therefore, it is urgent to provide a power backflow prevention device for power management chips. Utility Model Content

[0004] In view of the above problems, the utility model provides a power backflow prevention device for a power management chip, which can improve the reliability of power transmission and power management, prevent battery backflow, and can be used in various charging products.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] The utility model provides a power backflow prevention device for a power management chip, comprising a charging management module, an anti-backflow protection circuit and a power management module, wherein the anti-backflow protection circuit and the power management module are both connected to the charging management module, and the anti-backflow protection circuit is connected to the power management module;

[0007] The charging management module includes a battery, a charging unit, a power adjustment unit, a main control unit and a conversion unit, wherein the power adjustment unit, the battery and the charging unit are all connected to the main control unit, the power adjustment unit is connected to the battery, the charging unit is connected to the conversion unit, the power adjustment unit and the power management module are all connected to the conversion unit, and the charging unit and the battery are all connected to the anti-backflow protection circuit;

[0008] Among them, the main control unit receives the input voltage of the charging unit to control the power management module to adjust the charging power of the charging unit to charge the battery, and when the charging unit is powered off, the anti-backflow protection circuit is used to provide anti-backflow protection for the battery.

[0009] As a preferred embodiment of the above technical solution, the anti-backflow protection circuit includes a transistor Q1, a transistor Q2, a plurality of resistors, a voltage stabilizing diode Z1, a MOS tube M0, an operational amplifier U1 and a capacitor C2, and the transistor Q1 is connected to the battery;

[0010] When the battery has voltage and is connected with the correct polarity, the base and emitter of the transistor Q1 are forward-biased and turned on, the MOS tube M0 is turned on, the battery is charged normally, the charging current flows from left to right through the MOS tube M0, the remote amplifier U1 outputs a low level, and the transistor Q2 is turned off;

[0011] When the battery is connected reversely, the base and emitter of the transistor Q1 are reverse biased and cut off, and the MOS transistor M0 is cut off to prevent the battery from being connected reversely;

[0012] When the input voltage of the charging unit is powered off, the diode Q1 and the MOS tube M0 remain turned on, the remote amplifier U1 outputs a high level, the diode Q2 is turned on, and the MOS tube M0 is turned off to prevent the battery from backflowing.

[0013] As a preferred embodiment of the above technical solution, the power supply adjustment unit includes a first-stage power supply adjustment circuit, a second-stage power supply adjustment circuit, a shutdown logic generation circuit, a voltage reference circuit and an oscillation counting circuit, wherein the first-stage power supply adjustment circuit, the second-stage power supply adjustment circuit and the voltage reference circuit are all connected to the shutdown logic generation circuit, the oscillation counting circuit is connected to the voltage reference circuit, and the first-stage power supply adjustment circuit and the second-stage power supply adjustment circuit are all connected to the voltage reference circuit;

[0014] The first-stage power supply adjustment circuit is used to perform primary adjustment on the high-voltage input and limit the maximum output voltage. After the output of the first-stage power supply adjustment circuit is stable, it switches to the second-stage power supply adjustment circuit. The output voltage is determined by the precise on-chip reference voltage and the voltage divider resistor. The oscillation counting circuit uses the internally generated oscillation clock as the timing reference, and realizes the counting delay through the counter in the oscillation counting circuit. The shutdown logic generation circuit is used to generate high and low voltage control signals to shut down the high-voltage MOS tube and other low-voltage modules, so that the circuit finally outputs a high-precision low-voltage power supply VCC.

[0015] As a preferred embodiment of the above technical solution, the first-stage power supply adjustment circuit includes a startup current generating circuit composed of a resistor Rc, a resistor R10, a MOS tube MP1, a MOS tube MP2, a MOS tube MN1, a MOS tube MN2 and a MOS tube MN3, as well as MNDEP and a diode D0. The resistor Rc is used to set the size of the startup current. The MNDEP and the diode D0 constitute the output end of the first-stage power supply adjustment circuit. The output voltage of the first-stage power supply adjustment circuit is clamped by the diode D0, and voltage limiting protection is provided when the second-stage power supply adjustment circuit is not started. The MNDEP is a depletion-type MOS tube.

[0016] As a preferred embodiment of the above technical solution, the second-stage power supply adjustment circuit includes an operational amplifier OP, a resistor R11, a resistor R12, a MOS tube MP0 and a MOS tube MN0, and a reference voltage V is selected when starting. R11 The voltage reference circuit is connected to the operational amplifier OP through switches S1 and S2, and switches to the reference voltage V after the startup is completed. R12 and started working steadily;

[0017] Among them, the reference voltage V R11 Less than the reference voltage V R12 , when powered on, switch S1 is closed and the reference voltage V R11 The negative terminal of the operational amplifier OP is used as an input voltage of the operational amplifier OP, and the positive terminal of the operational amplifier OP is connected to a node voltage VF of the voltage-dividing resistor R11 and the resistor R12 of the output voltage.

[0018] As a preferred embodiment of the above technical solution, when the circuit is powered on, the timing starts, and the oscillation counting circuit outputs a logic signal to control the switch S1 and the switch S2. When the initial state is started, the switch S1 is closed and the switch S2 is open. The voltage input to the negative terminal of the operational amplifier OP is the reference voltage V R11 ;

[0019] When the set counting time is reached, the oscillation counting circuit outputs a control logic signal to control switch S1 to open and switch S2 to close, R12Connect to the negative terminal of the operational amplifier OP.

[0020] As a preferred embodiment of the above technical solution, the voltage reference circuit includes MOS tube P1, MOS tube P2, MOS tube P3, OSC generating circuit, triode Q3, triode Q4, triode Q5, resistor R14, resistor R15 and resistor R16, the negative end of the operational amplifier OP is connected to the MOS tube P1 and the triode Q3, the positive end of the operational amplifier OP is connected to the MOS tube P2, the resistor R14 and the triode Q4, and the OS tube P3 and the resistor R15 are used to output the reference voltage V R12 , resistor R15, resistor R16 and transistor Q5 are used to output reference voltage V R11 .

[0021] As a preferred embodiment of the above technical solution, the shutdown logic generation circuit includes an inverter INV1, an inverter INV2 and a plurality of MOS tubes, and the shutdown logic generation circuit is used to generate an enable control signal for shutting down the MOS tubes.

[0022] As a preferred embodiment of the above technical solution, the conversion unit includes a DCDC converter, an inductor L, a resistor R9, a capacitor C0, a capacitor C1, a MOS transistor MN10 and a MOS transistor MN11. The inductor L, the resistor R9, the capacitor C0, the capacitor C1, the MOS transistor MN10 and the MOS transistor MN11 are all connected to the DCDC converter, the resistor R9 is connected in series with the capacitor C0 and then in parallel with the capacitor C1, and the MOS transistor MN1 is connected in series with the inductor L.

[0023] As a preferred embodiment of the above technical solution, the DCDC converter is a synchronous boost DCDC converter with an external power tube, and the MOS tube MN10 and the MOS tube MN11 are both NMOS tubes.

[0024] Compared with the prior art, the beneficial effects of the utility model are:

[0025] By setting up a charging management module, an anti-backflow protection circuit and a power management module, the main control unit receives the input voltage of the charging unit to control the power management module to adjust the charging power of the charging unit to charge the battery. The conversion unit can provide accurate and stable voltage to each module. When the charging unit is powered off, the anti-backflow protection circuit is used to provide anti-backflow protection to the battery. The power management module can provide higher output power. The power adjustment unit includes a first-stage power adjustment circuit and a second-stage power adjustment circuit. The first-stage power adjustment circuit can enable the circuit to obtain a lower standby operating current. The second-stage power adjustment circuit can reduce losses and obtain a higher output voltage. The anti-backflow protection circuit can prevent the problem of reverse connection of the battery and backflow, effectively ensuring the working reliability and safety of the power management chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a structural block diagram of a power backflow prevention device for a power management chip proposed by the utility model;

[0027] Figure 2 A circuit diagram of the anti-backflow protection circuit proposed by the utility model;

[0028] Figure 3 This is a structural block diagram of the power supply adjustment unit proposed in the utility model;

[0029] Figure 4 A circuit diagram of the power adjustment unit proposed in the utility model;

[0030] Figure 5 A circuit diagram of the power management module proposed in the utility model;

[0031] Figure 6 A circuit diagram of a voltage reference circuit proposed in the utility model;

[0032] Figure 7 A circuit diagram of a shutdown logic generation circuit proposed by the utility model;

[0033] Figure 8 This is a circuit diagram of the conversion unit proposed by the utility model.

[0034] The main component symbols are described as follows:

[0035] 100-charging management module; 110-battery; 120-charging unit; 130-power supply adjustment unit; 140-main control unit; 150-conversion unit; 160-anti-backflow protection circuit; 170-power management module; 180-first-stage power supply adjustment circuit; 190-second-stage power supply adjustment circuit; 200-shutdown logic generation circuit; 210-voltage reference circuit; 220-oscillation counting circuit. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.

[0037] See also Figure 1 and Figure 2 The utility model provides a power backflow prevention device for a power management chip, comprising a charging management module 100, an anti-backflow protection circuit 160 and a power management module 170, wherein the anti-backflow protection circuit 160 and the power management module 170 are both connected to the charging management module 100, and the anti-backflow protection circuit 160 is connected to the power management module 170;

[0038] The charging management module 100 includes a battery, a charging unit 120, a power adjustment unit 130, a main control unit 140 and a conversion unit 150. The power adjustment unit 130, the battery 110 and the charging unit 120 are all connected to the main control unit 140, the power adjustment unit 130 is connected to the battery 110, the charging unit 120 is connected to the conversion unit 150, the power adjustment unit 130 and the power management module 170 are all connected to the conversion unit 150, and the charging unit 120 and the battery 110 are all connected to the anti-backflow protection circuit 160;

[0039] Among them, the main control unit 140 receives the input voltage of the charging unit 120 to control the power management module 170 to adjust the charging power of the charging unit 120 to charge the battery 110. When the charging unit 120 is powered off, the anti-backflow protection circuit 160 is used to provide anti-backflow protection for the battery 110.

[0040] In this embodiment, the anti-backflow protection circuit includes a transistor Q1, a transistor Q2, a plurality of resistors, a voltage stabilizing diode Z1, a MOS transistor M0, an operational amplifier U1 and a capacitor C2, and the transistor Q1 is connected to the battery 110; when the battery 110 has voltage and is connected with the correct polarity, the base and emitter of the transistor Q1 are forward biased and turned on, the MOS transistor M0 is turned on, the battery 110 is charged normally, the charging current flows through the MOS transistor M0 from left to right, the remote operational amplifier U1 outputs a low level, and the transistor Q2 is turned off; when the battery 110 is connected reversely, the base and emitter of the transistor Q1 are reverse biased and turned off, and the MOS transistor M0 is turned off to prevent the battery 110 from being reversely connected; when the input voltage of the charging unit 120 is powered off, the diode Q1 and the MOS transistor M0 remain turned on, the remote operational amplifier U1 outputs a high level, the diode Q2 is turned on, and the MOS transistor M0 is turned off to prevent the battery 110 from backflowing.

[0041] See also Figure 5 In order to have a power transmission path under continuous large current stable working conditions, a power management module 170 is added. The power management module 170 includes MOS tubes M1, MOS tubes M2, MOS tubes M3 and MOS tubes M4. The parasitic diode of M4 between VIN and VOUT is set in the reverse direction of VIN value VOUT. The input is forwardly isolated from the output, but there is a parasitic path in the reverse direction. In this way, when the power switch M4 is turned off, power will not be transmitted to the device, which is beneficial to energy saving of the device.

[0042] It should be noted that the main control unit 140 can be an MCU, the battery 110 can be a plurality of series-connected batteries, the charging unit 140 can be a power adapter, the transistor Q1 is a PNP type and can be used as an auxiliary switch, and the MOS tube M0 is an NMOS tube. Only when the battery 110 has voltage and is connected with the correct polarity, the base emitter of Q1, i.e., the BE pole, is forward-biased and turned on, thereby causing MO to be turned on, and the battery can be charged normally. At this time, the charging current flows from right to left through M0, the operational amplifier U1, i.e., the operational amplifier U1 and its peripheral circuits output a low level, and Q2 is turned off; when the battery is connected in reverse, Q1 is turned off due to the reverse bias of the BE pole, and thus M0 is turned off, which plays a role in preventing the battery from being turned on. In other words, the conduction of Q1 and M0 is triggered by the voltage of the battery 110. If the battery is connected in reverse, they cannot be turned on, and the current channel between the input and the battery will be cut off. When the input voltage is cut off, due to the existence of battery 110 voltage, Q1 and M0 remain turned on, and the battery view is backflowed through the input terminal. At this time, U1 outputs a high level, Q2 is turned on, and M0 is turned off, thereby preventing backflow. It is suitable for a variety of charger products, and has good effects in preventing battery reverse connection and backflow.

[0043] It should be understood that by setting the charging management module 100, the anti-backflow protection circuit 160 and the power management module 170, the main control unit 140 receives the input voltage of the charging unit 120 to control the power management module 170 to adjust the charging power of the charging unit 120 to charge the battery 110, the conversion unit 150 can provide accurate and stable voltage to each module, when the charging unit 120 is powered off, the anti-backflow protection circuit 160 is used to provide anti-backflow protection to the battery 110, the power management module 170 can provide higher output power, the power adjustment unit 130 includes a first-stage power adjustment circuit 180 and a second-stage power adjustment circuit 190, the first-stage power adjustment circuit 180 can enable the circuit to obtain a lower standby operating current, the second-stage power adjustment circuit 190 can reduce losses and obtain a higher output voltage, the anti-backflow protection circuit 160 can prevent the battery 110 from being reversed and backflowing, and effectively ensure the working reliability and safety of the power management chip.

[0044] See also Figure 3 . Figure 4 and Figure 6 , the power adjustment unit 130 includes a first-stage power adjustment circuit 180, a second-stage power adjustment circuit 190, a shutdown logic generation circuit 200, a voltage reference circuit 210 and an oscillation counting circuit 220, the first-stage power adjustment circuit 180, the second-stage power adjustment circuit 190, and the voltage reference circuit 210 are all connected to the shutdown logic generation circuit 200, the oscillation counting circuit 220 is connected to the voltage reference circuit 210, and the first-stage power adjustment circuit 180 and the second-stage power adjustment circuit 190 are all connected to the voltage reference circuit 210;

[0045] The first-stage power supply adjustment circuit 180 is used to perform primary adjustment on the high-voltage input and limit the maximum output voltage. After the output of the first-stage power supply adjustment circuit 180 is stable, it switches to the second-stage power supply adjustment circuit 190. The output voltage is determined by the precise on-chip reference voltage and the voltage divider resistor. The oscillation counting circuit 220 uses the internally generated oscillation clock as the timing reference, and realizes the counting delay through the counter in the oscillation counting circuit 220. The shutdown logic generating circuit 200 is used to generate high and low voltage control signals to shut down the high-voltage MOS tube and other low-voltage modules, so that the circuit finally outputs a high-precision low-voltage power supply VCC.

[0046] In this embodiment, the first-stage power supply adjustment circuit 180 includes a startup current generating circuit composed of a resistor Rc, a resistor R10, a MOS transistor MP1, a MOS transistor MP2, a MOS transistor MN1, a MOS transistor MN2 and a MOS transistor MN3, as well as MNDEP and a diode D0. The resistor Rc is used to set the size of the startup current. The MNDEP and the diode D0 constitute the output end of the first-stage power supply adjustment circuit 180. The output voltage of the first-stage power supply adjustment circuit 180 is clamped by the diode D0 to provide voltage limiting protection when the second-stage power supply adjustment circuit 190 is not started. Among them, MNDEP is a depletion-type MOS transistor.

[0047] The second-stage power supply adjustment circuit 190 includes an operational amplifier OP, a resistor R11, a resistor R12, a MOS transistor MP0 and a MOS transistor MN0. When starting, a reference voltage V R11 The voltage reference circuit 210 is connected to the operational amplifier OP through the switch S1 and the switch S2, and switches to the reference voltage V after the startup is completed. R12 and started working steadily;

[0048] Among them, the reference voltage V R11 Less than the reference voltage V R12 , when powered on, switch S1 is closed and the reference voltage V R11 The negative terminal of the operational amplifier OP is used as an input voltage of the operational amplifier OP, and the positive terminal of the operational amplifier OP is connected to a node voltage VF of the voltage-dividing resistor R11 and the resistor R12 of the output voltage.

[0049] It should be noted that when the circuit is powered on, the timing starts. The oscillation counting circuit outputs a logic signal to control switches S1 and S2. In the initial state, switch S1 is closed and switch S2 is open. The voltage input to the negative terminal of the operational amplifier OP is the reference voltage V R11 When the set counting time is reached, the oscillation counting circuit outputs a control logic signal to control switch S1 to open and switch S2 to close, setting the reference voltage V R12The voltage reference circuit includes MOS tube P1, MOS tube P2, MOS tube P3, OSC generating circuit, transistor Q3, transistor Q4, transistor Q5, resistor R14, resistor R15 and resistor R16. The negative end of the operational amplifier OP is connected to the MOS tube P1 and the transistor Q3, the positive end of the operational amplifier OP is connected to the MOS tube P2, the resistor R14 and the transistor Q4, and the OS tube P3 and the resistor R15 are used to output the reference voltage V R12 , resistor R15, resistor R16 and transistor Q5 are used to output reference voltage V R11 .

[0050] Among them, Rc is used to set the size of the starting current, and R0 bears a part of the voltage, which can reduce the influence of the drain-source voltage change of the MOS tube on the current value under different power supply voltage conditions. In an environment where the startup speed requirement is not high, the startup current can be set to less than 0.3μA, thereby obtaining a lower standby operating current. MNDEP and D0 constitute the output stage of the first stage of power adjustment. At this time, the output voltage of the first-stage power adjustment circuit 180 is clamped by D0, and voltage limiting protection is provided when the second-stage power adjustment circuit 190 is not started. MNDEP is a depletion-type MOS tube, which can reduce the threshold loss and obtain a higher output voltage. The D0 clamping voltage is 5.2V. When the input power supply voltage is less than 5.2V, the output voltage of the first-stage power adjustment circuit 180 follows the input power supply voltage. The second-stage power adjustment circuit 190 may include a high-precision voltage reference circuit, in which the reference voltage V generated R11 is 1.15V, the reference voltage V R12 is 1.26V. When starting, select V R11 After the startup is completed, switch to V R12 And start stable operation, you can set V R11 The voltage is approximately V R12 0.9 times of the value above, which can ensure that the circuit works normally when powered on, and at the same time, the feedback voltage will not rise too high, which can effectively prevent the output voltage of the power adjustment unit 130 from overshooting.

[0051] Specifically, when the power is turned on, the switch S1 is closed and the reference voltage V R11 As the negative input voltage of the op amp, the node voltage VF of the voltage divider resistors R11 and R12 of the positive output voltage of the op amp, the output voltage VCC can be expressed as Calculate and set (R11+R12) / R12=4. In addition, V R11=1.15V, the output voltage VCC is 4.6V. The oscillation counting circuit inside the circuit generates a timing clock, which starts when the circuit is powered on. DFF, i.e., D-type flip-flop frequency division timing, is used to achieve a 4ms counting delay after power-on. The output logic signal of the counting delay module of the oscillation counting circuit controls switches S1 and S2. In the initial state, switch S1 is closed and S2 is open. The output voltage input to the negative terminal of the op amp is V R11 When the set counting time is reached, the output control logic disconnects S1 and closes S2. At this time, the reference voltage V R12 Connected to the negative terminal of the op amp, the output voltage can be calculated similarly from the above expression to be 5.04V. Among them, the first-stage power supply adjustment circuit 180 is the primary adjustment circuit of the input high-voltage power supply, which realizes the rough adjustment of the high voltage, and the accuracy is not high. MP1, MP2 and MP3 are high-voltage MOS, which can withstand a maximum of 40V high voltage. MN1 and MN3 have original loads and provide bias voltage for the shutdown logic generation circuit. D0 is a Zener diode for voltage clamping protection.

[0052] See also Figure 7 The shutdown logic generation circuit 200 includes an inverter INV1, an inverter INV2 and a plurality of MOS transistors. The shutdown logic generation circuit 200 is used to generate an enable control signal for shutting down the MOS transistors.

[0053] In this embodiment, the shutdown logic generation circuit 200 is used to generate an enable control signal that can shut down the high-voltage MOS. When the power supply voltage is a high-voltage input, a high-voltage MOS is required as an adjustment tube for the output power supply path. Therefore, a high-voltage control signal is generated to shut down the high-voltage adjustment MOS. SD is an external control signal used to select whether the control circuit is working in a normal working mode or a standby mode. SD is connected to the drain of MN4, and its gate is connected to the low-voltage power supply VCC. The source and drain of MN4 can withstand a maximum high-voltage input of 40V. The gate voltage is fixed to VCC, and the gate and source voltages are clamped, so the source voltage can be limited to a low voltage. The pull-down resistor R13 determines the initial value of the input signal of the inverter INV1, and the inverters INV1 and INV2 use a low-voltage power supply as the working voltage. MN5 and MN6 use a high-voltage MOS that can withstand high voltages. D1 is connected between the gate and source of MP3 for voltage clamping to prevent the gate and source voltages of MP3 from being too large and burning the device at the moment of power-on startup when VIN is a high-voltage power input. When SD is high, all modules are in normal working mode. On the contrary, the output low voltage logic VSD turns off the reference voltage circuit and turns off the switch tube MN0 in the second-stage power adjustment circuit. At the same time, the high voltage signal VT is in a high level state, which can turn off the high voltage PMOS.

[0054] See also Figure 8The conversion unit includes a DCDC converter, an inductor L, a resistor R9, a capacitor C0, a capacitor C1, a MOS transistor MN10 and a MOS transistor MN11. The inductor L, the resistor R9, the capacitor C0, the capacitor C1, the MOS transistor MN10 and the MOS transistor MN11 are all connected to the DCDC converter. The resistor R9 is connected in series with the capacitor C0 and then in parallel with the capacitor C1. The MOS transistor MN11 is connected in series with the inductor L.

[0055] In this embodiment, the DCDC converter is a synchronous boost DCDC converter with an external power tube, and both the MOS tube MN10 and the MOS tube MN11 are NMOS tubes. A dual-NMOS synchronous boost DCDC converter is used, and both NMOS are designed outside the chip, which can obtain better heat dissipation characteristics to support higher output power requirements.

[0056] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes within the technical scope disclosed by the present invention according to the technical scheme and the utility model concept of the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A power backflow prevention device for a power management chip, It is characterized in that It includes a charging management module, an anti-backflow protection circuit and a power management module, wherein the anti-backflow protection circuit and the power management module are both connected to the charging management module, and the anti-backflow protection circuit is connected to the power management module; The charging management module includes a battery, a charging unit, a power adjustment unit, a main control unit and a conversion unit, wherein the power adjustment unit, the battery and the charging unit are all connected to the main control unit, the power adjustment unit is connected to the battery, the charging unit is connected to the conversion unit, the power adjustment unit and the power management module are all connected to the conversion unit, and the charging unit and the battery are all connected to the anti-backflow protection circuit; Among them, the main control unit receives the input voltage of the charging unit to control the power management module to adjust the charging power of the charging unit to charge the battery, and when the charging unit is powered off, the anti-backflow protection circuit is used to provide anti-backflow protection for the battery.

2. The power backflow prevention device for a power management chip according to claim 1, It is characterized in that The anti-backflow protection circuit includes a transistor Q1, a transistor Q2, a plurality of resistors, a voltage stabilizing diode Z1, a MOS tube M0, an operational amplifier U1 and a capacitor C2, and the transistor Q1 is connected to the battery; When the battery has voltage and is connected with the correct polarity, the base and emitter of the transistor Q1 are forward-biased and turned on, the MOS tube M0 is turned on, the battery is charged normally, the charging current flows from left to right through the MOS tube M0, the remote amplifier U1 outputs a low level, and the transistor Q2 is turned off; When the battery is connected reversely, the base and emitter of the transistor Q1 are reverse biased and cut off, and the MOS transistor M0 is cut off to prevent the battery from being connected reversely; When the input voltage of the charging unit is powered off, the diode Q1 and the MOS tube M0 remain turned on, the remote amplifier U1 outputs a high level, the diode Q2 is turned on, and the MOS tube M0 is turned off to prevent the battery from backflowing.

3. The power backflow prevention device for a power management chip according to claim 1, It is characterized in that The power supply adjustment unit comprises a first-stage power supply adjustment circuit, a second-stage power supply adjustment circuit, a shutdown logic generation circuit, a voltage reference circuit and an oscillation counting circuit, wherein the first-stage power supply adjustment circuit, the second-stage power supply adjustment circuit and the voltage reference circuit are all connected to the shutdown logic generation circuit, the oscillation counting circuit is connected to the voltage reference circuit, and the first-stage power supply adjustment circuit and the second-stage power supply adjustment circuit are all connected to the voltage reference circuit; The first-stage power supply adjustment circuit is used to perform primary adjustment on the high-voltage input and limit the maximum output voltage. After the output of the first-stage power supply adjustment circuit is stable, it switches to the second-stage power supply adjustment circuit. The output voltage is determined by the precise on-chip reference voltage and the voltage divider resistor. The oscillation counting circuit uses the internally generated oscillation clock as the timing reference, and realizes the counting delay through the counter in the oscillation counting circuit. The shutdown logic generation circuit is used to generate high and low voltage control signals to shut down the high-voltage MOS tube and other low-voltage modules, so that the circuit finally outputs a high-precision low-voltage power supply VCC.

4. The power backflow prevention device for a power management chip according to claim 3, It is characterized in that The first-stage power supply adjustment circuit includes a startup current generating circuit composed of a resistor Rc, a resistor R10, a MOS tube MP1, a MOS tube MP2, a MOS tube MN1, a MOS tube MN2 and a MOS tube MN3, as well as MNDEP and a diode D0. The resistor Rc is used to set the size of the startup current. The MNDEP and the diode D0 constitute the output end of the first-stage power supply adjustment circuit. The output voltage of the first-stage power supply adjustment circuit is clamped by the diode D0, and voltage limiting protection is provided when the second-stage power supply adjustment circuit is not started. The MNDEP is a depletion-type MOS tube.

5. The power backflow prevention device for a power management chip according to claim 4, It is characterized in that The second-stage power supply adjustment circuit includes an operational amplifier OP, a resistor R11, a resistor R12, a MOS tube MP0 and a MOS tube MN0. When starting, a reference voltage V is selected. R11 The voltage reference circuit is connected to the operational amplifier OP through switches S1 and S2, and switches to the reference voltage V after the startup is completed. R12 and started working steadily; Among them, the reference voltage V R11 Less than the reference voltage V R12 , when powered on, switch S1 is closed and the reference voltage V R11 The negative terminal of the operational amplifier OP is used as an input voltage of the operational amplifier OP, and the positive terminal of the operational amplifier OP is connected to a node voltage VF of the voltage-dividing resistor R11 and the resistor R12 of the output voltage.

6. The power backflow prevention device for a power management chip according to claim 5, It is characterized in that When the circuit is powered on, the timing starts. The oscillation counting circuit outputs a logic signal to control switches S1 and S2. In the initial state, switch S1 is closed and switch S2 is open. The voltage input to the negative terminal of the operational amplifier OP is the reference voltage V R11 ; When the set counting time is reached, the oscillation counting circuit outputs a control logic signal to control switch S1 to open and switch S2 to close, R12 Connect to the negative terminal of the operational amplifier OP.

7. The power backflow prevention device for a power management chip according to claim 5, It is characterized in that The voltage reference circuit includes MOS tube P1, MOS tube P2, MOS tube P3, OSC generating circuit, triode Q3, triode Q4, triode Q5, resistor R14, resistor R15 and resistor R16. The negative end of the operational amplifier OP is connected to the MOS tube P1 and the triode Q3, the positive end of the operational amplifier OP is connected to the MOS tube P2, the resistor R14 and the triode Q4, and the OSC tube P3 and the resistor R15 are used to output the reference voltage V R12 , resistor R15, resistor R16 and transistor Q5 are used to output reference voltage V R11 .

8. The power backflow prevention device for a power management chip according to claim 3, It is characterized in that The shutdown logic generation circuit includes an inverter INV1, an inverter INV2 and a plurality of MOS transistors, and the shutdown logic generation circuit is used to generate an enable control signal for shutting down the MOS transistors.

9. The power backflow prevention device for a power management chip according to claim 1, It is characterized in that The conversion unit includes a DCDC converter, an inductor L, a resistor R9, a capacitor C0, a capacitor C1, a MOS transistor MN10 and a MOS transistor MN11. The inductor L, the resistor R9, the capacitor C0, the capacitor C1, the MOS transistor MN10 and the MOS transistor MN11 are all connected to the DCDC converter. The resistor R9 is connected in series with the capacitor C0 and then in parallel with the capacitor C1. The MOS transistor MN11 is connected in series with the inductor L.

10. The power backflow prevention device for a power management chip according to claim 9, It is characterized in that The DCDC converter is a synchronous boost DCDC converter with an external power tube, and both the MOS tube MN10 and the MOS tube MN11 are NMOS tubes.

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