Packaging substrate and chip packaging structure
By using glass substrates and conductive vias and rewiring layers to form signal paths in the RDL process, warping of the packaging unit during the stripping process is avoided, the substrate warping problem is solved, and the product yield and use reliability are improved. , and simplifies the preparation process.
Patent Information
- Application Number
- CN202420467124.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-12
- Publication Date
- 2025-01-14
- Estimated Expiration
- 2034-03-12
Smart Images
Figure CN222355137U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a packaging substrate and a chip packaging structure. Background Art
[0002] As Moore's Law gradually reaches its limit, many industry giants have turned their attention to the field of advanced packaging. Among them, the re-distribution layer (RDL) process, as an important part of advanced packaging technology, has attracted the attention of many researchers due to its advantages of high yield and high-density wiring.
[0003] However, in the current RDL process, after the chip is plastic-sealed, the substrate needs to be peeled off from the layer formed after the chip is plastic-sealed (sometimes called the plastic-sealing layer). During this peeling process, the plastic-sealing layer is prone to warping due to stress release, which causes the chip bonded to the substrate to warp and then causes the chip to fail, seriously affecting the production yield and reliability of the product. Therefore, how to keep the plastic-sealing layer flat is a problem that needs to be solved urgently.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Utility Model Content
[0005] Based on this, the embodiments of the present application provide a packaging substrate and a chip packaging structure, which can provide a first packaging unit with a flat morphology, thereby improving product production yield and reliability.
[0006] According to some embodiments, the present application provides a packaging substrate, including:
[0007] A glass substrate, wherein a conductive through hole is provided in the glass substrate;
[0008] A first packaging unit; the first packaging unit comprises:
[0009] A first plastic sealing layer is located on the first surface of the glass substrate;
[0010] The first redistribution layer is located on a side of the first plastic packaging layer away from the glass substrate and is electrically connected to the first end of the conductive through hole.
[0011] In some embodiments, the number of the first packaging units is multiple;
[0012] The plurality of first plastic encapsulation layers are stacked in sequence along a direction perpendicular to the first surface, and the plurality of first redistribution layers are electrically connected in sequence.
[0013] In some embodiments, the packaging substrate further includes a second packaging unit; the second packaging unit includes:
[0014] A second plastic sealing layer is located on a second surface of the glass substrate; the second surface is opposite to the first surface;
[0015] The second redistribution layer is located on a side of the second plastic packaging layer away from the glass substrate and is electrically connected to the second end of the conductive through hole.
[0016] In some embodiments, the number of the second packaging units is multiple;
[0017] The plurality of second plastic encapsulation layers are stacked in sequence along a direction perpendicular to the second surface, and the plurality of second redistribution layers are electrically connected in sequence.
[0018] In some embodiments, a material of the second plastic encapsulation layer is the same as a material of the first plastic encapsulation layer, and the second plastic encapsulation layer and the first plastic encapsulation layer are symmetrically arranged with the glass substrate as the center.
[0019] In some embodiments, the glass substrate defines a first active area and a second active area that are adjacently disposed;
[0020] The orthographic projection of the first redistribution layer on the glass substrate falls within the first effective area, and the orthographic projection of the second redistribution layer on the glass substrate falls within the second effective area.
[0021] In some embodiments, the packaging substrate further includes:
[0022] A first signal lead-out structure is located on a side of the first packaging unit away from the glass substrate; the first signal lead-out structure is electrically connected to the first end of the conductive through hole via the first redistribution layer;
[0023] The second signal lead-out structure is located on a side of the glass substrate away from the first packaging unit and is electrically connected to the second end of the conductive through hole.
[0024] In some embodiments, the second signal lead-out structure is located on a side of the second packaging unit away from the glass substrate, and is electrically connected to the second end of the conductive via via the second redistribution layer.
[0025] In some embodiments, the glass substrate has a thickness less than or equal to 100 μm.
[0026] According to some embodiments, the present application further provides a chip packaging structure, including:
[0027] chip;
[0028] The packaging substrate as described in some of the above embodiments; the chip is arranged on the packaging substrate and electrically connected to the packaging substrate.
[0029] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application.
[0030] The embodiments of the present application may or at least have the following advantages:
[0031] In an embodiment of the present application, the first packaging unit is arranged on the first surface of the glass substrate, the first packaging unit includes a first redistribution layer, and a conductive through hole is arranged in the glass substrate. The packaging substrate can form a signal path through the conductive through hole and the first redistribution layer arranged inside the glass substrate, which is used to provide an electrical lead-out path for the chip during subsequent production and use. In this way, since there is no need to peel off the first packaging unit from the glass substrate, the problem of warping of the first packaging unit due to stress release during the peeling process is avoided, so that the first packaging unit can maintain a flat morphology, and the chip is prevented from being driven by the first packaging unit during the peeling process. The warping effectively improves the product production yield and reliability. In an embodiment of the present application, since the glass substrate is retained, a continuous planar support can be provided for the first packaging unit in the subsequent process, so that the first packaging unit can always maintain a flat morphology in the subsequent process, and the product packaging accuracy is improved. In the preparation process of the embodiment of the present application, the step of peeling off the glass substrate can be omitted, so the preparation process is simpler and helps to reduce the preparation cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings.
[0033] Figure 1 A schematic diagram of a cross-sectional structure of a packaging substrate provided in some embodiments of the present application;
[0034] Figure 2 A schematic diagram of the cross-sectional structure of a glass substrate in a packaging substrate provided in some embodiments of the present application;
[0035] Figure 3 A schematic diagram of a cross-sectional structure of a packaging substrate provided in some other embodiments of the present application;
[0036] Figure 4 A schematic flow chart of a chip packaging method provided in some embodiments of the present application.
[0037] Description of reference numerals:
[0038] 100, glass substrate; 110, conductive through hole; 210, first packaging unit; 211, first plastic packaging layer; 212, first redistribution layer; 220, second packaging unit; 221, second plastic packaging layer; 222, second redistribution layer; 230, first insulating dielectric layer; 240, second insulating dielectric layer; 310, first signal lead-out structure; 320, second signal lead-out structure; A, first effective area; B, second effective area. DETAILED DESCRIPTION
[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0041] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, redistribution layer, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first redistribution layer may be referred to as the second redistribution layer, and similarly, the second redistribution layer may be referred to as the first redistribution layer; the first redistribution layer and the second redistribution layer are different redistribution layers.
[0042] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0043] In the current RDL process, the substrate is prone to warping, which causes the chip bonded to the substrate to warp and then causes the chip to fail, seriously affecting the production yield and reliability of the product. Therefore, how to keep the substrate in a better morphology is an urgent problem to be solved.
[0044] Based on this, the embodiments of the present application provide a packaging substrate and a chip packaging structure, which can provide a first packaging unit with a flat morphology, thereby improving the production yield and reliability of the product. The details will be described in the subsequent embodiments.
[0045] See also Figure 1 According to some embodiments, the present application provides a packaging substrate, which may specifically include a glass substrate 100 and a first packaging unit 210 .
[0046] Please combine Figure 2 It is understood that the glass substrate 100 is provided with a conductive via 110. The first packaging unit 210 may include a first plastic encapsulation layer 211 and a first redistribution layer 212; the first plastic encapsulation layer 211 is located on the first surface of the glass substrate 100, and the first redistribution layer 212 is located on a side of the first plastic encapsulation layer 211 away from the glass substrate 100, and is electrically connected to the first end of the conductive via 110.
[0047] In the packaging substrate provided in the above embodiment, the first packaging unit 210 is arranged on the first surface of the glass substrate 100, the first packaging unit 210 includes a first redistribution layer 212, and the glass substrate 100 is provided with a conductive through hole 110. The packaging substrate can form a signal path through the conductive through hole 110 and the first redistribution layer 212 provided inside the glass substrate 100, which is used to provide an electrical lead-out path for the chip during subsequent production and use. In this way, compared with the related art in which the glass substrate 100 and the plastic sealing layer need to be peeled off from each other after the chip is set, the above packaging substrate does not need to peel off the first packaging unit 210 from the glass substrate 100, thereby avoiding the problem of warping of the first packaging unit 210 due to stress release during the peeling process, so that the first packaging unit 210 can maintain a flat morphology, avoiding the chip from being driven by the first packaging unit 210 during the peeling process and warping, and effectively improving the product production yield and use reliability.
[0048] It can be understood that in the above-mentioned packaging substrate, since the glass substrate 100 is retained, it can provide continuous planar support for the first packaging unit 210 in the subsequent process, so that the first packaging unit 210 can always maintain a flat morphology in the subsequent process, thereby improving the product packaging accuracy.
[0049] In addition, the step of peeling off the glass substrate 100 can be omitted during the preparation process of the above-mentioned packaging substrate, so the preparation process is simpler and convenient, which is conducive to reducing the preparation cost.
[0050] It should be noted that the embodiment of the present application does not specifically limit the material of the first plastic layer 211. The material of the first plastic layer 211 can be adaptively selected so that the coefficient of thermal expansion (CTE) of the first plastic layer 211 matches the coefficient of thermal expansion of the glass substrate 100, thereby avoiding delamination of the first packaging unit 210 and the glass substrate 100, and further improving the product production yield.
[0051] As an example, the material of the first plastic layer 211 may include polyimide (PI for short). The thermal expansion coefficient of the PI layer matches well with that of the glass substrate 100 , which can ensure that the first packaging unit 210 and the glass substrate 100 are tightly fitted during the manufacturing process.
[0052] It should be noted that the number of the first packaging units 210 may be one or more, and the embodiment of the present application does not specifically limit this.
[0053] In some embodiments, there are multiple first encapsulation units 210 , and the multiple first encapsulation units 210 are stacked in sequence along a direction perpendicular to the first surface of the glass substrate 100 .
[0054] The plurality of first plastic encapsulation layers 211 are stacked in sequence along a direction perpendicular to the first surface, and the plurality of first redistribution layers 212 are electrically connected in sequence.
[0055] In the package substrate provided in the above embodiment, even if there is a large stress inside the plurality of first package units 210, since there is no need to peel the plurality of first package units 210 from the glass substrate 100, the stress will not be released, thereby avoiding warping, so that the first package unit 210 can maintain a flat morphology. Therefore, the above package substrate is conducive to stacking the plurality of first package units 210, so that the package substrate can have a higher line density, thereby improving the package level of the package substrate.
[0056] See also Figure 3 In some embodiments, the package substrate may further include a second package unit 220. The second package unit 220 may include a second plastic packaging layer 221 and a second redistribution layer 222.
[0057] The second plastic encapsulation layer 221 is located on the second surface of the glass substrate 100 , and the second redistribution layer 222 is located on a side of the second plastic encapsulation layer 221 away from the glass substrate 100 , and is electrically connected to the second end of the conductive via 110 .
[0058] It should be noted that, in the embodiment of the present application, the second surface refers to: a surface on the glass substrate 100 that is opposite to the first surface.
[0059] In the package substrate provided in the above embodiment, package units are arranged on both sides of the glass substrate 100, which further improves the package level of the package substrate. In addition, compared with arranging the first package unit 210 and the second package unit 220 on the same side of the glass substrate 100, arranging the first package unit 210 and the second package unit 220 on the opposite sides of the glass substrate 100 can reduce the number of package unit layers carried by a single side of the glass substrate 100, which is conducive to improving the stability of the overall structure.
[0060] It should be noted that the number of the second packaging units 220 may be one or more, and the embodiment of the present application does not specifically limit this.
[0061] In some embodiments, there are multiple second encapsulation units 220. The multiple second encapsulation units 220 are stacked in sequence along a direction perpendicular to the second surface of the glass substrate 100. That is, in the embodiment of the present application, multiple encapsulation units can be stacked on both sides of the glass substrate 100.
[0062] The plurality of second plastic encapsulation layers 221 are stacked in sequence along a direction perpendicular to the second surface, and the plurality of second redistribution layers 222 are electrically connected in sequence.
[0063] In some embodiments, the material of the second plastic encapsulation layer 221 is the same as that of the first plastic encapsulation layer 211 , and the second plastic encapsulation layer 221 and the first plastic encapsulation layer 211 are symmetrically arranged with the glass substrate 100 as the center.
[0064] In the package substrate provided in the above embodiment, the first plastic layer 211 and the second plastic layer 221 have the same material and the same size, so the forces exerted on the glass substrate 100 are opposite in direction and the same in magnitude, so that the force on the glass substrate 100 is more uniform as a whole. Therefore, the package substrate provided in the above embodiment can ensure that the glass substrate 100 maintains a straight shape and is not bent, avoids the yield loss of the glass substrate 100 due to the bending deformation force, and effectively improves the production yield and use reliability.
[0065] For ease of understanding, the following embodiments define a first effective area and a second effective area that are adjacently disposed on the glass substrate 100. Figure 3 understand, Figure 3 A first active area A and one of the adjacent second active areas B on the glass substrate 100 are shown.
[0066] In some embodiments, the orthographic projection of the first redistribution layer 212 on the glass substrate 100 falls within the first active area A, and the orthographic projection of the second redistribution layer 222 on the glass substrate 100 falls within the second active area B.
[0067] That is, the second redistribution layer 222 and the first redistribution layer 212 are staggered in a direction parallel to the glass substrate 100. In this way, stress concentration can be reduced, while increasing the wiring area of the package substrate, further improving the structural strength of the package substrate.
[0068] Please continue reading Figure 1 In some embodiments, the packaging substrate may further include a first signal lead-out structure 310 and a second signal lead-out structure 320 .
[0069] The first signal lead-out structure 310 is located on a side of the first packaging unit 210 away from the glass substrate 100; the first signal lead-out structure 310 is electrically connected to the first end of the conductive via 110 via the first redistribution layer 212. The second signal lead-out structure 320 is located on a side of the glass substrate 100 away from the first packaging unit 210, and is electrically connected to the second end of the conductive via 110.
[0070] The package substrate provided in the above embodiment is already provided with the first signal lead-out structure 310 and the second signal lead-out structure 320 before bonding the chip, so the preparation yield of the first signal lead-out structure 310 and the second signal lead-out structure 320 will not affect the whole process, for example, it will not affect the chip bonding process. Therefore, the use of the above package substrate is also conducive to improving the production yield.
[0071] As an example, the first signal lead-out structure 310 can be used to realize the electrical connection between the chip and the packaging substrate in the subsequent process, so that the electrical signal can be transmitted from the chip to the packaging substrate, which helps to package the chip into a final integrated circuit product so that it can work normally in practical applications. Exemplarily, the first signal lead-out structure 310 can include a conductive bump.
[0072] As an example, the second signal lead-out structure 320 may be used to implement electrical lead-out of the package substrate. For example, the second signal lead-out structure 320 may include a solder ball.
[0073] Please continue reading Figure 3 In some embodiments, the second signal lead-out structure 320 may be electrically connected to the second end of the conductive via 110 via the second redistribution layer 222 .
[0074] As an example, the first signal lead-out structure 310 and the first redistribution layer 212 may be electrically connected by an interconnection structure; as an example, the second signal lead-out structure 320 and the second redistribution layer 222 may also be electrically connected by an interconnection structure. The embodiment of the present application does not specifically limit the form of the interconnection structure, and the interconnection structure may be, for example, a metal wire.
[0075] Please continue reading Figure 1 In some embodiments, the package substrate may further include a first insulating dielectric layer 230 . The first insulating dielectric layer 230 is located on a side of the first plastic encapsulation layer 211 away from the glass substrate 100 , and is located between the first plastic encapsulation layer 211 and the first signal lead-out structure 310 .
[0076] In the packaging substrate provided in the above embodiment, the first signal lead-out structure 310 and the first redistribution layer 212 can be electrically connected via an interconnection structure disposed in the first insulating dielectric layer 230 .
[0077] Please continue reading Figure 3 In some embodiments, the package substrate may further include a second insulating dielectric layer 240 . The second insulating dielectric layer 240 is located on a side of the second plastic encapsulation layer 221 away from the glass substrate 100 , and is located between the second plastic encapsulation layer 221 and the second signal lead-out structure 320 .
[0078] In the packaging substrate provided in the above embodiment, the second signal lead-out structure 320 and the second redistribution layer 222 can be electrically connected via an interconnection structure disposed in the second insulating dielectric layer 240 .
[0079] As an example, the thickness of the glass substrate 100 may be less than or equal to 100 μm.
[0080] In the packaging substrate provided in the above example, the thickness of the glass substrate 100 is less than or equal to 100 μm. The smaller thickness of the glass substrate 100 shortens the heat dissipation path and reduces thermal resistance, thereby improving the heat dissipation efficiency and effectively improving the heat dissipation effect of the packaging substrate.
[0081] Moreover, the glass substrate 100 with a smaller thickness can also reduce the overall volume and mass of the packaging substrate, thereby facilitating a lightweight and thin design of the packaging substrate, so that the packaging substrate can be used to manufacture a variety of different electronic devices, with higher compatibility and a wider range of applications. For example, the overall thickness of the packaging substrate is smaller, and it can be suitable for use in thin electronic products.
[0082] For example, the thickness of the glass substrate 100 may be 30 μm, 50 μm, 70 μm, 90 μm, or 100 μm, etc., but is not limited thereto.
[0083] According to some embodiments, the present application also provides a chip packaging structure, including a chip and a packaging substrate as described in some embodiments above, wherein the chip is disposed on the packaging substrate and is electrically connected to the packaging substrate.
[0084] Since the packaging substrate in the chip packaging structure of the embodiment of the present application is the same as the packaging substrate structure described in the above embodiment, the two can solve the same technical problems and obtain the same technical effects, which will not be repeated here.
[0085] As an example, Figure 1 As shown, the chip may be disposed on a side of the first packaging unit 210 facing away from the glass substrate 100 .
[0086] It is understood that the embodiment of the present application does not specifically limit the type of chip. As an example, the chip can be a processing chip with a data processing function, such as a central processing unit (CPU), a system on chip (SOC), or a graphics processing unit (GPU) that can process data.
[0087] According to some embodiments, the present application further provides a chip packaging method, which can be used to prepare the chip packaging structure described in some of the above embodiments. Therefore, the technical features between the chip packaging method embodiment and the chip packaging structure embodiment can be replaced and supplemented with each other without conflict, so that those skilled in the art can understand the technical content of the present application.
[0088] See also Figure 4 In some embodiments, the chip packaging method may include the following steps S100 to S300.
[0089] In step S100 , a glass substrate 100 is provided, and a conductive through hole 110 is formed in the glass substrate 100 .
[0090] In step S200, a first packaging unit 210 is formed on the first surface of the glass substrate 100; wherein the first packaging unit 210 may specifically include a first plastic packaging layer 211 and a first redistribution layer 212, the first plastic packaging layer 211 is located on the first surface of the glass substrate 100, the first redistribution layer 212 is located on the side of the first plastic packaging layer 211 away from the glass substrate 100, and is electrically connected to the first end of the conductive through hole 110.
[0091] The glass substrate 100 and the first packaging unit 210 may together constitute a packaging substrate. The structure of the packaging substrate may refer to the relevant descriptions in some of the above embodiments. The packaging substrate may also include other necessary elements or components, which are not limited in the embodiments of the present application.
[0092] In step S300 , a chip is disposed on a side of the first packaging unit 210 away from the glass substrate 100 , so that the chip is electrically connected to the packaging substrate.
[0093] In the chip packaging method provided in the above embodiment, the first packaging unit 210 is formed on the first surface of the glass substrate 100, and the first packaging unit 210 includes a first redistribution layer 212, and a conductive through hole 110 is formed in the glass substrate 100. Therefore, the conductive through hole 110 formed inside the glass substrate 100 and the first redistribution layer 212 can form a signal path together, which is used to provide an electrical lead-out path for the chip set in step S300. In this way, compared with the need to peel the glass substrate 100 and the plastic sealing layer from each other in the related art, the above chip packaging method does not need to peel the first packaging unit 210 from the glass substrate 100, avoiding the problem of warping of the first packaging unit 210 due to stress release during the peeling process, so that the first packaging unit 210 can maintain a flat morphology, so as to provide continuous planar support for the chip, and avoid the chip being driven by the first packaging unit 210 during the peeling process. The warping occurs, and the product production yield and reliability are effectively improved.
[0094] In the above chip packaging method, since the glass substrate 100 is retained, it can provide continuous planar support for the first packaging unit 210 in step S300 and subsequent processes, so that the first packaging unit 210 can always maintain a flat morphology in subsequent processes, thereby improving product packaging accuracy.
[0095] In addition, the chip packaging method does not need to add an additional step of peeling off the glass substrate 100, so the process flow is simpler, which is conducive to reducing the preparation cost.
[0096] In some embodiments, before executing step S300, the chip packaging method may further include the following steps:
[0097] A first signal lead-out structure 310 is formed on a side of the first packaging unit 210 away from the glass substrate 100 . The first signal lead-out structure 310 is electrically connected to the first end of the conductive via 110 via the first redistribution layer 212 .
[0098] In some embodiments, before executing step S300, the chip packaging method may further include the following steps:
[0099] A second signal lead-out structure 320 is formed on a side of the glass substrate 100 away from the first packaging unit 210 . The second signal lead-out structure 320 is electrically connected to the second end of the conductive via 110 .
[0100] It can be understood that in the chip packaging method provided in the above embodiment, the chip can be electrically connected to the packaging substrate via the first signal lead-out structure 310. Since the above chip packaging method forms the first signal lead-out structure 310 and the second signal lead-out structure 320 before setting the chip, the preparation yield of the first signal lead-out structure 310 and the second signal lead-out structure 320 will not affect the subsequent step S300, that is, it will not affect the setting of the chip. Therefore, the use of the above chip packaging method is also conducive to further improving the production yield.
[0101] In some embodiments, the chip packaging method may further include a step of forming a second packaging unit 220 on the second surface of the glass substrate 100 .
[0102] The second packaging unit 220 may specifically include a second plastic encapsulation layer 221 and a second redistribution layer 222. The second plastic encapsulation layer 221 is located on the second surface of the glass substrate 100; the second redistribution layer 222 is located on the side of the second plastic encapsulation layer 221 away from the glass substrate 100, and is electrically connected to the second end of the conductive via 110.
[0103] In the chip packaging method provided in the above embodiment, packaging units are formed on both sides of the glass substrate 100, which can further improve the packaging level of the chip packaging method. In addition, compared with forming the first packaging unit 210 and the second packaging unit 220 on the same side of the glass substrate 100, forming the first packaging unit 210 and the second packaging unit 220 on the opposite sides of the glass substrate 100 can reduce the number of packaging unit layers carried by a single side of the glass substrate 100, which is conducive to improving the stability of the overall structure.
[0104] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0105] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A packaging substrate, characterized in that: include: A glass substrate, wherein a conductive through hole is provided in the glass substrate; A first packaging unit; The first packaging unit includes: A first plastic sealing layer is located on the first surface of the glass substrate; The first redistribution layer is located on a side of the first plastic packaging layer away from the glass substrate and is electrically connected to the first end of the conductive through hole.
2. The packaging substrate according to claim 1, characterized in that: The number of the first packaging units is multiple; The plurality of first plastic encapsulation layers are stacked in sequence along a direction perpendicular to the first surface, and the plurality of first redistribution layers are electrically connected in sequence.
3. The packaging substrate according to claim 2, characterized in that: Also includes a second packaging unit; the second packaging unit includes: A second plastic sealing layer is located on a second surface of the glass substrate; the second surface is opposite to the first surface; The second redistribution layer is located on a side of the second plastic packaging layer away from the glass substrate and is electrically connected to the second end of the conductive through hole.
4. The packaging substrate according to claim 3, characterized in that: The number of the second packaging units is multiple; The plurality of second plastic encapsulation layers are stacked in sequence along a direction perpendicular to the second surface, and the plurality of second redistribution layers are electrically connected in sequence.
5. The packaging substrate according to claim 3, characterized in that: The material of the second plastic encapsulation layer is the same as that of the first plastic encapsulation layer, and the second plastic encapsulation layer and the first plastic encapsulation layer are symmetrically arranged with the glass substrate as the center.
6. The packaging substrate according to claim 5, characterized in that: The glass substrate defines a first effective area and a second effective area that are adjacently arranged; The orthographic projection of the first redistribution layer on the glass substrate falls within the first effective area, and the orthographic projection of the second redistribution layer on the glass substrate falls within the second effective area.
7. The packaging substrate according to claim 3, characterized in that: Also includes: A first signal lead-out structure is located on a side of the first packaging unit away from the glass substrate; the first signal lead-out structure is electrically connected to the first end of the conductive through hole via the first redistribution layer; The second signal lead-out structure is located on a side of the glass substrate away from the first packaging unit and is electrically connected to the second end of the conductive through hole.
8. The packaging substrate according to claim 7, characterized in that: The second signal lead-out structure is located on a side of the second packaging unit away from the glass substrate, and is electrically connected to the second end of the conductive via via the second redistribution layer.
9. The packaging substrate according to claim 1, characterized in that: The thickness of the glass substrate is less than or equal to 100 μm.
10. A chip packaging structure, characterized in that: include: chip; The packaging substrate according to any one of claims 1 to 9; The chip is disposed on the packaging substrate and is electrically connected to the packaging substrate.