Electronic package

Abstract

An electronic package at least includes an electronic component, a conductive pillar, a reinforcing member, a cladding layer, and a redistribution layer. The conductive column and the reinforcing member are arranged around the electronic component. The coating layer coats the electronic component, the conductive column and the reinforcing member. The redistribution layer is disposed on the same side of the electronic component, the conductive pillar, the reinforcing member, and the cladding layer, and is electrically connected to the electronic component and the conductive pillar. The reinforcing member has high hardness and an adjustable thermal expansion coefficient, so that the strength and rigidity of the electronic packaging member can be improved, and the warping of the electronic packaging member can be reduced.

Description

Technical Field

[0001] The present application relates to a packaging structure, and more particularly to an electronic packaging with a reinforcement component. Background Art

[0002] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package 1 .

[0003] like Figure 1 As shown, the semiconductor package 1 includes a first insulating layer 111, a first semiconductor chip 12, an adhesive layer 121, a conductive element 123, a second insulating layer 124, a conductive column 112, a first packaging colloid 113, a redistribution layer 13, a second semiconductor chip 14, a first conductive bump 142, a first base glue 143, a second packaging colloid 144, an under bump metal layer 151, a second conductive bump 152, a second base glue 153, a packaging substrate 10, and a conductor 103.

[0004] A plurality of electrode pads 122 are provided on the active surface of the upper side of the first semiconductor chip 12. A plurality of the conductive elements 123 are bonded to the plurality of electrode pads 122. A second insulating layer 124 is provided on the active surface of each of the first semiconductor chips 12 and is provided around the plurality of conductive elements 123. The first semiconductor chip 12 is bonded to the first insulating layer 111 by the adhesive layer 121 at the inactive surface on the lower side thereof. A plurality of conductive pillars 112 are provided around the first semiconductor chip 12. The first encapsulating body 113 covers the plurality of conductive pillars 112, the first semiconductor chip 12, the adhesive layer 121 and the second insulating layer 124. A redistribution layer 13 is provided on the upper side of the first semiconductor chip 12, the plurality of conductive elements 123, the second insulating layer 124, the plurality of conductive pillars 112 and the first encapsulating body 113.

[0005] The second semiconductor chip 14 has an upper non-active surface and a lower active surface, and the active surface has a plurality of electrode pads 141 to combine with a plurality of first conductive bumps 142. The second semiconductor chip 14 is flip-chip bonded to the upper side of the redistribution layer 13 through the electrode pads 141 and the first conductive bumps 142. The first bottom glue 143 covers the plurality of first conductive bumps 142. The second encapsulation glue 144 is disposed on the upper side of the redistribution layer 13 and covers the second semiconductor chip 14 and the first bottom glue 143.

[0006] The package substrate 10 is disposed on the lower side of the first insulating layer 111. In detail, the first insulating layer 111 and the structure thereon are bonded to the upper side of the package substrate 10 through the under bump metal layer 151 and the second conductive bump 152. The under bump metal layer 151 is at least partially disposed in the first insulating layer 111, and the second conductive bump 152 is bonded to the lower side of the under bump metal layer 151 and the upper side of the package substrate 10. The second underfill 153 covers the second conductive bump 152. The conductor 103 is disposed on the lower side of the package substrate 10.

[0007] As the threshold of semiconductor packaging technology is gradually raised, the size of semiconductor packages is enlarged. However, in large packaging structures such as semiconductor packages 1, warpage problems have begun to occur, and effective solutions are urgently needed. Utility Model Content

[0008] To solve the above problems, the present application provides an electronic package, comprising an electronic component, a conductive column, a reinforcement, a coating layer and a redistribution layer. The conductive column and the reinforcement are both arranged around the electronic component. The coating layer covers the electronic component, the conductive column and the reinforcement. The redistribution layer is arranged on the same side of the electronic component, the conductive column, the reinforcement and the coating layer, and electrically connects the electronic component and the conductive column.

[0009] The present application also provides a method for manufacturing an electronic package, comprising: setting a conductive column and a reinforcement member around an electronic component; forming a coating layer so that the coating layer covers the electronic component, the conductive column and the reinforcement member; and forming a redistribution layer on the same side of the electronic component, the conductive column, the reinforcement member and the coating layer so that the redistribution layer electrically connects the electronic component and the conductive column.

[0010] As described above, the electronic package of the present application includes a reinforcing member. The reinforcing member has a higher hardness than the coating layer and has an adjustable coefficient of thermal expansion (CTE), so it can improve the strength and rigidity of the structure of the electronic package to reduce the warping of the electronic package, thereby facilitating the development of advanced packaging technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package.

[0012] Figures 2A to 2K It is a cross-sectional schematic diagram of a method for manufacturing an electronic package according to an embodiment of the present application.

[0013] Figure 3A FIG. 4 is a cross-sectional schematic diagram of a method for manufacturing an electronic package according to another embodiment of the present application.

[0014] Figure 3BFIG. 4 is a cross-sectional schematic diagram of a method for manufacturing an electronic package according to another embodiment of the present application.

[0015] Description of Reference Numerals

[0016] 1 Semiconductor Package

[0017] 10 Package substrate

[0018] 101 Insulation layer

[0019] 102 Circuit layer

[0020] 103 Conductors

[0021] 111 First insulation layer

[0022] 112 Conductive column

[0023] 113 First Encapsulation Colloid

[0024] 12 First Semiconductor Chip

[0025] 121 Adhesive layer

[0026] 122 electrode pads

[0027] 123 Conductive elements

[0028] 124 Second insulation layer

[0029] 13 Redistribution Layer

[0030] 131 Insulation layer

[0031] 132 Line Layer

[0032] 14. Second semiconductor chip

[0033] 141 Electrode pads

[0034] 142 first conductive bump

[0035] 143 Second primer

[0036] 144 Second packaging colloid

[0037] 151 Under Bump Metal

[0038] 152 second conductive bump

[0039] 153 Second primer

[0040] 2 Electronic packaging

[0041] 20 Load-bearing structure

[0042] 201 Insulation layer

[0043] 202 Line Layer

[0044] 203 Conductors

[0045] 211 First insulation layer

[0046] 212 Conductive column

[0047] 213 First coating layer

[0048] 22 First Electronic Components

[0049] 221 Adhesive layer

[0050] 222 Electrode pads

[0051] 223 Conductive elements

[0052] 224 Second insulation layer

[0053] 23 Redistribution Layer

[0054] 231 Insulation layer

[0055] 232 Line Layer

[0056] 24 Second electronic component

[0057] 241 Electrode pads

[0058] 242 first conductive bump

[0059] 243 First Primer

[0060] 244 Second coating layer

[0061] 251 Under Bump Metal

[0062] 252 second conductive bump

[0063] 253 Second primer

[0064] 26 Bearing

[0065] 261 Release layer

[0066] 262 Basal layer

[0067] 27 Reinforcements. DETAILED DESCRIPTION

[0068] The following describes the implementation methods of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.

[0069] Figures 2A to 2K It is a cross-sectional schematic diagram of a method for manufacturing an electronic package according to an embodiment of the present application.

[0070] First, if Figure 2A As shown, a release layer 261 is formed on a first side of the carrier 26 , and a base layer 262 is formed or disposed on the first side of the release layer 261 .

[0071] Figure 2A The components shown in the figure such as the carrier 26, the release layer 261 and the base layer 262 all have a first side and a second side opposite to each other. Figures 2B to 2K , 3A and 3B also have opposite first and second sides.

[0072] like Figure 2B As shown, a first insulating layer 211 is formed on a first side of a base layer 262, and a plurality of conductive pillars 212 are disposed on the first side of the base layer 262. The lower end of each conductive pillar 212 is disposed in the first insulating layer 211, and the remaining portion of each conductive pillar 212 is disposed on the first side of the first insulating layer 211. The conductive pillars 212 are formed of, for example, copper.

[0073] The material forming the first insulating layer 211 may be polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0074] like Figure 2C As shown, at least one first electronic component 22 is disposed on the first insulating layer 211, and a plurality of conductive pillars 212 are disposed around the first electronic component 22. This figure shows a plurality of first electronic components 22, wherein each of the first electronic components 22 is bonded to the first side of the first insulating layer 211 by an adhesive layer 221 such as glue on the non-active surface of the second side. A plurality of electrode pads 222 are disposed on the active surface of the first side of each of the first electronic components 22, a conductive element 223 is formed on the first side of each of the electrode pads 222, and a second insulating layer 224 is formed on the active surface of each of the first electronic components 22 and around the conductive element 223.

[0075] The material for forming the conductive element 223 is, for example, copper, and the material for forming the second insulating layer 224 may be the aforementioned poly(p-oxadiazole) (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0076] Each of the first electronic components 22 can be an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.

[0077] In addition, at least one reinforcing member 27 is disposed around the first electronic element 22, wherein the reinforcing member 27 is disposed on the first side of the first insulating layer 211. The reinforcing member 27 can be a glass block, a metal block or a dummy die.

[0078] like Figure 2D As shown, a first encapsulating layer 213 is formed on the first side of the first insulating layer 211 so that the first encapsulating layer 213 encapsulates the first insulating layer 211 and the conductive pillars 212, the reinforcing member 27, the adhesive layer 221, the first electronic element 22, the electrode pad 222, the conductive element 223 and the second insulating layer 224 located on the first side thereof.

[0079] The first coating layer 213 is made of an insulating material, such as polyimide (PI) or epoxy resin packaging colloid or packaging material. The first coating layer 213 can be formed by molding, lamination or coating.

[0080] Then, the upper end of the first cladding layer 213 is polished to expose the conductive pillar 212 , the reinforcing member 27 , the conductive element 223 and the second insulating layer 224 .

[0081] like Figure 2E As shown, a redistribution layer 23 is formed on the conductive pillar 212 , the reinforcement 27 , the first electronic element 22 , the conductive element 223 , the second insulating layer 224 and the first side of the first cladding layer 213 .

[0082] The redistribution layer 23 includes at least one insulating layer 231 and at least one circuit layer 232 combined with the insulating layer 231. For example, the circuit layer 232 is made of copper, and the insulating layer 231 can be made of the aforementioned poly(p-oxadiazole) (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0083] The circuit layer 232 of the redistribution layer 23 is electrically connected to the conductive pillars 212 , and is electrically connected to each of the first electronic components 22 through the conductive elements 223 and the electrode pads 222 .

[0084] like Figure 2F As shown, at least one second electronic component 24 is disposed on the first side of the redistribution layer 23. The second electronic component 24 can be an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor.

[0085] The second electronic component 24 has a non-active surface on the first side and an active surface on the second side. The active surface has a plurality of electrode pads 241 to combine with a plurality of first conductive bumps 242. Each of the first conductive bumps 242 can be formed of a solder material, or a conductive metal material. The second electronic component 24 is flip-chip-bonded to the first side of the redistribution layer 23 through the electrode pads 241 on the active surface and the first conductive bumps 242 to electrically connect the circuit layer 232 of the redistribution layer 23. For example, a first primer 243 can be used to cover the plurality of first conductive bumps 242.

[0086] like Figure 2G As shown, a second encapsulation layer 244 is formed on the first side of the redistribution layer 23 , so that the second encapsulation layer 244 encapsulates the second electronic component 24 and the first underfill 243 .

[0087] The second coating layer 244 is made of an insulating material, such as polyimide (PI) or epoxy resin packaging colloid or packaging material. The second coating layer 244 can also be formed by molding, lamination or coating.

[0088] like Figure 2H As shown, remove Figure 2G The carrier 26, the release layer 261 and the base layer 262 are shown, and the remaining structures are flipped. Then, an under bump metallurgy (UBM) 251 is formed. The under bump metallurgy 251 is at least partially formed in the first insulating layer 211, and the under bump metallurgy 251 can be electrically connected to the conductive pillar 212.

[0089] Then, a plurality of second conductive bumps 252 are formed or disposed on the under bump metal layer 251. Each of the second conductive bumps 252 can be formed of a solder material or a conductive metal material.

[0090] like Fig.2I As shown, flip Figure 2H The structure shown in FIG. 1 is further ground at its upper end to expose the second electronic component 24 .

[0091] like Figure 2J As shown, Fig.2I The structure shown is bonded to the first side of the supporting structure 20 through the second conductive bump 252, and the conductive pillar 212 is electrically connected to the circuit layer 202 of the supporting structure 20 through the under bump metal layer 251 and the second conductive bump 252. In addition, the second conductive bump 252 can be coated with a second underfill 253.

[0092] The supporting structure 20 may be a package substrate or an interposer, which includes at least one insulating layer 201 and at least one circuit layer 202 combined with the at least one insulating layer 201. For example, the material forming the circuit layer 202 is copper, and the material forming the insulating layer 201 may be the aforementioned poly(p-oxadiazole benzene) (PBO), polyimide (PI), prepreg (PP) or other dielectric materials. It should be understood that the supporting structure 20 may also be other plates, such as a lead frame, a wafer, or other plates with metal routing.

[0093] like Figure 2K As shown, a plurality of conductors 203 are formed on the second side of the supporting structure 20 , and the conductors 203 are electrically connected to the circuit layer 202 of the supporting structure 20 to complete the electronic package 2 .

[0094] Each of the conductors 203 is, for example, a conductive column or a conductive bump.

[0095] Through the aforementioned process, the electronic package 2 of the present application includes a first insulating layer 211, at least one first electronic component 22, an adhesive layer 221, multiple conductive components 223, a second insulating layer 224, multiple conductive pillars 212, at least one reinforcement 27, a first encapsulation layer 213, a redistribution layer 23, at least one second electronic component 24, multiple first conductive bumps 242, a first base glue 243, a second encapsulation layer 244, an under-bump metal layer 251, multiple second conductive bumps 252, a second base glue 253, a supporting structure 20, and multiple conductors 203.

[0096] A plurality of electrode pads 222 are provided on the active surface of the first side of the first electronic component 22. The plurality of conductive elements 223 are bonded to the plurality of electrode pads 222. The second insulating layer 224 is provided on the active surface of the first electronic component 22 and is provided around the conductive elements 223. The first electronic component 22 is bonded to the first side of the first insulating layer 211 through the adhesive layer 221 at the inactive surface of the second side thereof. The conductive pillar 212 and the reinforcing member 27 are provided on the first side of the first insulating layer 211 and are provided around the first electronic component 22. The first encapsulating layer 213 encapsulates the conductive pillar 212, the reinforcing member 27, the first electronic component 22, the adhesive layer 221 and the second insulating layer 224. The redistribution layer 23 is provided on the first side of the first electronic component 22, the conductive element 223, the second insulating layer 224, the conductive pillar 212, the reinforcing member 27 and the first encapsulating layer 213.

[0097] The second electronic component 24 has a non-active surface on the first side and an active surface on the second side, and the active surface has a plurality of electrode pads 241 to combine with a plurality of first conductive bumps 242. The second electronic component 24 is flip-chip-bonded to the first side of the redistribution layer 23 through the electrode pads 241 and the first conductive bumps 242. The first primer 243 covers the first conductive bumps 242. The second coating layer 244 is disposed on the first side of the redistribution layer 23 and covers the second electronic component 24 and the first primer 243.

[0098] The supporting structure 20 is disposed on the second side of the first insulating layer 211. Specifically, the first insulating layer 211 and the structure thereon are bonded to the first side of the supporting structure 20 through the under bump metal layer 251 and the second conductive bump 252. The second underfill 253 covers the second conductive bump 252. The conductor 203 is disposed on the second side of the supporting structure 20.

[0099] The conductor 203 is electrically connected to the circuit layer 202 of the supporting structure 20, the second conductive bump 252, the under bump metal layer 251, the conductive pillar 212, the circuit layer 232 of the redistribution layer 23, the conductive element 223, the electrode pad 222 of the first electronic element 22, the first conductive bump 242, and the electrode pad 241 of the second electronic element 24. Through the aforementioned electrical connection relationship, the conductor 203 can electrically connect the first electronic element 22 and the second electronic element 24.

[0100] Figure 2K In the electronic package 2 shown, the reinforcing member 27 is formed or disposed between the first electronic component 22 and the conductive pillar 212 , but the present application is not limited thereto.

[0101] For example, Figure 3A is a cross-sectional schematic diagram of a step in a method for manufacturing an electronic package 2 according to another embodiment of the present application, and the step corresponds to Figure 2E The steps shown are as follows. Figure 3A As shown, in this embodiment, the reinforcing member 27 is formed or disposed on the outer sides of the first electronic component 22 and the conductive pillar 212 , and the conductive pillar 212 is disposed between the first electronic component 22 and the reinforcing member 27 .

[0102] For another example, Figure 3B is a cross-sectional schematic diagram of a step in a method for manufacturing an electronic package 2 according to another embodiment of the present application, and the step corresponds to Figure 2E The steps shown are as follows. Figure 3B As shown, in this embodiment, the reinforcing member 27 is formed or configured to surround the conductive pillar 212 so that the conductive pillar 212 penetrates the reinforcing member 27 .

[0103] Since the electronic package 2 of the present application includes the reinforcing member 27, the volume of the first coating layer 213 can be reduced to 30%. In addition, the reinforcing member 27 has a higher hardness than the first coating layer 213 and has an adjustable coefficient of thermal expansion (CTE), so the strength and rigidity of the packaging structure can be improved to reduce the warpage of the large packaging structure of the electronic package 2, thereby facilitating the development of advanced packaging technology.

[0104] The above embodiments are used to illustrate the principles and effects of the present application, but are not used to limit the present application. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be as set forth in the claims.

Claims

1. An electronic package, characterized in that: include: a first electronic component; A conductive column is disposed around the first electronic component; A reinforcing member, disposed around the first electronic component; A first coating layer, coating the first electronic element, the conductive column and the reinforcing member; as well as The redistribution layer is disposed on the first electronic element, the conductive column, the reinforcement and the first side of the first cladding layer, and is electrically connected to the first electronic element and the conductive column.

2. The electronic package according to claim 1, wherein: The reinforcing member is a glass block, a metal block or a dummy chip.

3. The electronic package according to claim 1, wherein: The reinforcing member is arranged between the first electronic element and the conductive column.

4. The electronic package according to claim 1, wherein: The reinforcing piece is arranged on the outer sides of the first electronic element and the conductive column.

5. The electronic package according to claim 1, wherein: The conductive column penetrates the reinforcement member.

6. The electronic package according to claim 1, wherein: The electronic package also includes a first insulating layer disposed on the first covering layer, and the first electronic element is bonded to the first insulating layer through an adhesive layer via its inactive surface.

7. The electronic package according to claim 1, wherein: The electronic package also includes: The second electronic component is disposed on the first side of the redistribution layer and is electrically connected to the redistribution layer.

8. The electronic package according to claim 7, wherein: The electronic package also includes: The second encapsulating layer is disposed on the first side of the redistribution layer and encapsulates the second electronic component.

9. The electronic package according to claim 1, wherein: The electronic package also includes: The supporting structure has a first side and a second side opposite to each other, so that the first electronic element, the conductive column, the reinforcing member and the first cladding layer are arranged on the first side of the supporting structure and are electrically connected to the redistribution layer through the conductive column.

10. The electronic package according to claim 9, wherein: A plurality of electrical conductors are disposed on the second side of the supporting structure.

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