Chip packaging structure
By adopting a chip packaging structure in the hybrid package and using FOD film to wrap and superimpose the chips and components below, the problem of difficult packaging volume in the prior art is solved, and the packaging effect of high density and miniaturization is achieved.
Patent Information
- Application Number
- CN202421242815.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-03
- Publication Date
- 2025-02-25
- Estimated Expiration
- 2034-06-03
AI Technical Summary
In the prior art, it is difficult to achieve vertical superposition of chips and components in a hybrid package without increasing the area of the package substrate, so that the package volume cannot be effectively reduced.
A chip packaging structure is adopted, and the chip and components are fully wrapped by mounting the chip and components on the carrier, and the formal chip is wrapped and superimposed by FOD film to fill the space between the chip and the carrier, thereby achieving full wrapping of the chip and components.
Without increasing the area of the package carrier, the chips and components below are directly wrapped under the formal chip, which significantly improves the integration and packaging density and effectively reduces the packaging volume.
Smart Images
Figure CN222530440U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor packaging, and more specifically to a chip packaging structure. Background Art
[0002] As the integration of chip functions increases, the number of transistors on a single chip increases, and the chip size also increases. Under conventional packaging technology, in order to protect the fragile internal chip structure and achieve effective connection with external circuits, the size of the package body tends to increase as the chip size increases.
[0003] To solve this problem, the industry has developed a series of high-density and miniaturized packaging technologies, such as chip stacking (Chip Stacking or 3D packaging technology). By vertically stacking multiple chips together, the integration level can be greatly improved without increasing the area of the packaging substrate, and the packaging volume can be effectively reduced.
[0004] However, this approach will not work if you encounter a hybrid package where SMT components are still soldered around the chip and do not overlap vertically with the chip, which means the package size is not minimized. Figure 1 , Figure 2 and Figure 3 The packaging structure of the hybrid package in the prior art is as follows: Figure 1 The packaging structure mounts flip chips, face-up chips, and components on the substrate separately, which cannot be stacked vertically, and the packaging volume is large; Figure 2 and Figure 3 In this method, the chips, which are also upright chips, are stacked in the vertical direction, and the flip chips and components are mounted separately on the substrate, resulting in a larger package volume. Utility Model Content
[0005] In order to solve the above problems, the utility model provides a chip packaging structure that directly wraps all the lower chips and components under the upright chip without increasing the packaging carrier area, thereby greatly improving the integration and effectively reducing the packaging volume.
[0006] According to one aspect of the utility model, a chip packaging structure is provided, which includes a carrier, a lower chip and at least one component are mounted on the front side of the carrier, and the chip packaging structure also includes an upper chip, the upper chip is a front-mounted chip, a plastic packaging material 1 is arranged below the upper chip, the lower chip and the components are wrapped by the plastic packaging material 1, and the plastic packaging material 1 fills the space between the lower chip and the carrier, the upper chip longitudinally covers the lower chip and the components below, the upper chip is electrically connected to the carrier through welding wires, the carrier is a substrate or a lead frame, and the lower chip, components, upper chip and welding wires above the carrier are coated with plastic packaging material 2.
[0007] In some embodiments, the first molding compound is a FOD film.
[0008] In some embodiments, the lower chip is a flip chip or a face-up chip.
[0009] In some embodiments, the components are passive components.
[0010] Compared with the prior art, the beneficial effects of the present invention are as follows: in the chip packaging structure provided by the present invention, the flip chip / or the upright chip and the components are welded on a substrate or a lead frame, and the upright chip on the top is wrapped and stacked through the FOD (Flim on Die) process. Without increasing the packaging carrier area, the lower chip and the components are directly wrapped in the chip packaging structure under the upright chip. The introduction of this structure greatly improves the integration of the hybrid package, effectively reduces the package volume, and allows more chips to be placed inside the product with the same package size. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 It is a structural schematic diagram of an implementation method of a hybrid package in the prior art;
[0012] Figure 2 It is a structural schematic diagram of another embodiment of a hybrid package in the prior art;
[0013] Figure 3 It is a structural schematic diagram of another embodiment of a hybrid package in the prior art;
[0014] Figure 4 It is a structural schematic diagram of an implementation method of a chip packaging structure of the utility model. DETAILED DESCRIPTION
[0015] The utility model is further described below in conjunction with specific implementation methods.
[0016] like Figure 4As shown, a chip packaging structure of one embodiment of the utility model includes a carrier 1, the carrier 1 is a substrate or a lead frame, a lower chip 2 and at least one component 3 are mounted on the front of the carrier 1, and the chip packaging structure also includes an upper chip 5, the upper chip 5 is a positive chip, a plastic packaging material 4 is arranged below the upper chip 5, the lower chip 2 and the component 3 are wrapped by the plastic packaging material 4, and the plastic packaging material 4 fills the space between the lower chip 2 and the carrier 1, the upper chip 5 covers the lower chip 2 and the component 3 below longitudinally, the upper chip 5 is electrically connected to the carrier 1 through the welding wire 6, and the lower chip 2, the component 3, the upper chip 5 and the welding wire 6 above the carrier 1 are coated with a plastic packaging material 7. The plastic packaging material 4 is a FOD film. FOD (Flim on Die) is a film based on thermosetting resin and uses insulating materials such as silicon dioxide as fillers.
[0017] Figure 4 The middle lower chip 2 can be a flip chip, but in practical applications, the lower chip 2 can also be a normal chip. The components 3 are passive components, including but not limited to common surface mount passive components such as resistors, capacitors, and inductors.
[0018] The packaging process of the chip packaging structure described in this application is specifically described, and the steps are as follows:
[0019] Step 1: Take a carrier 1 , i.e., a substrate or a lead frame, and solder the lower chip 2 , i.e., a flip chip or a face-up chip, and components 3 onto the carrier 1 .
[0020] Step 2: A layer of FOD film is pasted on the bottom (i.e., non-functional surface) of the upper chip 5, i.e., the mounted chip, and is diced and divided into units at the same time as the upper chip 5.
[0021] Step 3: Place the upper chip with FOD film directly above the lower chip 2 and components 3. The FOD film is subjected to the combined effects of the mounting pressure and heat of the upper chip 5 to form a plastic encapsulation material 4 that covers the lower chip 2 and components 3 and fills the space between the lower chip 2 and the carrier 1, and the space between the lower chip 2 and the components. The thickness of the FOD film is 120 μm.
[0022] Compared with EMC (Epoxy molding compound / epoxy molding compound), the filling property of the product can be further improved through the bottom filling / FOD (Flim on Die) of extremely small particles.
[0023] Step 4: After the plastic encapsulation material 4 is solidified, the wire bonding 6 of the upper chip 5 is performed, and the upper chip 5 and the carrier 1 are interconnected through the wire bonding 6 .
[0024] Step 5: The lower chip 2 , components 3 , upper chip 5 and bonding wires 6 on the carrier 1 are encapsulated with a plastic encapsulation resin to form a second plastic encapsulation material 7 .
[0025] In the chip packaging structure provided by the utility model, the flip chip / or the upright chip and the component 3 are welded on a substrate or a lead frame, and the upright chip is used on the upper side to be wrapped and stacked through the FOD (Flim on Die) process. Without increasing the area of the packaging carrier 1, the chip 2 and the component 3 below are directly wrapped in the chip packaging structure under the upright chip. The introduction of this structure greatly improves the integration of the hybrid package and effectively reduces the package volume, so that more chips can be placed inside the product with the same package size.
[0026] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.
Claims
1. A chip packaging structure, comprising a carrier (1), wherein a lower chip (2) and at least one component (3) are mounted on the front side of the carrier (1), characterized in that: The chip packaging structure also includes an upper chip (5), the upper chip (5) is a front-mounted chip, a plastic encapsulation material (1) is provided below the upper chip (5), the lower chip (2) and the components (3) are wrapped by the plastic encapsulation material (4), and the plastic encapsulation material (4) fills the space between the lower chip (2) and the carrier (1), the upper chip (5) vertically covers the lower chip (2) and the components (3) below, the upper chip (5) is electrically connected to the carrier (1) through a welding wire (6), the carrier (1) is a substrate or a lead frame, and the lower chip (2), the components (3), the upper chip (5) and the welding wire (6) above the carrier (1) are coated with a plastic encapsulation material (7) on their peripheries.
2. The chip packaging structure according to claim 1, characterized in that: The first plastic packaging material (4) is a FOD film.
3. The chip packaging structure according to claim 2, characterized in that: The lower chip (2) is a flip chip or a face-up chip.
4. The chip packaging structure according to claim 3, characterized in that: The component (3) is a passive component.