Sigma-Delta Circuit And Related Method with Time Sharing Architecture

a time sharing and circuit technology, applied in the field of sigma-delta circuits, can solve the problems of wasting hardware areas, wasting direct implementations of audio processing, and increasing the complexity of the circuit of sigma-delta modulators, and wasting too much hardware areas

Inactive Publication Date: 2008-03-06
PRINCETON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The invention is a circuit and method for processing audio signals using a sigma-delta circuit with a time sharing architecture. The circuit includes a coefficient generation element, a sigma-delta processing element, and a storage element. The method involves generating coefficients, executing sigma-delta operations, and storing the results. The circuit can process multiple orders of sigma-delta operations simultaneously. The method also includes receiving a plurality of coefficients, a state signal, and selecting one coefficient to output based on the state signal. The results of the sigma-delta operations are quantized. The technical effects of this invention include improved processing speed and efficiency for audio signals."

Problems solved by technology

On this account, with the increasing of the orders of the sigma-delta operations, the circuit of the sigma-delta modulators becomes more and more complicated.
However, the fifth order sigma-delta modulator 30 needs at least eight adders, eighteen multipliers, and five integrators, which will waste hardware areas.
Direct implementations of audio processing will waste too much hardware areas and cost due to the audio processing only having frequencies of KHz.
Hence, most designs are implemented by general microprocessors such as central processing units (CPU) or digital signal processors (DSP) recently, but their hardware cost is too high and will result in raising operational frequencies, which is difficult to be implemented in FPGA.
These elements will increase not only manufacture cost but also hardware areas.

Method used

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  • Sigma-Delta Circuit And Related Method with Time Sharing Architecture
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  • Sigma-Delta Circuit And Related Method with Time Sharing Architecture

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Embodiment Construction

[0022]Please refer to FIG. 4. FIG. 4 is a diagram of a sigma-delta circuit 40 with a time sharing architecture according to an embodiment of the present invention. The sigma-delta circuit 40 includes a coefficient generation element 41, a sigma-delta processing element 44, and a storage element 47. The coefficient generation element 41 is used for generating coefficients a, c, and g for sigma-delta operations, and includes a first multiplexer MUX1, a second multiplexer MUX2, and a third multiplexer MUX3. The first multiplexer MUX1 includes n input ends, a control end 411, and an output end 412. The n input ends are used for receiving n coefficients a[1]˜a[n], the control end 411 is used for receiving a state signal ST1, and the output end 412 is used for selecting one coefficient a from the n coefficients a[1]˜a[n] to output. The second multiplexer MUX2 includes n input ends, a control end 413, and an output end 414. The n input ends are used for receiving n coefficients c[1]˜c[n], ...

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Abstract

A sigma-delta circuit with time sharing architecture includes a coefficient generation element, a sigma-delta processing element, and a storage element. The coefficient generation element is used for generating coefficients for sigma-delta operations. The sigma-delta processing element is used for executing sigma-delta operations according to the coefficients generated by the coefficient generation element. The storage element is used for storing results of the sigma-delta operations executed by the sigma-delta processing element. The sigma-delta circuit is used for executing a plurality of orders of sigma-delta operations through the coefficient generation element, the sigma-delta processing element and the storage element.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a sigma-delta circuit and related method, and more particularly, to a sigma-delta circuit and related method with a time sharing architecture.[0003]2. Description of the Prior Art[0004]Recently, audio processing is implemented by general microprocessors such as central processing units (CPU) or digital signal processors (DSP). Another method for audio processing is implemented in field programmable gate arrays (FPGA), due to operational frequency of sigma-delta modulators being low enough to be implemented in FPGA easily. The sigma-delta modulators are already widespreadly applied to analog-to-digital converters (ADC) and digital-to-analog converters (DAC), because of the sigma-delta modulators having a capability of noise shaping to restrain quantized noise within signal bandwidths and to raise the signal to noise ratio further. Hence, the sigma-delta modulators are popular in applicati...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H03M3/00
CPCH03M3/474
InventorCHIEN, HUNG-LUNKAO, DE-YU
OwnerPRINCETON TECH CORP