One-time programable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof

a one-time programable and data-judging technology, applied in the field of one-time programable cells, semiconductor integrated circuits including the same, and data judging methods, can solve problems such as the inability to read b>1/b> and the correct value of data

Inactive Publication Date: 2013-07-11
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach allows accurate data judgment in OTP cells, preventing misreadings and ensuring reliable storage of chip IDs and settings, regardless of resistance variations in the anti-fuse element.

Problems solved by technology

This result in a problem that a correct value of data such as a chip ID and a setting parameter stored in the semiconductor integrated circuit where a cell array is composed of this OTP cell 1 cannot be read.

Method used

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  • One-time programable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof
  • One-time programable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof
  • One-time programable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof

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Embodiment Construction

[0035]An exemplary embodiment of the present invention will be described in detail below with reference to the accompanying drawings. In the exemplary embodiment, the present invention is applied to a semiconductor integrated circuit and an OTP cell. FIG. 1 shows a configuration of a semiconductor integrated circuit 100 according to this exemplary embodiment. As shown in FIG. 1, the semiconductor integrated circuit 100 includes a logic and memory part 101 and a fuse part 102.

[0036]The logic and memory part 101 is composed of logic circuits that perform logic operations. Further, the logic and memory part 101 includes an internal power supply 103 that supplies a voltage VCOR of about 1 to 2 [V] as a power supply voltage of the logic circuits. Furthermore, the logic and memory part 101 includes a judgment circuit 110 which is described later. The logic circuits of the logic and memory part 101 are composed of transistors that have a breakdown voltage of about the voltage VCOR level. I...

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Abstract

Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected between the first node and a first data line applied with a predetermine first voltage, and enters an off state from an on state according to a first control signal; and a detection part that detects write data of the anti-fuse element according to whether a voltage of the first node is substantially the same as the first voltage or substantially the same as a supply voltage of the first power supply terminal when the first switch circuit enters the off state.

Description

INCORPORATION BY REFERENCE[0001]This application is a Continuation Application of U.S. application Ser. No. 12 / 898,210 filed Oct. 5, 2010, which claims the benefit of priority from Japanese patent application No. 2009-231535, filed on Oct. 5, 2009, the disclosures of which are incorporated herein in their entirety by reference.BACKGROUND[0002]1. Field of the Invention[0003]The present invention relates to an one-time programmable cell, a semiconductor integrated circuit including the same, and data judging method thereof.[0004]2. Description of Related Art[0005]An OTP (One-time programmable) cell is widely applied as a single memory or a memory array in a semiconductor integrated circuit. For instance, information written in the OTP cell array is used as a chip ID, a setting parameter, or the like.[0006]A configuration of an OTP cell is disclosed in Japanese Unexamined Patent Application Publication No. 2008-204600, as a prior art. FIG. 6 shows the configuration of an OTP cell 1 of ...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G11C17/16
CPCG11C17/12G11C17/165G11C17/18
InventorFURUKAWA, HIROYUKINARITAKE, ISAO
OwnerRENESAS ELECTRONICS CORP