Error correction circuit

a technology of error correction and circuit, applied in error detection/correction, instruments, coding, etc., can solve the problems of one-bit error correction but not more than two-bit error correction, and store data is susceptible to disturbances

Active Publication Date: 2007-11-20
LAPIS SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The solution ensures that microcomputers with built-in flash memory do not malfunction due to more-than-two-bit errors, improving data reliability and allowing flexible selection of circuit capacity based on flash memory reliability.

Problems solved by technology

The reason is that stored data are susceptible to change by disturbances from outside the memory when data-retention, data-write, or data-read is done.
However, a conventional ECC circuit, which adds a six-bit width checkbit to 32-bit width memory data, has a problem in that it can do one-bit error correction but not more-than-two-bit error correction.
A problem arises because a malfunction occurs in a MICOM using a built-in flash memory as a memory device of the CPU programs when a more-than-two-bit error occurs.

Method used

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first embodiment

[0020]FIG. 1 is a block diagram illustrating the basic configuration of an ECC in accordance with a first preferred embodiment of the present invention. The ECC is composed of a CPU 100, a flash memory 101, a selected-bit reverse circuit 105, an ECC 108 for one-bit error correction circuit, a flash memory data register 109, a checkbit generation circuit 111, an ECC data register 113 for retention of the ECC data, an address register 114 to store output addresses from the CPU 100, a bit comparing circuit 115 to compare the output data from the ECC data register 113 with the output data from the flash memory data register 109, a timing control circuit 118 to control the data-setting timing in each component such as the flash memory data register 109, error data memories (error data memory unit) 128a-128x storing error bits, address memories (address memory unit) 127a-127x to store the address where an error occurs, a write control circuit 125 to control writing data in the aforementio...

second embodiment

[0043]A second embodiment will now be explained. In view of the similarity between the first and second embodiments, the parts of the second embodiment that are identical to the parts of the first embodiment will be given the same reference numerals as the parts of the first embodiment. Moreover, the descriptions of the parts of the second embodiment that are identical to the parts of the first embodiment may be omitted for the sake of brevity.

[0044]FIG. 6 is a block diagram illustrating the configuration of an error correction circuit according to a second embodiment of the present invention. The main difference between the first embodiment of the present invention and this one is that an external input terminal 601 is equipped and an input signal 602 that is inputted from this input terminal 601 is inputted to the timing control circuit 118. Referring to FIG. 6, the error correction circuit of the second embodiment will now be explained as below.

[0045]When the input signal 602 fro...

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Abstract

An error correction circuit includes a selected-bit reverse circuit, an ECC circuit, a checkbit generation circuit, an ECC data register, a bit-comparing circuit, and an address memory unit. The selected-bit reverse circuit includes memory data and check data from the memory unit. The ECC circuit corrects a one-bit error. The checkbit generation circuit generates checkbits. The ECC data register stores the corrected data and the checkdata. The bit-comparing circuit compares each bit between the output data A from the selected-bit reverse circuit and the output data A′ from the ECC data register. The address memory unit stores an address corresponding to the memory data when the bit-comparing circuit detects a discrepancy among the data A and the data A′. The error data memory unit writes the discrepancy information at the bit-location. The data OR circuit generates the first signal.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention generally relates to technology to improve data reliability of flash memory. More specifically, the present invention relates to technology to improve data reliability of flash memory mainly in ICs such as microcomputers having built-in flash memories.[0003]2. Background Information[0004]In conventional ICs such as microcomputers (referred to as MICOMs hereafter) that have built-in flash memories, error checking and correcting circuits (referred to as ECC circuits or EECs hereafter ) have been provided. The reason is that stored data are susceptible to change by disturbances from outside the memory when data-retention, data-write, or data-read is done. Especially, when a flash memory is used as a memory device for operation programs of MICOMs, a malfunction never fails to occur even if a CPU receives just one error bit, and then a checkbit for error checking is stored in addition to the data itself...

Claims

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Application Information

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Patent Type & AuthorityPatents(United States)
IPC IPC(8): G11C29/00G06F12/16G11C29/42H03M13/00H03M13/37
CPCG06F11/1048G11C2029/0411
InventorYUSA, ATSUSHI
OwnerLAPIS SEMICON CO LTD