Statistical timing analysis method and device based on improved adaptive random configuration method
A technique for static timing analysis and timing diagrams, used in computing, special data processing applications, instruments, etc.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Publication Date
- 2011-05-11
- Estimated Expiration
- Not applicable · inactive patent
Smart Images
Figure 1 Figure 2 Figure 3
Abstract
Description
Technical field:
[0001] The invention belongs to the field of integrated circuits, and in particular relates to a statistical static timing analysis method based on an improved self-adaptive random configuration method. Background technique
[0002] As the feature size of integrated circuits enters the nanometer level, the impact of process deviation on circuit performance is becoming more and more serious. In order to analyze the impact of process deviation on the timing of integrated circuits, Statistical Static Timing Analysis (SSTA) was introduced into timing analysis. "Statistical Time-Series Analysis: From Fundamentals to State-of-the-art", 27(4), pp. 589-607. In statistical static timing analysis, due to the influence of random process deviation, the delay of the circuit is no longer a definite value, but a random variable with a certain distribution. Statistical static timing analysis analyzes circuit timing by passing a random distribution of delays through the ci...
Examples
Embodiment Construction
[0028] The present invention is based on the statistical static timing analysis method of the improved adaptive random configuration method MASCM such as figure 1 shown, including the following steps:
[0029] step one : Establish the statistical delay model of gate unit and interconnection line based on random orthogonal polynomial. Firstly, the independent random vectors of d-dimensional normal distribution obtained after principal component analysis on the process parameter disturbance are as follows: ,here represents the number of random variables. The delays of gate units and interconnection lines can be expressed in the form of second-order random Hermite orthogonal polynomial expansion based on these random variables, namely
[0030] (1)
[0031] in express Dimensional Hermite random orthogonal polynomials. For the specific form of Hermite orthogonal polynomials, see the paper "Stochastic Analysis of Inner Link Performance in Existing Pro...