Printed circuit board and storage device including the printed circuit board

Abstract

Provided is a printed circuit board and a storage device including the printed circuit board. The printed circuit board may include a controller socket, a first branch point, a second branch point, and a third branch point, a first socket and a second socket arranged on the top surface, and a third socket and a fourth socket arranged on the bottom surface. The first branch point may be spaced apart from the controller socket by a first distance in a horizontal direction parallel to the top surface, and may be electrically connected to the controller socket. The second branch point may be spaced apart from the first branch point by a second distance longer than the first distance, and may be electrically connected to the first branch point, the first socket, and the third socket. The third branch point may be spaced apart from the first branch point by a third distance longer than the first distance, and may be electrically connected to the first branch point, the second socket, and the fourth socket.

Description

[0001] This patent application claims the benefit of Korean Patent Application No. 10-2018-0061301 filed on May 29, 2018, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Example embodiments relate to a semiconductor memory.For example, at least some example embodiments relate to a printed circuit board and / or a memory device including the printed circuit board. Background Art

[0003] Semiconductor memory devices can be classified into volatile memory devices that lose data stored therein when power is off (e.g., static random access memory (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM)) and nonvolatile memory devices that retain data stored therein even when power is off (e.g., read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM)).

[0004] In a flash memory based storage device, various operations are performed based on electrical signals. As an example, the storage device may include a controller and a non-volatile memory device configured to communicate with each other through a plurality of signal lines. In order to improve the reliability of the storage device, many schemes are being implemented to maintain the reliability of the signal. However, due to the increasing demand for storage devices with fast operating speeds and high integration density, it may be difficult to maintain signal reliability. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a high-reliability printed circuit board and / or a memory device including the high-reliability printed circuit board.

[0006] According to some example embodiments conceived by the present invention, a printed circuit board (PCB) having a top surface and a bottom surface may include: a controller socket on the top surface; a first socket and a second socket on the top surface; a third socket and a fourth socket on the bottom surface, facing the first socket and the second socket, respectively; and a plurality of signal lines connecting the controller socket to the first socket, the second socket, the third socket and the fourth socket, the plurality of signal lines being connected at a plurality of branch points, the plurality of branch points including: a first branch point electrically connected to the controller socket so that the first branch point is spaced a first distance from the controller socket in a horizontal direction parallel to the top surface, a second branch point electrically connected to the first branch point, the first socket and the third socket so that the second branch point is spaced a second distance from the first branch point, the second distance being longer than the first distance in the horizontal direction, and a third branch point electrically connected to the first branch point, the second socket and the fourth socket so that the third branch point is spaced a third distance from the first branch point, the third distance being longer than the first distance in the horizontal direction.

[0007] According to some example embodiments conceived in the present invention, a storage device may include: a plurality of nonvolatile memory devices, including a first nonvolatile memory device, a second nonvolatile memory device, a third nonvolatile memory device, and a fourth nonvolatile memory device; a memory controller configured to control the plurality of nonvolatile memory devices; and a plurality of signal lines, including: a first signal line configured to electrically connect the memory controller to a first branch point, a second signal line configured to electrically connect the first branch point to a second branch point, the second signal line being longer than the first signal line, a third signal line configured to electrically connect the first branch point to a third branch point, the third signal line being longer than the first signal line, a fourth signal line configured to electrically connect the second branch point to the first nonvolatile memory device, a fifth signal line configured to electrically connect the second branch point to the second nonvolatile memory device, a sixth signal line configured to electrically connect the third branch point to the third nonvolatile memory device, and a seventh signal line configured to electrically connect the third branch point to the fourth nonvolatile memory device.

[0008] According to some example embodiments of the inventive concept, a storage device may include: a memory controller; a plurality of nonvolatile memory devices including a first nonvolatile memory device, a second nonvolatile memory device, a third nonvolatile memory device, and a fourth nonvolatile memory device; and a printed circuit board including a top surface and a bottom surface, the top surface having the first nonvolatile memory device and the second nonvolatile memory device mounted thereon, the bottom surface having the third nonvolatile memory device and the fourth nonvolatile memory device mounted thereon such that the third nonvolatile memory device faces the first nonvolatile memory device and the fourth nonvolatile memory device faces the second nonvolatile memory device, the printed circuit board including a memory controller connected to the memory controller; The plurality of signal lines of the plurality of nonvolatile memory devices are connected at a plurality of branch points, the plurality of branch points comprising: a first branch point electrically connected to a memory controller such that the first branch point is spaced a first distance from the memory controller in a horizontal direction parallel to the top surface, a second branch point electrically connected to the first branch point, the first nonvolatile memory device and the third nonvolatile memory device such that the second branch point is spaced a second distance from the first branch point in the horizontal direction, the second distance being longer than the first distance, and a third branch point electrically connected to the first branch point, the second nonvolatile memory device and the fourth nonvolatile memory device such that the third branch point is spaced a third distance from the first branch point in the horizontal direction, the third distance being longer than the first distance.

[0009] According to some example embodiments conceived in the present invention, a printed circuit board (PCB) having a top surface and a bottom surface may include: a controller socket, arranged on the top surface; a plurality of sockets, on the PCB, the plurality of sockets including: a first socket, on the top surface, a second socket, on the top surface, spaced apart from the first socket, a third socket, on the top surface, between the first socket and the second socket, a fourth socket, on the bottom surface, facing the first socket, a fifth socket, on the bottom surface, facing the second socket, and a sixth socket, on the bottom surface, facing the third socket; and a plurality of signal lines, connecting the controller socket to the plurality of sockets, the plurality of signal lines being connected at a plurality of branch points, the plurality of branch points including: a first branch point, electrically connected to the controller socket, a second branch point, electrically connected to the first branch point, the first socket and the second socket, and a third branch point, electrically connected to the first branch point, the fourth socket and the fifth socket.

[0010] According to some example embodiments of the inventive concept, a memory device may include: a memory controller; a plurality of nonvolatile memory devices including a first nonvolatile memory device, a second nonvolatile memory device, a third nonvolatile memory device, a fourth nonvolatile memory device, a fifth nonvolatile memory device, and a sixth nonvolatile memory device; and a printed circuit board including a top surface and a bottom surface, the top surface having the first nonvolatile memory device and the second nonvolatile memory device mounted thereon and the third nonvolatile memory device mounted between the first nonvolatile memory device and the second nonvolatile memory device; A printed circuit board comprises a first nonvolatile memory device, a second nonvolatile memory device, and a third nonvolatile memory device. The printed circuit board comprises a first branch point electrically connected to the memory controller, a second branch point electrically connected to the first branch point, the first nonvolatile memory device and the second nonvolatile memory device, and a third branch point electrically connected to the first branch point, the fourth nonvolatile memory device and the fifth nonvolatile memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0012] Figure 1 is a block diagram illustrating a storage device according to an example embodiment of the inventive concept;

[0013] Figure 2A and Figure 2B are block diagrams and timing diagrams provided to illustrate signal flow between a memory controller and a non-volatile memory device;

[0014] Figure 3A and 3B are block diagrams and timing diagrams provided to illustrate signal flows in a memory device according to example embodiments of the inventive concept;

[0015] Figure 4 is a block diagram illustrating a signal flow in a storage device according to an example embodiment of the inventive concept;

[0016] FIG. 5A to FIG. 5C Each of the Figure 4 A timing diagram of the signal flow shown in ;

[0017] Figure 6 is a block diagram illustrating a signal flow in a storage device according to an example embodiment of the inventive concept;

[0018] Figure 7is a block diagram illustrating an example of a storage device according to an example embodiment of the inventive concept;

[0019] Figure 8 is a diagram illustrating an example of a storage device according to an example embodiment of the inventive concept;

[0020] 9A to 9C It is shown Figure 8 An illustration of an example of a printed circuit board;

[0021] FIG. 10A to FIG. 10C It is shown Figure 8 An illustration of an example of a printed circuit board;

[0022] Fig.11A and Fig. 11B It is shown Figure 8 An illustration of an example of a printed circuit board;

[0023] Fig. 12A and Fig. 12B is a diagram illustrating an example of a printed circuit board according to an example embodiment of the inventive concept;

[0024] Fig.13A and Fig. 13B is a timing diagram illustrating the attenuation effect of a reflected signal according to an example embodiment of the inventive concept;

[0025] Fig.14A and Fig. 14B is a timing diagram illustrating the attenuation effect of a reflected signal according to an example embodiment of the inventive concept;

[0026] Fig.15 is a block diagram illustrating an SSD system using a storage device according to an example embodiment of the inventive concept.

[0027] It should be noted that these figures are intended to describe the general features of the methods, structures and / or materials used in specific exemplary embodiments and to supplement the text description provided below. However, these drawings are not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given exemplary embodiment and should not be interpreted as limiting or restricting the range of values ​​or properties contained in the exemplary embodiments. For example, the relative thickness and position of molecules, layers, regions and / or structural elements may be reduced or exaggerated for clarity. Similar or identical reference numerals used in the various drawings are intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0028] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown.

[0029] Figure 1is a block diagram illustrating a memory device according to an example embodiment of the inventive concept.

[0030] Reference Figure 1 , the memory device 100 may include a memory controller 110 and a plurality of nonvolatile memory devices 120 .

[0031] The memory controller 110 may control the nonvolatile memory device 120. For example, the memory controller 110 may control the nonvolatile memory device 120 through a plurality of channels CH1-CHn, respectively.

[0032] The nonvolatile memory devices 120 may be operated based on signals transmitted from the memory controller 110 through the channels CH1-CHn. For example, under the control of the memory controller 110, each of the nonvolatile memory devices 120 may be configured to store data transmitted through the channels CH1-CHn and / or transmit the stored data to the memory controller 110 through the channels CH1-CHn.

[0033] In some example embodiments, each of the nonvolatile memory devices 120 may be a NAND FLASH memory chip or a multi-chip package including a plurality of NAND FLASH memory chips, but the inventive concept is not limited thereto. For example, each of the nonvolatile memory devices 120 may be one of various memory devices such as a static RAM (SRAM) device, a dynamic RAM (DRAM) device, a synchronous DRAM (SDRAM) device, a phase change RAM (PRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, and a ferroelectric RAM (FRAM) device.

[0034] In some example embodiments, each or one of the channels CH1-CHn (e.g., the first channel CH1) may be used to allow at least two of the nonvolatile memory devices 120 to communicate with the memory controller 110. In other words, the memory device 100 may have a multi-rank structure (or topology). For example, a signal intended to be transmitted to a first memory device connected to the first channel CH1 may be provided to other memory devices connected to the first channel CH1.

[0035] Typically, a reflection signal generated by such other memory devices may be sent to the first memory device. The reflection signal sent to the first memory device may affect the normally received signal of the first memory device. This may result in abnormal signal reception or failure in the first memory device.

[0036] In contrast, in one or more example embodiments, according to the memory device 100 of the example embodiments of the inventive concept, the channel or signal line between the memory controller 110 and the non-volatile memory device 120 may be configured to have an adjusted (e.g., increased) length at a specific portion. Therefore, the memory device 100 may reduce the influence of the reflected signal on the plurality of non-volatile memory devices connected to the same channel. Some features of the memory device 100 associated with the length of the signal line will be described in more detail with reference to the accompanying drawings.

[0037] In some example embodiments, each of the nonvolatile memory devices 120 may be a memory package including a plurality of nonvolatile memory chips or dies. In some example embodiments, since each of the nonvolatile memory devices 120 includes a plurality of nonvolatile memory chips or dies, a large-capacity storage device may be easily implemented. For ease of description, the term "memory device" will be used in the following description, but it may also be interpreted as referring to a memory package including a plurality of memory chips.

[0038] Figure 2A and Figure 2B 1 is a block diagram and a timing diagram provided to describe a signal flow between a memory controller and a nonvolatile memory device. For ease of description, the following description will focus on a portion of the memory device 100 in which the first nonvolatile memory device NVM1 to the fourth nonvolatile memory device NVM4 connected to the first channel CH1 and one of the plurality of signal lines constituting the first channel CH1 are provided. However, the inventive concept is not limited thereto, and in a specific example embodiment, the first channel CH1 may also include a plurality of signal lines. In a specific example embodiment, the memory controller 11 may also be connected to other nonvolatile memory devices through the first channel CH1.

[0039] exist Figure 2B In the timing diagram, the horizontal axis and vertical axis represent time and signal amplitude respectively. For ease of description, Figure 2B The timing diagram is shown in a simplified manner, but actually the waveform of the signal provided by the signal line is not limited to Figure 2B waveform.

[0040] Reference Figure 2A , the memory controller 11 may be connected to the first to fourth nonvolatile memory devices NVM1 to NVM4 through signal lines S1-S7 of the first channel CH1. In some example embodiments, the signal lines S1-S7 of the first channel CH1 may represent a single interconnect structure for transmitting one of the other control signals or the data signal DQ to at least one of the nonvolatile memory devices NVM1-NVM4.

[0041] For example, the signal lines S1-S7 may be used to provide a signal (e.g., a data signal DQ) to each of the nonvolatile memory devices NVM1-NVM4. In other words, each of the first to fourth nonvolatile memory devices NVM1 to NVM4 may be configured to receive the same signal transmitted from the memory controller 11 through the signal lines S1-S7 of the first channel CH1. To this end, the first channel CH1 may include a plurality of branch points B1, B2, and B3, and may be divided into a plurality of parts P0, P1, and P2 based on the positions of the branch points B1, B2, and B3.

[0042] In some example embodiments, the portions P0, P1, and P2 may be defined in such a manner that three of the signal lines S1-S7 meet each other at each of the branch points B1, B2, and B3. For example, the zeroth portion P0 may include a signal line S1 from the memory controller 11 to the first branch point B1. The first portion P1 may include a signal line S2 from the first branch point B1 to the second branch point B2 and a signal line S3 from the first branch point B1 to the third branch point B3. The second portion P2 may include signal lines S4 and S5 from the second branch point B2 to the first nonvolatile memory device NVM1 and the second nonvolatile memory device NVM2 and signal lines S6 and S7 from the third branch point B3 to the third nonvolatile memory device NVM3 and the fourth nonvolatile memory device NVM4. In other words, each signal line may be branched into two signal lines at branch points B1 , B2 , and B3 , and thus the memory controller 11 and each of the first to fourth nonvolatile memory devices NVM1 to NVM4 may be electrically connected to each other.

[0043] In some example embodiments, the zeroth part P0 may include one signal line (e.g., S1). The first part P1 may include two signal lines (e.g., S2 and S3). The second part P2 may include four signal lines (e.g., S4, S5, S6, and S7). However, the inventive concept is not limited to this example, and the number of signal lines in each part may be changed according to the number of nonvolatile memory devices connected to a single channel.

[0044] In some example embodiments, the memory controller 11 may use an additional control signal (e.g., a chip select signal) to select a nonvolatile memory device to which a signal is to be transmitted. For example, in the case where the memory controller 11 transmits an input signal to the first nonvolatile memory device NVM1, the memory controller 11 may activate a chip select signal for selecting the first nonvolatile memory device NVM1, and then may transmit the input signal to the first to fourth nonvolatile memory devices NVM1 to NVM4 through signal lines S1-S7. In some example embodiments, the chip select signal may be provided to each of the first to fourth nonvolatile memory devices NVM1 to NVM4 through additional signal lines different from each other.

[0045] Here, since the input signal is provided not only to the selected device (e.g., the first nonvolatile memory device NVM1) but also to the unselected devices (e.g., the nonvolatile memory devices NVM2-NVM4), a reflected wave or signal may be generated by the unselected nonvolatile memory devices NVM2-NVM4. For example, in the case where the memory controller 11 transmits the input signal prepared for the first nonvolatile memory device NVM1 to the first nonvolatile memory device NVM1 through the signal lines S1-S7, the third nonvolatile memory device NVM3 may generate a reflected signal due to impedance mismatch at the input end of the third nonvolatile memory device NVM3.

[0046] In some example embodiments, each of the first to fourth nonvolatile memory devices NVM1 to NVM4 may include an on-chip termination (ODT) resistor for impedance matching. The ODT resistor may be provided to achieve impedance matching between a signal line and a plurality of memory devices, thereby blocking (or optionally, preventing) generation of a reflection signal. However, in the case where the operating speed of the memory device 100 is higher than a certain speed (i.e., the memory device 100 is configured to perform high-speed operation), it may be difficult for a conventional ODT resistor to effectively suppress the reflection signal.

[0047] exist Figure 2A In FIG. 1 , the dotted line represents the input signal from the memory controller 11, and the single-point dashed line represents the reflected signal from the third nonvolatile memory device NVM3. Figure 2A As shown, the reflection signal from the third nonvolatile memory device NVM3 can be sent to the first nonvolatile memory device NVM1 through the signal lines S6, S3, S2 and S4. In other words, the first nonvolatile memory device NVM1 can not only receive the input signal from the memory controller 11, but also receive the reflection signal from the third nonvolatile memory device NVM3.

[0048] In this case, it may be difficult for the first nonvolatile memory device NVM1 to normally determine the input signal. Figure 2B As shown, the sensing margin of the input signal may be a first time T1. At a specific operating speed, the reflection signal may be transmitted to the first nonvolatile memory device NVM1 within the first time T1 or in a rising edge region. In this case, the reflection signal may cause signal distortion within the first time T1, and as a result, the first nonvolatile memory device NVM1 may have difficulty in accurately determining the input signal.

[0049] Figure 3A and Figure 3B are block diagrams and timing diagrams provided to illustrate signal flows in a memory device according to example embodiments of the inventive concept. For concise description, previously described elements may be identified by reference numerals without repeating overlapping descriptions thereof.

[0050] Reference Figure 3A , the memory device 100 may include a memory controller 110 and first to fourth nonvolatile memory devices NVM1 to NVM4. The first channel CH1 may include signal lines SL01, SL11, SL12, SL21, SL22, SL23, and SL24, and the memory controller 110 may be connected to each of the first to fourth nonvolatile memory devices NVM1 to NVM4 through the signal lines SL01, SL11, SL12, SL21, SL22, SL23, and SL24 included in the first channel CH1. Similar to the previously described structure, the first channel CH1 may include a plurality of branch points BP11, BP21, and BP22, and may be divided into a zeroth part PR0, a first part PR1, and a second part PR2 based on the positions of the branch points BP11, BP21, and BP22. This division of the first channel CH1 is similar to that of the previous example, and therefore, a detailed description thereof will be omitted.

[0051] In the memory device 100 according to the example embodiment of the inventive concept, the length of the channel or the length of the signal line in a specific portion may be adjusted to reduce the undesired interference between nonvolatile memory devices that may be caused by the reflected signal. Figure 3A In the structure of Figure 2A 3A , the lengths of the signal lines SL11 and SL12 in the first portion PR1 may be increased. In other words, the lengths of the signal lines SL11 and SL12 in FIG. 3A may be respectively Figure 2A The lengths of the signal lines S2 and S3 are long.

[0052] In some example embodiments, the length of each of the signal lines SL11 and SL12 in the first portion PR1 may be longer than the length of the signal line SL01 in the zeroth portion PR0. In a specific embodiment, the length of each of the signal lines SL11 and SL12 in the first portion PR1 may be increased to block (or, alternatively, prevent) a reflection signal from the third nonvolatile memory device NVM3 or the fourth nonvolatile memory device NVM4 from affecting an input signal to be transmitted to the first nonvolatile memory device NVM1 or the second nonvolatile memory device NMV2. In a specific example embodiment, the length of each of the signal lines SL11 and SL12 in the first portion PR1 may be increased in such a manner that the reflection signal is attenuated below a specific level. Here, the specific level may be determined to sufficiently block (or, alternatively, prevent) a reflection signal from the third nonvolatile memory device NVM3 or the fourth nonvolatile memory device NVM4 from affecting an input signal to be transmitted to the first nonvolatile memory device NVM1 or the second nonvolatile memory device NMV2. In certain example embodiments, the lengths of the signal lines SL11 and SL12 in the first portion PR1 may be increased to delay the reflected signal for a certain period of time. Here, the certain period of time may be determined to sufficiently block (or, alternatively, prevent) the reflected signal from the third nonvolatile memory device NVM3 or the fourth nonvolatile memory device NVM4 from affecting the input signal to be transmitted to the first nonvolatile memory device NVM1 or the second nonvolatile memory device NVM2.

[0053] For example, in the case where the memory controller 110 transmits an input signal prepared for the first nonvolatile memory device NVM1, the input signal may be provided to the first nonvolatile memory device NVM1 through the signal lines SL01, SL11, and SL21. In this case, the input signal may also be provided to the third nonvolatile memory device NVM3 through the signal lines SL01, SL12, and SL23. As described above, the reflection signal may be generated by the third nonvolatile memory device NVM3 and may be transmitted to the first nonvolatile memory device NVM1 through the signal lines SL23, SL12, SL11, and SL21.

[0054] In this case, due to the increase in the length of each of the signal lines SL12 and SL11 in the first portion PR1, it is possible to effectively prevent or suppress the reflected signal from the third nonvolatile memory device NVM3 from affecting the input signal (i.e., the signal to be transmitted to the first nonvolatile memory device NVM1). Figure 3BAs shown, since each of the signal lines SL12 and SL11 in the first portion PR1 has an increased length, the signal lines SL11 and SL12 in the first portion PR1 can allow the reflected signal from the third nonvolatile memory device NVM3 to have an attenuated amplitude below a specific level. In other words, due to its attenuated amplitude, the reflected signal can have a small influence on the input signal to be transmitted to the first nonvolatile memory device NVM1. That is, since the reflected signal should be transmitted through the lengthened signal lines SL12 and SL11, the reflected signal can have a reduced amplitude or lost energy when it is transmitted to the first nonvolatile memory device NVM1. This can make it possible to reduce the influence of the reflected signal generated by other nonvolatile memory devices on the operation of the first nonvolatile memory device NVM1.

[0055] In a specific example embodiment, the signal lines SL11 and SL12 in the first portion PR1 may be configured to delay the reflected signal for a specific time. For example, this may allow the reflected signal to be sent to the first nonvolatile memory device NVM1 after the first time T1 (i.e., the sensing margin) of the input signal, thereby reducing the influence of the reflected signal on the first nonvolatile memory device NVM1. In other words, since the lengthened signal lines SL12 and SL11 are located on the transmission path of the reflected signal from the third nonvolatile memory device NVM3 to the first nonvolatile memory device NVM1, the transmission time of the reflected signal may be increased by the delay time given by the increased signal line length; that is, it takes a longer time to send the reflected signal from the third nonvolatile memory device NVM3 to the first nonvolatile memory device NVM1. This means that the reflected signal from the third nonvolatile memory device NVM3 does not affect the input signal to be sent to the first nonvolatile memory device NVM1, or the first nonvolatile memory device NVM1 may determine the input signal normally without any influence of the reflected signal.

[0056] Although not shown in the drawings, due to the increased length of the signal lines SL11 and SL12 in the first portion PR1, the influence of the reflection signal generated by the fourth nonvolatile memory device NVM4 on the operation of the first nonvolatile memory device NVM1 can be reduced. In addition, the influence of the reflection signal generated by the third nonvolatile memory device NVM3 or the fourth nonvolatile memory device NVM4 on the operation of the second nonvolatile memory device NVM2 can be reduced. In a specific embodiment, the influence of the reflection signal generated by the first nonvolatile memory device NVM1 or the second nonvolatile memory device NVM2 on the operation of the third nonvolatile memory device NVM3 or the fourth nonvolatile memory device NVM4 can also be reduced. In other words, an undesirable interference phenomenon caused by reflection signals generated by different groups between the first group including the first nonvolatile memory device NVM1 and the second nonvolatile memory device NVM2 and the second group including the third nonvolatile memory device NVM3 and the fourth nonvolatile memory device NVM4 can be reduced.

[0057] As described above, the signal lines SL11 and SL12 may be used to reduce or attenuate the amplitude of the reflection signal generated by the first to fourth nonvolatile memory devices NVM1 to NVM4 to below a specific level. In this case, the influence of the reflection signal on the input signal to be transmitted to the activated nonvolatile memory device may be reduced.

[0058] In certain example embodiments, the signal lines SL11 and SL12 may be used to delay the transmission of the reflection signal generated by the first nonvolatile memory device NVM1 to the fourth nonvolatile memory device NVM4 by a certain delay time. Here, the certain delay time may be determined to sufficiently block (or, alternatively, prevent) the generated reflection signal from affecting another nonvolatile memory device during an activation period of the other nonvolatile memory device. For example, the certain delay time may be determined in consideration of the operating speed of the memory device 100.

[0059] Figure 4 is a block diagram illustrating a signal flow in a memory device according to an example embodiment of the inventive concept. FIG. 5A to FIG. 5C Each of the Figure 4 For simplicity of description, previously described elements may be identified by reference numerals without repeating their repeated description.

[0060] Reference Figure 4, the memory device 200 may include a memory controller 210 and first to fourth nonvolatile memory devices NVM1 to NVM4. Similar to the previously described structure, the memory controller 210 may be connected to the first to fourth nonvolatile memory devices NVM1 to NVM4 through signal lines of the first channel CH1. The first channel CH1 may include branch points BP11, BP21, and BP22, and may be divided into a zeroth portion PR0, a first portion PR1, and a second portion PR2' based on the positions of the branch points BP11, BP21, and BP22.

[0061] As reference Figure 3A As described above, the lengths of the signal lines SL11 and SL12 in the first portion PR1 may be increased to reduce or suppress undesired interference between the first and second nonvolatile memory devices NVM1 and NVM2 and the third and fourth nonvolatile memory devices NVM3 and NVM4 that may be caused by reflected signals.

[0062] In the case where the operation speed of the memory device 200 is higher than the reference speed, the first nonvolatile memory device NVM1 and the second nonvolatile memory device NVM2 may affect each other through the reflection signal therebetween. Figure 4 As shown, the reflection signal from the second nonvolatile memory device NVM2 may be sent to the first nonvolatile memory device NVM1. Figure 5A As shown, when the input signal has a first frequency f1 (eg, corresponding to the operating speed of the memory device 200 ), the reflected signal from the second nonvolatile memory device NVM2 may have no effect on the input signal during the first time T1 (ie, the sensing margin).

[0063] For example, the signal lines SL22 and SL21 may be configured in such a manner that a reflected signal from the second nonvolatile memory device NVM2 is delayed by a relatively short delay time compared to the first frequency f1 (i.e., the operating speed of the memory device 200). That is, in a case where the delay time caused by the signal lines SL21 and SL22 is relatively short, when compared to the operating speed of the memory device 200, the reflected signal from the second nonvolatile memory device NVM2 may be transmitted to the first nonvolatile memory device NVM1 before the first time T1 of the input signal. In this case, the reflected signal is not transmitted to the first nonvolatile memory device NVM1 within the sensing margin of the input signal, and therefore, the first nonvolatile memory device NVM1 may accurately determine the input signal without any influence caused by the reflected signal.

[0064] In contrast, Figure 5B As shown, in the case where the input signal has a second frequency f2 higher than the first frequency f1 (i.e., the memory device 200 has an operating speed faster than the reference speed), the reflected signal may be transmitted to the first nonvolatile memory device NVM1 during the second time T2 (i.e., the sensing margin) and the rising edge of the input signal. This is because there is no difference in the delay time caused by the signal lines SL21 and SL22, and the total length of the input signal is shortened by the increase in the frequency of the input signal. That is, in the case where the operating speed of the memory device 200 is faster than the reference speed, signal distortion may be caused by the reflected signal between the first nonvolatile memory device NVM1 and the second nonvolatile memory device NVM2.

[0065] As described above, the length of the signal line in a specific portion (e.g., PR2) can be increased to prevent or suppress a reflected signal between physically adjacent or electrically adjacent nonvolatile memory devices in the nonvolatile memory device from affecting the physically adjacent or electrically adjacent nonvolatile memory device. Figure 4 The length of each of the signal lines SL21', SL22', SL23', and SL24' in the second portion PR2' may be longer than Figure 3A The length of each of the signal lines SL21, SL22, SL23 and SL24 in the second portion.

[0066] In other words, by increasing the length of each of the signal lines SL21, SL22, SL23, and SL24 of the second portion PR2, an interference phenomenon between the first nonvolatile memory device NVM1 and the second nonvolatile memory device NVM2 and between the third nonvolatile memory device NVM3 and the fourth nonvolatile memory device NVM4, which is caused by a reflection signal between the first nonvolatile memory device NVM1 and the second nonvolatile memory device NVM2 and between the third nonvolatile memory device NVM3 and the fourth nonvolatile memory device NVM4, can be reduced.

[0067] For example, Figure 5C As shown, in the case where the frequency of the input signal has a second frequency f2 higher than the first frequency f1, the length of each of the signal lines SL21', SL22', SL23', and SL24' in the second portion PR2' may be increased to reduce the reflected signal from the second nonvolatile memory device NVM2 to below a certain level and / or allow the reflected signal to be transmitted to the first nonvolatile memory device NVM1 after the input signal. In other words, the first nonvolatile memory device NVM1 may normally determine the input signal without any influence of the reflected signal from the second nonvolatile memory device NVM2.

[0068] In some example embodiments, the length of each of the signal lines SL21' and SL22' in the second portion PR2' may be determined to allow a reflected signal between the first nonvolatile memory device NVM1 and the second nonvolatile memory device NVM2 to have a signal level or delay time capable of blocking (or, alternatively, preventing) an undesired influence or interference between the first nonvolatile memory device NVM1 and the second nonvolatile memory device NVM2. Similarly, the length of each of the signal lines SL23' and SL24' in the second portion PR2' may be determined to allow a reflected signal between the third nonvolatile memory device NVM3 and the fourth nonvolatile memory device NVM4 to have a signal level or delay time capable of blocking (or, alternatively, preventing) an undesired influence or interference between the third nonvolatile memory device NVM3 and the fourth nonvolatile memory device NVM4.

[0069] As described above, in a storage device according to an example embodiment of the present invention, a signal line between a memory controller and a plurality of nonvolatile memory devices may be configured to have an increased length in a specific portion, and this may prevent or inhibit the nonvolatile memory device from being affected by a reflection signal between the nonvolatile memory devices. In some example embodiments, the length of the signal line in the specific portion may be determined in consideration of the operating speed of the storage device, the frequency of the input / output signal, and the like. In some example embodiments, the length of the signal line in the specific portion may be determined to reduce the amplitude of the reflection signal to below a specific level. In some example embodiments, the length of the signal line in the specific portion may be determined to allow a reflection signal from an unselected nonvolatile memory device to have a delay time that is capable of preventing (or, alternatively, preventing) the reflection signal from reaching the selected nonvolatile memory device during the activation period of the selected nonvolatile memory device.

[0070] In some example embodiments, the activation period of the selected nonvolatile memory device may represent a time period during which the selected nonvolatile memory device receives a signal from the memory controller or transmits a signal to the memory controller.

[0071] Figure 6 is a block diagram illustrating a signal flow in a memory device according to an example embodiment of the inventive concept. For the sake of brevity of description, previously described elements may be identified by reference numerals without repeating overlapping descriptions thereof.

[0072] Reference Figure 6, the memory device 300 may include a memory controller 310 and first to fourth nonvolatile memory devices NVM1 to NVM4. Similar to the previously described structure, the memory controller 310 may be connected to the first to fourth nonvolatile memory devices NVM1 to NVM4 through signal lines of the first channel CH1. The first channel CH1 may include branch points BP11, BP21, and BP22, and may be divided into a zeroth portion PR0', a first portion PR1, and a second portion PR2 based on the positions of the branch points BP11, BP21, and BP22.

[0073] In some example embodiments, the length of the signal line SL01' in the zeroth portion PR0' may be longer than the lengths of the signal lines SL11 and SL12 in the first portion PR1. Figure 6 The length of the signal line SL01' in the zeroth part PR0' can be greater than Figure 3A or Figure 4 Although the length of the signal line SL01' in the zeroth part PR0' is longer than the lengths of the signal lines SL11 and SL12 in the first part PR1, it is still different from the conventional memory device 10 (see, for example, Figure 2A ), the lengths of the signal lines SL11 and SL12 in the first portion PR1 may be increased, and this may make it possible to achieve the above-mentioned effect of reducing the influence of the reflected signal on the first to fourth nonvolatile memory devices NVM1 to NVM4 in the same or similar manner.

[0074] Figure 7 is a block diagram illustrating an example of a memory device according to an example embodiment of the inventive concept. For the sake of brevity of description, previously described elements may be identified by reference numerals without repeating overlapping descriptions thereof.

[0075] Reference Figure 7 , the memory device 400 may include a memory controller 410 and a plurality of nonvolatile memory devices 420. Similar to the previously described structure, the memory controller 410 may be configured to communicate with the nonvolatile memory devices 420 through a first channel CH1.

[0076] The first channel CH1 may include a plurality of branch points BP11, BP21, BP22, BP31, BP32, BP33, BP34, BP41-BP48 . . . BP(n-1)1-BP(n-1)2. n-2 ,BPn1-BPn2 n-1, and can be based on branch points BP11, BP21, BP22, BP31, BP32, BP33, BP34, BP41-BP48... BP(n-1)1-BP(n-1)2 n-2 ,BPn1-BPn2 n-1 The position of the signal line is divided into a plurality of parts PR0, PR1, ... and PRn. Similar to the previously described structure, the zeroth part PR0 may include one signal line, the first part PR1 may include two signal lines, and the nth part PRn may include two signal lines. n In some example embodiments, there may be one branch point between the zeroth portion PR0 and the first portion PR1, there may be two branch points between the first portion PR1 and the second portion PR2, and there may be two branch points between the n-1th portion PRn-1 and the nth portion PRn. n-1 branch points.

[0077] As an example, Figure 7 As shown, a single signal line branches out two signal lines at each branch point, but the inventive concept is not limited thereto. For example, a single signal line may branch out three or more signal lines at each branch point.

[0078] Similar to the previously described structure, the length of the signal line in a specific portion may be increased to reduce the undesired interference between the nonvolatile memory devices 420 that may be caused by the reflection signal. For example, the length of the signal line in the bottommost portion (i.e., the nth portion PRn) may be increased to reduce the influence of the reflection signal on each of the nonvolatile memory devices 420.

[0079] In a specific example embodiment, the nonvolatile memory device 420 may be classified into a plurality of groups. In this case, the signal line in the upper part of the common branch point to which all nonvolatile memory devices included in each group are connected may be set to have an increased length, which may make it possible to reduce the interference phenomenon between the groups caused by the reflection signal between the groups. For example, Figure 7 As shown, in order to reduce the interference phenomenon between the first group GR1 and the second group GR2 caused by the reflection signal between the first group GR1 and the second group GR2, the signal line in the upper part (i.e., the PRn-1 part) of the branch point BPn1 to which all the non-volatile memory devices of the first group GR1 are connected or the branch point BPn2 to which all the non-volatile memory devices of the second group GR2 are connected can be set to have an increased length.

[0080] In some example embodiments, Figure 7The first group GR1 and the second group GR2 shown in FIG. 1 are merely examples presented to describe example embodiments of the inventive concept, but the inventive concept is not limited to the examples. For example, the number of nonvolatile memory devices included in each group may be variously changed.

[0081] Although the above description represents a write operation of a storage device or an operation of sending a signal from a memory controller to one of the nonvolatile memory devices, the inventive concept is not limited thereto. For example, the storage device may be configured to perform a read operation of sending an input signal (e.g., read data) from one of the nonvolatile memory devices to the memory controller. Similarly, even in this case, the length of the signal line in a specific portion may be adjusted or increased to prevent or inhibit a reflected signal from an unselected nonvolatile memory device from being sent to the memory controller or the selected nonvolatile memory device during a read operation of a selected one of the nonvolatile memory devices.

[0082] Figure 8 is a diagram showing an example of a storage device according to an example embodiment of the present invention. For ease of explanation, Figure 8 However, the inventive concept is not limited thereto, and in certain example embodiments, the memory device 400 may further include other elements (eg, a buffer memory, at least one additional nonvolatile memory device, an auxiliary power supply, etc.).

[0083] Reference Figure 8 , the memory device may include a printed circuit board PCB, a memory controller, and first to fourth nonvolatile memory devices NVM1 to NVM4. The memory controller and the first to fourth nonvolatile memory devices NVM1 to NVM4 may be configured to have substantially the same features as those described above, and therefore, a detailed description thereof will be omitted.

[0084] The printed circuit board PCB may include a memory controller socket SCK_CT and a first socket SCK1 and a second socket SCK2. The memory controller socket SCK_CT may be an area, element or device configured to allow the memory controller 410 to be mounted thereon. Each of the first socket SCK1 and the second socket SCK2 may be an area, element or device configured to allow a corresponding one of the first nonvolatile memory device NVM1 and the second nonvolatile memory device NVM2 to be mounted thereon. Although not clearly shown in the drawings, the printed circuit board PCB may further include an additional socket disposed on its bottom surface. The third nonvolatile memory device NVM3 and the fourth nonvolatile memory device NVM4 may be mounted on the additional socket disposed on the bottom surface of the printed circuit board PCB.

[0085] In some example embodiments, the first socket SCK1 and the second socket SCK2 may be disposed on opposite side regions of the memory controller socket SCK_CT. For example, the memory controller socket SCK_CT may be placed on a middle region of the top surface of the printed circuit board PCB, and the first socket SCK1 and the second socket SCK2 may be spaced apart from each other with the memory controller socket SCK_CT inserted therebetween. In other words, when viewed on the top surface of the printed circuit board PCB, the memory controller socket SCK_CT may be located in a middle region of the printed circuit board PCB, and the first socket SCK1 and the second socket SCK2 may be located in a left region and a right region of the printed circuit board PCB, respectively.

[0086] In some example embodiments, the printed circuit board PCB may include signal lines that electrically connect the sockets (e.g., SCK_CT, SCK1, and SCK2, etc.) to each other. The signal lines may be included in a metal layer ML of the printed circuit board PCB. Although the metal layer ML is shown as a single-layer structure, the inventive concept is not limited thereto. The metal layer ML may be a multi-layer structure including a plurality of layers.

[0087] In reference Figures 1 to 7 In the aforementioned exemplary embodiments described, the signal line included in the printed circuit board PCB may be lengthened in a specific portion to reduce the influence of the reflected signal. Hereinafter, the signal line provided in the metal layer will be described in more detail with reference to the accompanying drawings.

[0088] 9A to 9C It is shown Figure 8 FIG. 1 is a diagram of an example of a printed circuit board. Fig.9A FIG. 1 is a top view showing the first printed circuit board PCB_1 . Fig. 9B is along Fig.9A A cross-sectional view of the first printed circuit board PCB_1 taken along line AA′. Fig. 9C It is along Fig.9A For ease of explanation, reference will be made to the cross-sectional view of the first printed circuit board PCB_1 taken along the line BB'. 9A to 9C Some example embodiments of the present inventive concept are described with reference to a single signal line SL shown in FIG. However, the present inventive concept is not limited thereto, and in certain example embodiments, the printed circuit board may further include a plurality of additional signal lines.

[0089] Reference 9A to 9C , the first printed circuit board PCB_1 may include a memory controller socket SCK_CT and first to fourth sockets SCK1 to SCK4. Fig. 9B As shown, the memory controller socket SCK_CT and the first socket SCK1 and the second socket SCK2 may be disposed on the top surface PCB_TOP of the first printed circuit board PCB_1, and the third socket SCK3 and the fourth socket SCK4 may be disposed on the bottom surface PCB_BOTTOM of the first printed circuit board PCB_1. In some example embodiments, the third socket SCK3 may be disposed to face the first socket SCK1 with the first printed circuit board PCB_1 inserted between the third socket SCK3 and the first socket SCK1, and the fourth socket SCK4 may be disposed to face the second socket SCK2 with the first printed circuit board PCB_1 inserted between the fourth socket SCK4 and the second socket SCK2.

[0090] The memory controller socket SCK_CT can be mounted on the reference Figures 1 to 7 Each of the first socket SCK1 and the second socket SCK2 may be an area on which a nonvolatile memory device is mounted. In other words, each of the memory controller and the nonvolatile memory device may be mounted on a corresponding one of the sockets and may communicate with each other through a signal line SL of the printed circuit board PCB.

[0091] The printed circuit board PCB may include a signal line SL. The signal line SL may be configured to be used as a signal transmission path between the memory controller and the non-volatile memory device. In other words, the signal line SL may be configured to electrically connect the first socket SCK1 and the second socket SCK2 to the memory controller socket SCK_CT. For example, the signal line SL may be formed in a metal layer or a wiring layer of the first printed circuit board PCB_1.

[0092] For example, similar to the previously described structure, the signal line SL may branch out at least two line segments at branch points BP11, BP21, and BP22 in a direction away from the memory controller socket SCK_CT, and in this case, the segmented signal line of the signal line SL may be used to electrically connect the first socket SCK1 and the second socket SCK2 and the memory controller socket SCK_CT to each other. For example, a signal line from the memory controller socket SCK_CT to the branch point BP11 may be included in the zeroth portion PR0. A signal line from the branch point BP11 to the branch points BP21 and BP22 may be included in the first portion PR1. A signal line from each of the branch points BP21 and BP22 to a corresponding one of the first socket SCK1 to the fourth socket SCK4 may be included in the second portion PR2.

[0093] In some example embodiments, branch points BP11, BP21, and BP22 may be located in an area associated with the memory controller socket SCK_CT and the first to fourth sockets SCK1 to SCK4. For example, branch point BP11 may be located in an area physically adjacent to the memory controller socket SCK_CT. Branch point BP21 may be located between the first socket SCK1 and the third socket SCK3, and may be connected to the first socket SCK1 and the third socket SCK3 through a through-hole contact. Branch point BP22 may be located between the second socket SCK2 and the fourth socket SCK4, and may be connected to the second socket SCK2 and the fourth socket SCK4 through a through-hole contact.

[0094] In a specific example embodiment, the branch point BP11 may be spaced a first distance from the memory controller socket SCK_CT in the horizontal direction. Each of the branch points BP21 and BP22 may be spaced a second distance from the branch point BP11 in the horizontal direction. Here, the second distance may be longer than the first distance. The horizontal direction may be a direction parallel to the top surface or the bottom surface of the printed circuit board PCB. In a specific example embodiment, the horizontal direction may be parallel to one of the sides of the printed circuit board PCB or may be a diagonal direction that is at an angle to the side of the printed circuit board PCB but parallel to the top surface of the printed circuit board PCB.

[0095] The branch points BP21 and BP22 may be spaced a certain distance from the sockets SCK1-SCK4 in the vertical direction. Here, the vertical direction may be a direction perpendicular to or orthogonal to the top or bottom surface of the printed circuit board PCB. For example, the vertical direction may be an extending direction of the through-hole contact.

[0096] The second distance may be determined to prevent or inhibit nonvolatile memory devices mounted on the first and third sockets SCK1 and SCK3 and other nonvolatile memory devices mounted on the second and fourth sockets SCK2 and SCK4 from being mutually affected by reflected signals therebetween.

[0097] Similar to the previously described structure, the length of the signal line in the second portion PR2 can be increased to reduce the interference phenomenon between the non-volatile memory devices caused by the reflected signal between the non-volatile memory devices. Fig.9A As shown, the branch point BP11 may be formed at a position adjacent to the memory controller socket SCK_CT, and branch points BP21 and BP22 may be formed at positions adjacent to the first to fourth sockets SCK1 to SCK4, respectively.

[0098] As a more detailed example, the memory controller socket SCK_CT and the branch point BP11 may be spaced apart from each other by a first length, each of the branch points BP21 and BP22 may be spaced apart from a corresponding one of the first to fourth sockets SCK1 to SCK4 by a second length, and the branch point BP11 may be spaced apart from each of the branch points BP21 and BP22 by a third length. Here, the third length may be longer than the first length or the second length.

[0099] In the case where the branch point is formed in the first printed circuit board PCB_1 as described above, the reference Figures 1 to 6 The storage device 100 has the technical effects described.

[0100] FIG. 10A to FIG. 10C It is shown Figure 8 FIG. 1 is a diagram of an example of a printed circuit board. Fig. 10A is a plan view showing a top surface of the second printed circuit board PCB_2. Fig. 10B It is along Fig. 10A A cross-sectional view of the second printed circuit board PCB_2 taken along line CC'. Fig. 10C is along Fig. 10A 2 is a cross-sectional view of the second printed circuit board PCB_2 taken along line DD'. For the sake of brevity of description, previously described elements may be identified by reference numerals without repeating their repeated description.

[0101] Reference FIG. 10A to FIG. 10C As shown, the second printed circuit board PCB_2 may include a memory controller socket SCK_CT and first to fourth sockets SCK1 to SCK4. 9A to 9C The first printed circuit board PCB_1 is different from FIG. 10A to FIG. 10C The branch point BP11 in the second printed circuit board PCB_2 in the embodiment may be arranged below the memory controller socket SCK_CT. Fig. 10C As shown, the memory controller socket SCK_CT and the branch point BP11 may be directly connected to each other through a through-hole contact. Other elements may be configured to have substantially the same features as those in the previously described embodiment, and thus, a detailed description thereof will be omitted.

[0102] Fig.11A and Fig. 11B It is shown Figure 8 FIG. 1 is a diagram of an example of a printed circuit board. Fig.11A is a plan view showing a top surface of the third printed circuit board PCB_3. Fig. 11B is along Fig.11A A cross-sectional view of the third printed circuit board PCB_3 taken along the line EE'. Fig.11A The cross-sectional view of the third printed circuit board PCB_3 taken along the line F-F' is substantially similar to Fig. 10C Therefore, it is omitted.

[0103] Reference Fig.11A and Fig. 11B , the third printed circuit board PCB_3 may include a memory controller socket SCK_CT and first to fourth sockets SCK1 to SCK4. 9A to 9C The first printed circuit board PCB_1 or FIG. 10A to FIG. 10C The second printed circuit board PCB_2 is different in Fig.11A The branch points BP21 and BP22 in the third printed circuit board PCB_3 of FIG. 11B may be formed in a region spaced apart from the first to fourth sockets SCK1 to SCK4 when viewed in a front view.

[0104] For example, Fig. 10A and Fig. 10B As shown, a branch point BP21 may be formed in a region between the memory controller socket SCK_CT and the first socket SCK1. A branch point BP22 may be formed in a region between the memory controller socket SCK_CT and the second socket SCK2.

[0105] like Fig.11A and Fig. 11B As shown, since the branch points BP21 and BP22 are respectively formed in the region between the memory controller socket SCK_CT and the first socket SCK1 and the second socket SCK2, the length of the second portion PR2 can be increased. Fig. 10A and Fig. 10B The manner shown in the figure can be realized by referring to Figure 4 Described embodiments.

[0106] In other words, in Fig. 10A and Fig. 10B With the branch points BP21 and BP22 formed as shown, interference caused by reflected signals between nonvolatile memory devices to be mounted on the first and third sockets SCK1 and SCK3 and between other nonvolatile memory devices to be mounted on the second and fourth sockets SCK2 and SCK4 can be reduced.

[0107] Already referred to 9A to 9C , 10A to Fig. 10C , 11A and Fig. 11B Some examples of printed circuit boards (eg, PCB_1, PCB_2, and PCB_3) are described, but the inventive concept is not limited to these examples. 9A to 9C , 10A to Fig. 10C , 11A and Fig. 11B In the figure, printed circuit boards PCB_1, PCB_2 and PCB_3 are schematically shown to provide a better understanding of the inventive concept and reduce the complexity in the drawings. In other words, without departing from the spirit of the inventive concept, the signal lines can be implemented in various other layers of the printed circuit board in a similar manner. In addition, the memory controller socket SCK_CT and each of the sockets SCK1-SCK4 can be connected to each other through other signal lines.

[0108] in addition, 9A to 9C , 10A to Fig. 10C , 11A and Fig. 11B An example of a printed circuit board providing one controller socket and four sockets is shown, but the inventive concept is not limited thereto. The storage device may be configured to include a plurality of nonvolatile memory devices, and the printed circuit board of the storage device may further include a plurality of sockets, each of the plurality of sockets being used to mount a corresponding one of the nonvolatile memory devices.

[0109] Fig. 12A and Fig. 12B is a diagram illustrating an example of a printed circuit board according to an example embodiment of the inventive concept. Fig. 12A is a plan view illustrating a top surface of a fourth printed circuit board PCB_4 according to an example embodiment of the inventive concept. Fig. 12B is along Fig. 12A A cross-sectional view of the fourth printed circuit board PCB_4 taken along line G-G'.

[0110] A single signal line SL electrically connected to some of the plurality of sockets SCK11-SCK4n is exemplarily shown to reduce the complexity in the drawings and provide a better understanding of the exemplary embodiments of the inventive concept. However, the inventive concept is not limited thereto, and in certain embodiments, other sockets may also be electrically connected to other signal lines. Fig. 12A and Fig. 12B Description can be used to implement e.g. Figure 6 A printed circuit board of the storage device 300.

[0111] Reference Fig. 12A and Fig. 12B , the fourth printed circuit board PCB_4 may include a memory controller socket SCK_CT and a plurality of sockets SCK11-SCK4n. Figure 8 , 9A to 9C , FIG. 10A to FIG. 10C , Fig.11A and Fig. 11B The printed circuit boards described are different, Fig. 12A and Fig. 12B The memory controller socket SCK_CT can be placed in the side area of ​​the fourth printed circuit board PCB_4. 9A to 9C , FIG. 10A to FIG. 10C , Fig.11A and Fig. 11B In the described embodiment, the memory controller socket SCK_CT may be located in the middle area of ​​the printed circuit board, and the sockets SCK1 and SCK2 may be located in two opposite side areas of the memory controller socket SCK_CT. Fig. 12A and Fig. 12B As shown, the memory controller socket SCK_CT may be placed in a side area of ​​the fourth printed circuit board PCB_4, and a plurality of sockets SCK11-SCK4n may be placed in the remaining area.

[0112] The memory controller socket SCK_CT may be electrically connected to the first branch point BP11. The first branch point BP11 may be spaced apart from the memory controller socket SCK_CT by a predetermined distance. The first branch point BP11 may be electrically connected to each of the second branch point BP21 and the third branch point BP22.

[0113] The second branch point BP21 may be electrically connected to each of the sockets SCK11 and SCK51, and the third branch point BP22 may be electrically connected to each of the sockets SCK21 and SCK61. Here, as shown in FIG. 12B, the length of the zeroth portion PR0 may be longer than the length of the first portion PR1. However, as shown in FIG. Figure 6As described above, even when the length of the zeroth portion PR0 is longer than that of the first portion PR1, if the length of the first portion PR1 is longer than a specific length, interference between nonvolatile memory devices caused by a reflection signal between nonvolatile memory devices can be reduced.

[0114] For example, the sockets SCK11, SCK21, SCK51, and SCK61 may be electrically connected to the memory controller socket SCK_CT through a common channel (i.e., a single interconnect structure). Here, the sockets SCK11 and SCK51 may be arranged to face each other with a fourth printed circuit board PCB_4 inserted between the sockets SCK11 and SCK51, and the sockets SCK21 and SCK61 may be arranged to face each other with a fourth printed circuit board PCB_4 inserted between the sockets SCK21 and SCK61. In other words, the sockets SCK11 and SCK21 may be arranged on the top surface PCB_TOP of the printed circuit board, and the sockets SCK51 and SCK61 may be arranged on the bottom surface PCB_BOTTOM of the printed circuit board.

[0115] Here, the sockets SCK11 and SCK21 disposed on the top surface PCB_TOP may not be adjacent to each other. For example, at least one other socket (e.g., SCK12-SCK1n) may be located between the sockets SCK11 and SCK21 connected to a common channel (i.e., a single interconnect structure), and such other sockets (e.g., SCK12-SCK1n) may be electrically connected to the memory controller socket SCK_CT through an additional signal line. The sockets SCK51 and SCK61 disposed on the bottom surface PCB_BOTTOM may not be adjacent to each other. For example, at least one other socket (e.g., SCK52-SCK5n) may be located between the sockets SCK51 and SCK61 connected to a single interconnect structure, and such other sockets (e.g., SCK52-SCK5n) may be electrically connected to the memory controller socket SCK_CT through an additional signal line.

[0116] In some example embodiments, in a conventional memory device, adjacent sockets may be electrically connected to a memory controller socket through a single interconnect structure. In this case, a branch point may be formed near the adjacent sockets, and therefore, the signal line in the first portion may have a relatively short length. In contrast, according to an example embodiment of the present invention, non-adjacent sockets (e.g., SCK11 and SCK21) may be connected to the memory controller socket SCK_CT through a single interconnect structure, and therefore, the signal line in the first portion PR1 may be set to have a relatively long length. Therefore, interference phenomena between non-volatile memory devices mounted on the sockets that may be caused by reflected signals between the non-volatile memory devices may be reduced.

[0117] Fig. 12A and Fig. 12B The fourth printed circuit board PCB_4 shown in FIG. 1 is only an example of a printed circuit board according to some example embodiments of the inventive concept, but the inventive concept is not limited thereto. If within the allowable range under the spirit of the inventive concept, various changes may be made to the position of each of the branch points BP11, BP21, and BP22 in the fourth printed circuit board PCB_4.

[0118] For example, the first branch point BP11 may be located in the area for the socket SCK11, the area for the socket SCK21, or any other area, but the signal line in the first portion PR1 may be arranged in such a way that the first portion PR1 has a specific length. Here, the specific length may be determined to allow the reflected signal to have an amplitude below a specific level.

[0119] Fig.13A and Fig. 13B is a timing diagram illustrating the attenuation effect of a reflected signal according to an example embodiment of the inventive concept. Fig.13A Waveforms of input signals at a memory controller during a read operation (ie, sending a signal from a nonvolatile memory device to the memory controller) are shown. Fig. 13B 1 shows the waveform of an input signal at a nonvolatile memory device during a write operation (ie, sending a signal from a memory controller to the nonvolatile memory device). Fig.13A and Fig. 13B In the timing diagram, the horizontal axis represents time and the vertical axis represents the amplitude of the signal.

[0120] Reference Fig.13A , the first curve G1 shows the waveform of the read signal in the memory device of the conventional structure, and the second curve G2 shows the waveform of the read signal in the memory device of the structure proposed according to the inventive concept. For example, the read signal may be a signal sent through a signal line during a read operation of the memory device. In other words, the waveform of the read signal may be a waveform of a signal to be received by a memory controller.

[0121] like Fig.13A As shown, due to the interference phenomenon caused by the reflection signal, the margin of the read signal in the conventional structure memory device may be a first time T1, while the margin of the read signal in the memory device of the structure proposed according to the inventive concept may be a second time T2 longer than the first time T1. That is, by increasing the length of the channel or signal line in a specific portion, the undesirable interference phenomenon caused by the reflection signal from other non-volatile memory devices can be reduced, thereby increasing the margin of the read signal.

[0122] Reference Fig. 13B, the third graph G3 shows the waveform of the write signal in the storage device of the conventional structure, and the fourth graph G4 shows the waveform of the write signal in the storage device of the structure proposed according to the inventive concept. For example, the write signal may be a signal sent through a signal line during a write operation of the storage device. In other words, the waveform of the write signal may be the waveform of a signal received by the nonvolatile memory device.

[0123] like Fig. 13B As shown, due to the interference phenomenon caused by the reflection signal, the margin of the write signal in the memory device of the conventional structure may be the third time T3. As an example, in the case where the write signal has a waveform with a shape similar to that of the third graph G3, the input signal may be distorted due to the reflection signal, and therefore, the change in its amplitude may not be large enough. In this case, it is difficult to normally determine the signal input to the nonvolatile memory device.

[0124] In contrast, the margin of the write signal in the memory device of the structure proposed according to the inventive concept can be the fourth time T4 which is longer than the third time T3. In addition, since the interference phenomenon caused by the reflected signal is reduced, the change in the signal amplitude can be sufficiently large. That is, the signal to be input to the nonvolatile memory device can be reliably sensed.

[0125] In other words, according to example embodiments of the inventive concept, the length of a channel or signal line in a specific portion may be adjusted or increased to reduce interference phenomena caused by reflection signals from other nonvolatile memory devices, and this may improve the reliability of the memory device.

[0126] Fig.14A and Fig. 14B is a timing diagram illustrating the attenuation effect of a reflected signal according to an exemplary embodiment of the inventive concept. In detail, Fig.14A is a timing diagram showing how the waveform of a signal entering the first nonvolatile memory device NVM1 varies with the lengths of the zeroth portion PR0 and the first portion PR1 when the input signal is a step pulse (ie, a pulse signal having an increasing amplitude from a low state to a high state). Fig. 14B is a timing diagram showing how the waveform of the signal entering the first nonvolatile memory device NVM1 changes with the length of the zeroth part PR0 and the first part PR0 when the input signal is a random pulse. Fig.14A and Fig. 14B The lengths of the zeroth part PR0 and the first part PR1 of each curve in are summarized in Table 1.

[0127] Table 1

[0128] Line Type Length of part zero Length of the first part Solid Line 10mm 90mm dotted line 20mm 80mm Single dot dash line 80mm 20mm Double dotted line 90mm 10mm

[0129] exist Fig.14A and Fig. 14B In Table 1, the solid line and the dashed line represent the signals measured from the storage device of the structure proposed according to the present invention, and the single-dot chain line and the double-dot chain line represent the signals measured from the storage device of the conventional structure. In Table 1, some numerical values ​​are shown as examples, but the present invention is not limited thereto. Fig.14A As shown, compared with the conventional structure, the highest signal amplitude in the storage device of the structure proposed according to the present invention is low and converges to the reference value quickly. This means that the proposed structure suppresses the signal distortion problem caused by the reflected signal. For example, Fig.14A As shown, for the conventional structure, the highest signal amplitude is the first level L1 in the double-dotted line, and for the structure proposed according to the inventive concept, the highest signal amplitude is the second level L2 in the solid line that is lower than the first level L1. That is, the difference between the solid line and the reference level REF for the structure proposed according to the inventive concept is smaller than the difference between the double-dotted line and the reference level REF for the conventional structure. This means that, compared with the conventional structure, in the storage device of the structure proposed according to the inventive concept, the undesirable effects caused by the reflected signal can be more effectively reduced.

[0130] Reference Fig. 14B , similar to Fig.14A As shown in FIG. 1 , the solid line or the dotted line for the storage device according to the structure proposed by the present invention has reduced signal distortion compared with the single-dot chain line or the double-dot chain line of the conventional structure. As described above, in the storage device according to the structure proposed by the present invention, the length of the signal line in a specific portion is increased to attenuate or delay the reflection signal between the non-volatile memory devices. Therefore, the signal distortion caused by the reflection signal can be suppressed, thereby improving the reliability of the storage device.

[0131] Fig.15 is a block diagram illustrating a solid state drive (SSD) system using a storage device according to an example embodiment of the inventive concept.

[0132] Reference Fig.15 , the SSD system 1000 may include a host 1100 and an SSD 1200 .

[0133] The SSD 1200 may exchange a signal SIG with the host 1100 through a signal connector and may be supplied with power PWR through a power connector The SSD 1200 may include an SSD memory controller 1210 , a plurality of FLASH memories 1221 - 122 n , an auxiliary power supply 1230 , and a buffer memory 1240 .

[0134] The SSD memory controller 1210 may control the plurality of FLASH memories 1221-122n in response to a signal SIG provided from the host 1100. The plurality of FLASH memories 1221-122n may operate under the control of the SSD memory controller 1210. The auxiliary power supply 1230 may be connected to the host 1100 through a power connector. For example, each of the FLASH memories 1221-122n may include a power supply 1230 as shown in FIG. 1 to FIG. Fig.15 The auxiliary power supply 1230 may be charged by the power PWR from the host 1100. In the event that there is difficulty associated with the supply of the power PWR from the host 1100, the auxiliary power supply 1230 may be used to supply power to the SSD 1200.

[0135] In some example embodiments, SSD 1200 may be configured with reference Figures 1 to 14B The topology described above. For example, various elements constituting the SSD 1200 may be mounted on a printed circuit board and may be electrically connected to each other through various signal lines provided in the printed circuit board. Here, as described above, at least one of the signal lines between the SSD memory controller 1210 and the plurality of nonvolatile memory devices 1221-122n may be configured to have an increased length in a specific portion, and this may make it possible to suppress an undesirable interference phenomenon between the nonvolatile memory devices that may be caused by a reflection signal between the nonvolatile memory devices.

[0136] According to some example embodiments of the present invention, a signal line is provided between a memory controller and a non-volatile memory device. The length of the signal line in a specific portion may be increased to suppress interference between non-volatile memory devices caused by reflected signals between the non-volatile memory devices. Thus, it may be possible to prevent (or, optionally, prevent) signal reliability from being degraded by reflected signals. This may make it possible to improve the reliability of a printed circuit board or a memory device including the printed circuit board.

[0137] The above-mentioned units and / or devices (such as components of a storage device (e.g., 100) including a memory controller (e.g., 110) and a non-volatile memory device 120 and their subcomponents) may be implemented using hardware, a combination of hardware and software, or a non-transitory storage medium storing software (executable to perform its functions).

[0138] The hardware may be implemented using various hardware devices, such as an integrated circuit (IC), an application specific IC (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a system on a chip (SoC), or a processing circuit (such as, one or more central processing units (CPU), one or more controllers, one or more arithmetic logic units (ALU), one or more digital signal processors (DSP), one or more microcomputers), or any other device capable of responding and executing instructions in a defined manner.

[0139] Software may include computer programs, program codes, instructions, or some combination thereof, for independently or collectively instructing or configuring hardware devices to operate as desired. Computer programs and / or program codes may include programs or computer-readable instructions, software components, software modules, data files, data structures, etc. that can be implemented by one or more hardware devices (such as one or more of the hardware devices mentioned above). Examples of program code include machine code produced by a compiler and higher-level program code executed using an interpreter.

[0140] For example, when the hardware device is a computer processing device (e.g., one or more processors, CPUs, controllers, ALUs, DSPs, microcomputers, microprocessors, etc.), the computer processing device can be configured to execute the program code by performing arithmetic, logic, and input / output operations according to the program code. Once the program code is loaded into the computer processing device, the computer processing device can be programmed to execute the program code, thereby converting the computer processing device into a special-purpose computer processing device. In a more specific example, when the program code is loaded into the processor, the processor becomes programmed to execute the program code and the corresponding operations therewith, thereby converting the processor into a special-purpose processor. In another example, the hardware device can be an integrated circuit customized as a special-purpose processing circuit (e.g., ASIC).

[0141] A hardware device such as a computer processing device can run an operating system (OS) and one or more software applications running on the OS. The computer processing device can also access, store, manipulate, process, and create data in response to the execution of the software. For simplicity, one or more example embodiments may be illustrated as a computer processing device, however, those skilled in the art will appreciate that the hardware device may include multiple processing elements and multiple types of processing elements. For example, the hardware device may include multiple processors or a processor and a controller. In addition, other processing configurations are also possible, such as parallel processors.

[0142] The software and / or data may be permanently or temporarily contained in any type of storage medium, including but not limited to any machine, component, physical or virtual equipment, or computer storage medium or device capable of providing instructions or data to a hardware device or being interpreted by a hardware device. The software may also be distributed on a network-coupled computer system so that the software is stored and executed in a distributed manner. In particular, for example, the software and data may be stored by one or more computer-readable recording media (including tangible or non-transitory computer-readable storage media as discussed herein).

[0143] According to one or more example embodiments, the storage medium may also include one or more storage devices at the unit and / or device. One or more storage devices may be tangible or non-transitory computer-readable storage media, such as random access memory (RAM), read-only memory (ROM), permanent mass storage device (such as, disk drive) and / or any other similar data storage mechanism capable of storing and recording data. One or more storage devices may be configured to store computer programs, program codes, instructions or some combination thereof for one or more operating systems and / or for implementing the example embodiments described herein.

[0144] Computer program, program code, instruction or some combination thereof can also be loaded into one or more storage devices and / or one or more computer processing devices from a separate computer readable storage medium using a drive mechanism. Such a separate computer readable storage medium may include a universal serial bus (USB) flash drive, a memory stick, a Blu-ray / DVD / CD-ROM drive, a memory card and / or other similar computer readable storage media. Computer program, program code, instruction or some combination thereof can be loaded into one or more storage devices and / or one or more computer processing devices from a remote data storage device via a network interface rather than via a computer readable storage medium. In addition, a computer program, program code, instruction or some combination thereof can be loaded into one or more storage devices and / or one or more processors from a remote computing system configured to transmit and / or distribute computer program, program code, instruction or some combination thereof on a network. A remote computing system can transmit and / or distribute computer program, program code, instruction or some combination thereof via a wired interface, an air interface and / or any other similar medium.

[0145] One or more hardware devices, storage media, computer programs, program codes, instructions, or some combination thereof may be specially designed and constructed for the purposes of the example embodiments, or they may be known devices that have been altered and / or modified for the purposes of the example embodiments.

[0146] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A printed circuit board having a top surface and a bottom surface, the printed circuit board comprising: controller socket, on the top surface; a first socket and a second socket on the top surface; a third socket and a fourth socket, on the bottom surface, facing the first socket and the second socket, respectively; as well as A plurality of signal lines, including at least a first signal line to a seventh signal line, connect the controller socket to the first socket, the second socket, the third socket, and the fourth socket, the plurality of signal lines being connected at a plurality of branch points, the plurality of branch points comprising: a first branch point electrically connected to the controller socket via a first signal line, such that the first branch point is spaced a first distance from the controller socket in a horizontal direction parallel to the top surface, a second branch point electrically connected to the first branch point via the second signal line, electrically connected to the first socket via the fourth signal line, and electrically connected to the third socket via the fifth signal line, such that the second branch point is spaced apart from the first branch point by a second distance, the second distance being longer than the first distance in the horizontal direction, and a third branch point, electrically connected to the first branch point via a third signal line, electrically connected to the second socket via a sixth signal line, and electrically connected to the fourth socket via a seventh signal line, such that the third branch point is spaced a third distance from the first branch point, the third distance being longer than the first distance in the horizontal direction, Here, the length of each of the second signal line and the third signal line is longer than the length of each of the fourth signal line, the fifth signal line, the sixth signal line, and the seventh signal line.

2. The printed circuit board according to claim 1, wherein: The length of each of the second signal line and the third signal line is longer than that of the first signal line.

3. The printed circuit board according to claim 1, wherein: The first socket is at an area spaced apart from the controller socket in a first lateral direction, and The second socket is at a region spaced apart from the controller socket in a second lateral direction opposite to the first lateral direction.

4. The printed circuit board according to claim 1, wherein: The second branch point is at a region between the first socket and the third socket, and The third branch point is at a region between the second socket and the fourth socket.

5. The printed circuit board according to claim 1, further comprising: The metal layer includes the plurality of signal lines and a first branch point, a second branch point, and a third branch point connected to the plurality of signal lines.

6. A storage device, comprising: a plurality of nonvolatile memory devices, including a first nonvolatile memory device, a second nonvolatile memory device, a third nonvolatile memory device, and a fourth nonvolatile memory device; a memory controller configured to control the plurality of nonvolatile memory devices; as well as A plurality of signal lines, the plurality of signal lines comprising: a first signal line configured to electrically connect the memory controller to the first branch point, a second signal line configured to electrically connect the first branch point to the second branch point, the second signal line being longer than the first signal line, a third signal line configured to electrically connect the first branch point to a third branch point, the third signal line being longer than the first signal line, a fourth signal line configured to electrically connect the second branch point to the first nonvolatile memory device, a fifth signal line configured to electrically connect the second branch point to the second nonvolatile memory device, a sixth signal line configured to electrically connect the third branch point to the third nonvolatile memory device, and a seventh signal line configured to electrically connect the third branch point to the fourth nonvolatile memory device, Here, the length of each of the second signal line and the third signal line is longer than the length of each of the fourth signal line, the fifth signal line, the sixth signal line, and the seventh signal line.

7. The storage device according to claim 6, wherein: The memory controller is configured to provide input signals to the plurality of nonvolatile memory devices through the plurality of signal lines.

8. The storage device according to claim 6, wherein: The second signal line and the third signal line are configured to attenuate a reflection signal generated from the third nonvolatile memory device or the fourth nonvolatile memory device when the first nonvolatile memory device is activated to be below a set level.

9. The storage device according to claim 6, wherein: The fourth signal line and the fifth signal line are configured to attenuate a reflection signal generated from the second nonvolatile memory device when the first nonvolatile memory device is activated to be below a set level.

10. The storage device according to claim 6, wherein: In response to a chip select signal from a memory controller, each of the plurality of nonvolatile memory devices is activated.

11. The storage device according to claim 6, wherein: Each of the plurality of nonvolatile memory devices is a multi-chip package.

12. The storage device according to claim 6, wherein: The second signal line and the third signal line are configured to delay a reflection signal by a delay time set based on an operation speed of the memory device, wherein the reflection signal is generated by one or more of the plurality of nonvolatile memory devices.

13. A storage device, comprising: Memory controller; a plurality of nonvolatile memory devices, including a first nonvolatile memory device, a second nonvolatile memory device, a third nonvolatile memory device, and a fourth nonvolatile memory device; as well as A printed circuit board comprising a top surface and a bottom surface, a first nonvolatile memory device and a second nonvolatile memory device being mounted on the top surface, and a third nonvolatile memory device and a fourth nonvolatile memory device being mounted on the bottom surface so that the third nonvolatile memory device faces the first nonvolatile memory device and the fourth nonvolatile memory device faces the second nonvolatile memory device, the printed circuit board comprising a plurality of signal lines, the plurality of signal lines comprising at least a first signal line to a seventh signal line connecting a memory controller to the plurality of nonvolatile memory devices, the plurality of signal lines being connected at a plurality of branch points, the plurality of branch points comprising: a first branch point electrically connected to the memory controller via a first signal line such that the first branch point is spaced a first distance from the memory controller in a horizontal direction parallel to the top surface, a second branch point electrically connected to the first branch point via the second signal line, electrically connected to the first nonvolatile memory device via the fourth signal line, and electrically connected to the third nonvolatile memory device via the fifth signal line, such that the second branch point is spaced apart from the first branch point by a second distance in the horizontal direction, the second distance being longer than the first distance, and a third branch point electrically connected to the first branch point via a third signal line, electrically connected to the second nonvolatile memory device via a sixth signal line, and electrically connected to the fourth nonvolatile memory device via a seventh signal line, such that the third branch point is spaced a third distance from the first branch point in the horizontal direction, the third distance being longer than the first distance, Here, the length of each of the second signal line and the third signal line is longer than the length of each of the fourth signal line, the fifth signal line, the sixth signal line, and the seventh signal line.

14. The storage device according to claim 13, wherein: The second branch point is at a region between the first nonvolatile memory device and the third nonvolatile memory device, and The third branch point is at a region between the second nonvolatile memory device and the fourth nonvolatile memory device.

15. The storage device according to claim 13, wherein: The first branch point is below a region where the memory controller is mounted such that the first branch point is electrically connected to the memory controller through a through-hole contact extending in a vertical direction, the vertical direction being perpendicular to the top surface.

16. The storage device according to claim 13, wherein: A first nonvolatile memory device is mounted on a first region of the top surface, the first region being spaced apart from the memory controller in a first lateral direction, and A second nonvolatile memory device is mounted on a second region of the top surface, the second region being spaced apart from the memory controller in a second lateral direction opposite the first lateral direction.

17. The storage device according to claim 13, wherein: The first signal line and the second signal line are configured to delay a reflection signal by a delay time set based on an operation speed of the memory device, wherein the reflection signal is generated from one or more of the plurality of nonvolatile memory devices.

18. A printed circuit board having a top surface and a bottom surface, the printed circuit board comprising: a controller socket disposed on the top surface; a plurality of sockets on the top surface, the plurality of sockets comprising: The first socket, on the top surface, A second socket, on the top surface, is spaced apart from the first socket by a distance, a third socket, on the top surface, between the first socket and the second socket, a fourth socket, on the bottom surface, facing the first socket, a fifth socket, on the bottom surface, facing the second socket, and a sixth socket, on the bottom surface, facing the third socket; and A plurality of signal lines connect the controller socket to the plurality of sockets, the plurality of signal lines are connected at a plurality of branch points, the plurality of branch points comprising: The first branch point is electrically connected to the controller socket via a first signal line, a second branch point electrically connected to the first branch point via the second signal line, electrically connected to the first socket via the fourth signal line, and electrically connected to the second socket via the fifth signal line, and a third branch point electrically connected to the first branch point via a third signal line, electrically connected to the fourth socket via a sixth signal line, and electrically connected to the fifth socket via a seventh signal line, Here, the length of each of the second signal line and the third signal line is longer than the length of each of the fourth signal line, the fifth signal line, the sixth signal line, and the seventh signal line.

19. A storage device, comprising: Memory controller; a plurality of nonvolatile memory devices, including a first nonvolatile memory device, a second nonvolatile memory device, a third nonvolatile memory device, a fourth nonvolatile memory device, a fifth nonvolatile memory device, and a sixth nonvolatile memory device; as well as A printed circuit board comprising a top surface and a bottom surface, a first nonvolatile memory device, a second nonvolatile memory device, and a third nonvolatile memory device being mounted on the top surface, the third nonvolatile memory device being mounted between the first nonvolatile memory device and the second nonvolatile memory device, and a fourth nonvolatile memory device, a fifth nonvolatile memory device, and a sixth nonvolatile memory device being mounted on the bottom surface so that the fourth nonvolatile memory device, the fifth nonvolatile memory device, and the sixth nonvolatile memory device face the first nonvolatile memory device, the second nonvolatile memory device, and the third nonvolatile memory device, respectively, the printed circuit board comprising: a first branch point electrically connected to the memory controller via a first signal line, a second branch point electrically connected to the first branch point via the second signal line, electrically connected to the first nonvolatile memory device via the fourth signal line, and electrically connected to the second nonvolatile memory device via the fifth signal line, and a third branch point electrically connected to the first branch point via a third signal line, electrically connected to the fourth nonvolatile memory device via a sixth signal line, and electrically connected to the fifth nonvolatile memory device via a seventh signal line, Here, the length of each of the second signal line and the third signal line is longer than the length of each of the fourth signal line, the fifth signal line, the sixth signal line, and the seventh signal line.

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