Semiconductor device and power conversion device

Abstract

Provided is a molded semiconductor device with improved heat dissipation. The semiconductor device comprises: a circuit component (2) having a front surface and a back surface and having a planar portion; a terminal portion (2a) formed above the surface of the planar portion of the circuit component (2) and parallel to the planar portion; a semiconductor element (4) having an upper surface located below the upper surface of the terminal portion (2a) and formed on the surface of the planar portion of the circuit component (2); a resin layer (6) disposed on the semiconductor element (4) and having a plurality of first openings (10) through which the semiconductor element (4) is exposed; conductive layers (7, 8) disposed on the resin layer (6) and having an upper surface located above the upper surface of the terminal portion (2a) and bonded to the semiconductor element (4) at the plurality of first openings (10); and a sealing component (9) having an upper surface parallel to the planar portion and integrally sealing the circuit component (2), the semiconductor element (4), the resin layer (6), the conductive layers (7, 8) and a portion of the terminal portion (2a).

Description

Technical Field

[0001] The present invention relates to a semiconductor device in which an electrode and a conductive layer on a semiconductor element are joined via a resin layer, and a power conversion device including the semiconductor device. Background Art

[0002] Generally speaking, in semiconductor devices, electrodes and other parts on semiconductor elements are wired using bonding wires made of aluminum or the like, and resin sealing is performed for circuit insulation. Conventionally, it is known that in semiconductor devices using bonding wires made of aluminum or the like as wiring, the life of the semiconductor device is shortened during reliability tests due to the breakage of the bonding wires and the peeling at the interface between the semiconductor element and the bonding wires, which is one of the causes of reliability degradation of the semiconductor device.

[0003] In order to improve the reliability of semiconductor devices, a semiconductor device is disclosed in which a metal plate is connected from a bonding wire with solder in the connection on a semiconductor element (for example, Patent Document 1). However, in this structure, only the emitter electrode of the semiconductor element is bonded with a metal plate, and a bonding wire is used for the gate electrode and the sensor electrode as in the past. Therefore, the thickness of the sealing resin used to seal the bonding wire becomes thicker, so the distance from the surface side of the semiconductor element to the outside of the sealing resin is long, and the heat dissipation is deteriorated.

[0004] Therefore, there is a demand for a semiconductor device that connects all electrodes using only a metal layer without using bonding wires as wiring. As a countermeasure, a structure that uses power overlay (POL) for wiring is disclosed (for example, Patent Document 2).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2015-53343

[0008] Patent Document 2: Japanese Patent Application Publication No. 2015-70269 Summary of the invention

[0009] However, in the conventional semiconductor devices, although a metal layer is used for wiring with semiconductor elements, vias are formed around the semiconductor elements, and vias are used for wiring between the upper and lower parts, so heat is also generated around the semiconductor elements, and the semiconductor elements are sometimes affected by heat. In addition, it is necessary to form terminals for electrical connection with the outside. When the terminals are taken out from the side of the semiconductor device, it is necessary to increase the distance from the back side of the semiconductor element to ensure insulation. Moreover, the terminals are arranged at a connectable position on the upper part of the metal layer, and the whole is sealed with a sealing resin. Therefore, when the heat generated in the semiconductor element is also dissipated from the metal layer on the surface side of the semiconductor element to the outside, the upper surface of the metal layer on the upper part of the semiconductor element becomes the same as or lower than the upper surface of the terminal, and there is a problem that the distance from the metal layer connected to the semiconductor element with low thermal resistance to the sealing resin is long, and the heat dissipation of the semiconductor device is sometimes deteriorated.

[0010] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a molded semiconductor device having high heat dissipation properties.

[0011] The semiconductor device comprises: a circuit component having a front surface and a back surface and having a planar portion; a terminal portion formed at an upper side than the surface of the planar portion of the circuit component and parallel to the planar portion; a semiconductor element having an upper surface located at a lower side than the upper surface of the terminal portion and formed on the surface of the planar portion of the circuit component; a resin layer arranged on the semiconductor element and having a plurality of first openings through which the semiconductor element is exposed; a conductive layer arranged on the resin layer and having an upper surface located at an upper side than the upper surface of the terminal portion and joined to the semiconductor element at the plurality of first openings; and a sealing component having an upper surface parallel to the planar portion and integrally sealing the circuit component, the semiconductor element, the resin layer, the conductive layer and a portion of the terminal portion.

[0012] According to the semiconductor device of the present invention, the upper surface of the conductive layer is arranged above the upper surface of the terminal portion, so that the distance from the conductive layer to the filling member can be shortened, and the heat dissipation of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 FIG. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with Embodiment 1 of the present invention.

[0014] Figure 2 FIG. 1 is a schematic diagram showing a planar structure of a semiconductor device in accordance with Embodiment 1 of the present invention.

[0015] Figure 3 1 is a schematic diagram showing a planar structure of the semiconductor device before the resin insulating layer is formed in the first embodiment of the present invention.

[0016] Figure 41 is a schematic diagram showing a planar structure of a resin insulating layer of the semiconductor device in the first embodiment of the present invention.

[0017] Figure 5 1 is a schematic diagram showing a planar structure of the semiconductor device after the resin insulating layer is formed in the first embodiment of the present invention.

[0018] Figure 6 It is a schematic diagram showing a planar structure of the semiconductor device after the conductive layer is formed in the first embodiment of the present invention.

[0019] Figure 7 FIG. 1 is a schematic diagram showing a planar structure of a conductive layer of a semiconductor device in accordance with Embodiment 1 of the present invention.

[0020] Figure 8 1 is a schematic diagram showing a planar structure near an opening portion of the semiconductor device in accordance with the first embodiment of the present invention.

[0021] Fig. 9 FIG. 1 is a schematic diagram showing a planar structure of another opening portion and its vicinity in the semiconductor device according to the first embodiment of the present invention.

[0022] Fig.10 FIG. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with a second embodiment of the present invention.

[0023] Fig.11 FIG. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with a third embodiment of the present invention.

[0024] Fig.12 FIG. 1 is a schematic diagram showing a planar structure of a semiconductor device in accordance with a third embodiment of the present invention.

[0025] Fig.13 FIG. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with a fourth embodiment of the present invention.

[0026] Fig.14 FIG. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with a fifth embodiment of the present invention.

[0027] Fig.15 It is a schematic diagram showing a cross-sectional structure of another semiconductor device in accordance with the fifth embodiment of the present invention.

[0028] Fig.16 It is a schematic diagram showing a cross-sectional structure of another semiconductor device in accordance with the fifth embodiment of the present invention.

[0029] Fig.17 FIG. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with a sixth embodiment of the present invention.

[0030] Fig.18FIG. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with a seventh embodiment of the present invention.

[0031] Fig.19 This is a block diagram showing the configuration of a power conversion system to which a power conversion device is applied in Embodiment 8 of the present invention.

[0032] (Explanation of symbols)

[0033] 1: heat conducting component; 1a: metal foil; 1b: insulating sheet; 2: lead frame; 2a: terminal portion; 2b: step portion; 2c: protrusion; 3: solder; 4: semiconductor element; 5: conductive spacer; 6: resin insulating layer; 7: conductive layer for main circuit; 8: conductive layer for control; 9: sealing resin; 10, 11: opening; 12: flow direction; 13: convex portion; 14: resin thickness; 15: insulating circuit substrate; 16: through hole; 17: terminal; 100, 200, 300, 400, 500, 501, 510, 600, 700, 2002: semiconductor device; 1000: power supply; 2000: power conversion device; 2001: main conversion circuit; 2003: control circuit; 3000: load. DETAILED DESCRIPTION

[0034] First, the overall structure of the semiconductor device of the present invention is described with reference to the accompanying drawings. In addition, the drawings are schematic drawings and do not reflect the exact size of the components shown. In addition, the parts with the same symbols are the same or equivalent, which is the same throughout the entire text of the specification.

[0035] Implementation method 1.

[0036] use Figure 1 , Figure 2 , describing the semiconductor device in embodiment 1 of the present invention.

[0037] Figure 1 FIG. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with Embodiment 1 of the present invention. Figure 2 FIG. 1 is a schematic diagram showing a planar structure of a semiconductor device in accordance with Embodiment 1 of the present invention. Figure 1 yes Figure 2 A schematic diagram of the cross-sectional structure along the single-dot chain line AA is shown.

[0038] exist Figure 1In the embodiment, the semiconductor device 100 includes a heat conducting member 1, a lead frame 2 as a circuit member, a solder 3 as a bonding material, a semiconductor element 4, a conductive spacer 5 as a connection member, a resin insulating layer 6 as a resin layer, a main circuit conductive layer 7 as a conductive layer (first conductive layer), a control conductive layer 8 as a conductive layer (second conductive layer), and a sealing resin 9 as a sealing member. In addition, the distance from the upper surface of the terminal portion 2a of the lead frame 2 as the terminal portion inside the sealing resin 9 to the upper surface of the sealing resin 9 is set to h1, the distance from the upper surface of the semiconductor element 4 to the upper surface of the sealing resin 9 is set to h2, and the distance from the upper surface of the main circuit conductive layer 7 and the control conductive layer 8 to the upper surface of the sealing resin 9 is set to h3. In addition, the upper surface of the sealing resin 9 is parallel to and opposite to the upper surface of the terminal portion 2a of the lead frame 2 and the upper surface of the semiconductor element 4.

[0039] The heat conducting member 1 includes a metal foil 1a and an insulating sheet 1b formed on the upper surface of the metal foil 1a. The heat conducting member 1 is an insulating layer with high heat dissipation. The insulating sheet 1b has the function of insulating the metal foil 1a from the lead frame 2 and dissipating the heat generated in the semiconductor element 4 to the metal foil 1a via the insulating sheet 1b. As the metal foil 1a, a high heat conducting member such as a copper plate, an aluminum plate, or a copper foil is used.

[0040] The insulating sheet 1 b is made of a thermosetting resin such as epoxy resin, and a high-conductivity filler such as silicon dioxide, aluminum oxide, or boron nitride is mixed therein.

[0041] A lead frame 2 having a predetermined wiring structure (wiring circuit) formed thereon is provided on the thermally conductive member 1. The lead frame 2 has a front surface and a back surface. The back surface of the lead frame 2 is disposed on the insulating sheet 1b of the thermally conductive member 1. The back surface electrode of the semiconductor element 4 is bonded to the wiring circuit on the surface of the lead frame 2 via the solder 3 as a bonding material.

[0042] In the lead frame 2, for example, a flat copper plate with a thickness of about 0.6 mm is used to form a wiring circuit having a planar portion by stamping. In addition, the wiring circuit of the lead frame 2 has a terminal portion 2a and a step portion (inclined portion) 2b. The terminal portion 2a is connected to the wiring circuit of the lead frame 2 on which the semiconductor element 4 is arranged via the step portion 2b. The terminal portion 2a and the step portion 2b of the lead frame 2 are not in contact with the heat conduction member 1 due to the formation of the step portion 2b. Therefore, the area between the metal foil 1a of the heat conduction member 1 and the terminal portion 2a and the step portion 2b of the lead frame 2 becomes a portion where the sealing resin 9 enters. The step portion 2b of the lead frame 2 is a structure for suppressing insulation breakdown along the interface between the metal foil 1a of the heat conduction member 1 and the sealing resin 9. In addition, the terminal portion 2a is arranged inside the sealing resin 9. A part of the terminal portion 2a protrudes from the inside of the side surface of the sealing resin 9 to the outside. The terminal portion 2a is formed at a position higher than the surface of the planar portion of the lead frame 2.

[0043] The step portion 2b of the lead frame 2 is formed, for example, by half punching (half etching). The height of the step portion 2b of the lead frame 2 is set, for example, to be greater than or equal to 0.1 mm and less than or equal to 0.3 mm, which is half the thickness of the lead frame 2. By setting the height of the step portion 2b of the lead frame 2 to be greater than or equal to 0.1 mm, the generation of voids in the sealing resin 9 filled between the heat conducting member 1 and the lead frame 2 can be suppressed.

[0044] In addition, by setting the height of the step portion 2b of the lead frame 2 to be 0.3 mm or less, which is half the thickness of the lead frame 2, the strength of the lead frame 2 can be ensured. Furthermore, by providing the step portion 2b and filling the step portion 2b with the sealing resin 9, the insulation withstand voltage between the metal foil 1a of the heat conducting member 1 and the lead frame 2 can be improved.

[0045] Here, the terminal portion 2a of the lead frame 2 inside the sealing resin 9 is arranged above the mounting portion (region) of the semiconductor element 4 on the surface (upper surface) of the lead frame 2 by providing the step portion 2b in the lead frame 2. The semiconductor element 4 is arranged on the surface of the lead frame 2. The upper surface of the semiconductor element 4 is arranged closer to the surface side (lower side) of the lead frame 2 than the upper surface of the terminal portion 2a of the lead frame 2. That is, the distance (h1) from the upper surface of the terminal portion 2a of the lead frame 2 inside the sealing resin 9 to the upper surface of the sealing resin 9 is smaller than the distance (h2) from the upper surface of the semiconductor element 4 to the upper surface of the sealing resin 9. In addition, the upper surface of the terminal portion 2a of the lead frame 2 inside the sealing resin 9 is arranged above the upper surface of the semiconductor element 4. The upper surface of the semiconductor element 4 is located below the upper surface of the terminal portion 2a. By arranging in this way, the insulation withstand voltage between the metal foil 1a of the heat conducting member 1 and the terminal portion 2a of the lead frame 2 as described above can be improved.

[0046] The semiconductor element 4 includes a diode used in a converter section that converts input AC power into DC power, a bipolar transistor used in an inverter section that converts DC power into AC power, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a GTO (Gate Turn-Off Thyristor), etc.

[0047] The conductive spacer 5 is formed on the same surface of the upper surface of the lead frame 2 where the semiconductor element 4 is arranged (joined), and is electrically connected to the semiconductor element 4 via the main circuit conductive layer 7 and the control conductive layer 8. As for the conductive spacer 5, a metal plate such as copper or aluminum is arranged at a predetermined position on the upper surface of the lead frame 2 using solder 3 or the like. It can also be formed by stacking solder 3 instead of the metal plate. In addition, the conductive spacer 5 can also be used as a supporting member for the resin insulating layer 6 by, for example, arranging a non-conductive plate at a place where electrical connection is not required by installing it with an adhesive. The height of the conductive spacer 5 is the same as the height of the semiconductor element 4 in the range where the resin insulating layer 6 can be formed on the upper part.

[0048] For the resin insulating layer 6, for example, a polymer material such as a liquid crystal polymer or polyimide is used. The resin insulating layer 6 is made of a single-layer resin film formed by spin coating, printing, etc. using these materials, or a laminated film obtained by stacking resin films. The resin insulating layer 6 has a film thickness that can electrically insulate the semiconductor element 4 on the lower surface side of the resin insulating layer 6 and the main circuit conductive layer 7 or the control conductive layer 8 on the upper surface side of the resin insulating layer 6. In addition, the resin insulating layer 6 can also be made into parts with different thicknesses by stacking (stacking) resin films at predetermined positions of the resin insulating layer 6 where insulation withstand voltage is required.

[0049] The resin insulating layer 6 is in sheet form and is arranged continuously (across) between the upper surfaces of the semiconductor element 4. In addition, it is arranged continuously on the upper surface of the semiconductor element 4 and the upper surface of the conductive spacer 5. In the resin insulating layer 6, an opening 10 as a first opening is formed at a position where the semiconductor element 4 or the conductive spacer 5 is electrically connected to the main circuit conductive layer 7 or the control conductive layer 8 respectively. The opening 10 is connected to the semiconductor element 4 and the conductive spacer 5 at different opening positions. For example, the opening 10 is filled with copper as a material by plating or other methods and is deposited on the upper surface of the resin insulating layer 6, and the main circuit conductive layer 7 and the control conductive layer 8 are wired through the opening 10 of the resin insulating layer 6. The opening 10 can also be formed in multiple places in the resin insulating layer 6 in coordination with the circuit structure. Regarding the size of the opening 10, it can also be formed in multiple sizes according to the purpose.

[0050] In addition, an opening 11 as a second opening is formed in the resin insulating layer 6. In a plan view, at least a portion of the periphery of the opening 11 includes an area other than an area where the semiconductor element 4 or the conductive spacer 5 is arranged on the surface of the lead frame 2 (a portion not in contact with either of them) (see FIG. Figure 2 , 7 , 8). The opening 11 is formed by including a narrow gap formed between the semiconductor elements 4, the conductive spacer 5, or between the semiconductor element 4 and the conductive spacer 5. When the sealing resin 9 is filled and sealed, the narrow gap between the semiconductor elements 4 or between the conductive spacers 5 is filled with the sealing resin 9 through the opening 11. Thus, the sealing resin 9 is filled on the lower surface side of the resin insulating layer 6.

[0051] The main circuit conductive layer 7 is, for example, bonded to a source electrode or an emitter electrode that is a main electrode of the semiconductor element 4. In addition, the control conductive layer 8 is, for example, bonded to a gate electrode or a sensor electrode that is a control electrode of the semiconductor element 4. In the present embodiment, the main circuit conductive layer 7 and the control conductive layer 8 are aligned in thickness direction (have the same thickness), indicating that the time for depositing the conductive layers by plating or the like is the same. Furthermore, for example, in the case where the semiconductor element 4 is a diode, there is no control electrode, so only the main circuit conductive layer 7 is bonded to the main electrode of the diode. In addition, in the case where a plurality of semiconductor elements 4 are used, the main circuit conductive layer 7 connects the plurality of semiconductor elements 4 or the semiconductor element 4 and the conductive spacer 5. The control conductive layer 8 connects the control electrode of the semiconductor element 4 and the conductive spacer 5.

[0052] The thickness of the main circuit conductive layer 7 and the control conductive layer 8 is greater than that of the resin insulating layer 6. When the thickness of the main circuit conductive layer 7 and the control conductive layer 8 is thinner than that of the resin insulating layer 6, the opening 10 cannot be filled, and the resistance value of the conductive layer increases, and sometimes it does not function as a current path. Furthermore, due to the increase in resistance, excessive heat is generated, so the heat generated cannot be efficiently dissipated to the outside of the sealing resin 9, and the heat dissipation property is deteriorated. However, by making the thickness of the main circuit conductive layer 7 and the control conductive layer 8 thicker than that of the resin insulating layer 6, the opening 10 can be filled, and the main circuit conductive layer 7 and the control conductive layer 8 can be formed on the resin insulating layer 6. In addition, by making the thickness of the main circuit conductive layer 7 and the control conductive layer 8 thicker than that of the resin insulating layer 6, the resistance value of the main circuit conductive layer 7 and the control conductive layer 8 can be reduced, and the heat capacity of the main circuit conductive layer 7 and the control conductive layer 8 is also increased, and more heat generated by the semiconductor element 4 can be collected. Furthermore, by conducting heat to the upper portion of the sealing resin 9 via the main circuit conductive layer 7 and the control conductive layer 8 , the cooling efficiency can be improved.

[0053] In addition, the distance (h3) from the upper surface of the main circuit conductive layer 7 and the control conductive layer 8 to the upper surface of the sealing resin 9 is set to be less than the distance (h1) from the upper surface of the terminal portion 2a of the lead frame 2 inside the sealing resin 9 to the upper surface of the sealing resin 9. In other words, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are arranged at a position closer to the upper surface side of the sealing resin 9 than the upper surface of the terminal portion 2a of the lead frame 2 inside the sealing resin 9. The upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are located at a position higher than the upper surface of the terminal portion 2a. The heat generated from the semiconductor element 4 and the like is mainly conducted from the lead frame 2 to the heat conducting member 1 on the back side of the lead frame 2 on the lower surface side of the semiconductor element 4 and dissipated to the outside on the lower surface side of the sealing resin 9. On the upper surface side of the semiconductor element 4, it is considered that the heat is dissipated from the upper surface of the main circuit conductive layer 7 and the control conductive layer 8 bonded to the upper surface of the semiconductor element 4 to the outside from the upper surface of the sealing resin 9 via the sealing resin 9.

[0054] When the outer dimensions of the semiconductor device are the same and the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are closer to the arrangement side (lower side) of the semiconductor element 4 of the lead frame 2 than the upper surface of the terminal portion 2a of the lead frame 2, the thickness of the main circuit conductive layer 7 and the control conductive layer 8 becomes thinner. In addition, the distance from the main circuit conductive layer 7 and the control conductive layer 8 to the upper surface of the sealing resin 9 becomes longer. Therefore, the Joule heat generated by the current flowing through the main circuit conductive layer 7 and the control conductive layer 8 and the heat generated in the semiconductor element 4 are combined and conducted to the main circuit conductive layer 7 and the control conductive layer 8, but the distance from the upper surface side of the main circuit conductive layer 7 and the control conductive layer 8 to the outside of the sealing resin 9 is long, so that the heat cannot be efficiently dissipated from the upper surface side of the semiconductor element 4 to the outside of the sealing resin 9 and is conducted in the lead frame 2, and most of the heat is dissipated from the heat conductive member 1 on the back side of the lead frame 2 to the outside of the sealing resin 9, so the heat is concentrated on the heat conductive member 1 and the heat dissipation of the semiconductor device is deteriorated.

[0055] However, in the semiconductor device 100 of the first embodiment, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are arranged at a position higher than the upper surface of the terminal portion 2a of the lead frame 2 inside the sealing resin 9 (the upper surface side of the sealing resin 9). Therefore, the thickness of the sealing resin 9 on the main circuit conductive layer 7 and the control conductive layer 8 can be formed thin. Therefore, the distance from the upper surface of the main circuit conductive layer 7 and the control conductive layer 8 to the upper surface (outside) of the sealing resin 9 can be shortened, and a part of the heat conducted in the lead frame 2 and dissipated from the heat conducting member 1 on the back side of the lead frame 2 to the outside can be mainly shared by the upper surface side of the main circuit conductive layer 7 and the control conductive layer 8 to dissipate heat. Therefore, by efficiently conducting the heat generated on the upper surface side of the semiconductor element 4 to the outside of the sealing resin 9 and dissipating the heat, the cooling efficiency can be improved. In addition, the size of the semiconductor device 100 can be maintained as it is and the heat dissipation can be improved. As a result, the reliability of the semiconductor device 100 can be improved. In particular, in a usage situation where operation at a high temperature is required, it is effective to use heat dissipation at multiple locations.

[0056] The sealing resin 9 ensures insulation between the sealed components and functions as a housing of the semiconductor device 100. The sealing resin 9 seals the lead frame 2, the semiconductor element 4, the conductive spacer 5, the resin insulating layer 6, and the conductive layers 7 and 8 as a whole. In the sealing resin 9, the surface side of the lead frame 2 where the semiconductor element 4 is arranged is the upper surface side, and the back side of the lead frame 2 where the semiconductor element 4 is not arranged is the lower surface side. As a molding method of the sealing resin 9, for example, transfer molding, injection molding, compression molding, etc. can be used. In addition, as a material of the sealing resin 9, for example, epoxy resin, phenolic resin, etc. containing a filler can be used.

[0057] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment configured as described above will be described.

[0058] Figures 3 to 9 FIG. 1 is a schematic plan view showing a manufacturing process of a semiconductor device in Embodiment 1 of the present invention. Figure 3 , Figure 5 , Figure 6 After the process of resin sealing, it can be manufactured Figure 2 A semiconductor device 100 is shown.

[0059] Figure 3 1 is a schematic diagram showing a planar structure of the semiconductor device before the resin insulating layer is formed in the first embodiment of the present invention. Figure 4 1 is a schematic diagram showing a planar structure of a resin insulating layer of the semiconductor device in the first embodiment of the present invention. Figure 51 is a schematic diagram showing a planar structure of the semiconductor device after the resin insulating layer is formed in the first embodiment of the present invention. Figure 6 It is a schematic diagram showing a planar structure of the semiconductor device after the conductive layer is formed in the first embodiment of the present invention. Figure 7 FIG. 1 is a schematic diagram showing a planar structure of a conductive layer of a semiconductor device in accordance with Embodiment 1 of the present invention.

[0060] First, if Figure 3 As shown, a semiconductor element 4 and a conductive spacer 5 are bonded to a predetermined position on the surface of a lead frame 2 via solder 3 (component placement step).

[0061] Next, if Figure 5 As shown in FIG. 1 , a resin insulating layer 6 is formed on the semiconductor element 4 and the conductive spacer 5 bonded to the surface of the lead frame 2 (resin insulating layer forming step). Figure 4 As shown, openings 10 are provided in advance at positions that will become the upper parts of the semiconductor element 4 and the conductive spacer 5. The openings 10 are provided at a plurality of locations in the resin insulating layer 6, each of which has a shape that matches the electrode shape of the semiconductor element 4 or the shape of the conductive spacer 5 and can be connected to the main circuit conductive layer 7 and the control conductive layer 8 in the subsequent process.

[0062] Next, if Figure 6 As shown in FIG. 1 , the main circuit conductive layer 7 and the control conductive layer 8 are arranged on the upper surface of the resin insulating layer 6 (conductive layer forming step). At this time, as described above, the semiconductor element 4 and the main circuit conductive layer 7, the conductive spacer 5 and the control conductive layer 8 are electrically connected to each other through the opening 10 formed in the resin insulating layer 6. The main circuit conductive layer 7 and the control conductive layer 8 are connected to the semiconductor element 4 and the conductive spacer 5 by depositing a metal component such as copper by plating, etc., to form Figure 2 The structure shown.

[0063] Figure 7 An example of a schematic plan view of the main circuit conductive layer 7 and the control conductive layer 8 is shown, but the main circuit conductive layer 7 and the control conductive layer 8 may be formed into a conductive layer shape that matches the wiring circuit formed on the surface of the lead frame 2 .

[0064] Next, the lead frame 2 that has gone through these steps is sealed with a sealing resin 9 (resin sealing step). Figure 1As shown in FIG. 1 , the heat conducting member 1 and the lead frame 2 manufactured in the above process are put into the mold. After being put into the mold, the sealing resin 9 is molded (sealed) by transfer molding, compression molding, injection molding, etc. At this time, the sealing resin 9 fills the space between the lead frame 2 and the resin insulating layer 6 through the opening 11 provided in the resin insulating layer 6. In addition, in the resin sealing process, the resin insulating layer 6 does not soften due to the heat during the resin sealing process and maintains the shape of the resin insulating layer 6 when it is formed. That is, the resin insulating layer 6 is formed using a material having better heat resistance than the sealing resin 9.

[0065] Figure 8 1 is a schematic diagram showing a planar structure near an opening portion of the semiconductor device in accordance with the first embodiment of the present invention. Fig. 9 FIG. 1 is a schematic diagram showing a planar structure of another opening portion and its vicinity in the semiconductor device according to the first embodiment of the present invention.

[0066] like Figure 8 As shown in FIG. 1 , when the opening 11 as the second opening of the resin insulating layer 6 has a portion in contact with the conductive spacer 5 and the like around it, compared to Fig. 9 In the case where there is no portion in contact with the conductive spacer 5, the sealing resin 9 does not flow in the direction of the portion in contact but flows in the direction of the portion without contact, so the flow direction 12 of the sealing resin 9 can also be arbitrarily controlled by the formation position of the opening 11. In addition, after the sealing resin 9 is molded, the opening 11 is filled with the sealing resin 9.

[0067] In the semiconductor device 100 configured as described above, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are arranged above the upper surface of the terminal portion 2a of the lead frame 2, so that the heat generated in the semiconductor element 4 can be efficiently conducted to the outside of the sealing resin 9 from the upper surface side of the semiconductor element 4, and the cooling efficiency can be improved. As a result, the reliability of the semiconductor device 100 can be improved.

[0068] Implementation method 2.

[0069] In the second embodiment, the thickness of the main circuit conductive layer 7 used in the first embodiment is made thicker than the thickness of the control conductive layer 8. In this way, by making the thickness of the main circuit conductive layer 7 bonded to the semiconductor element 4 thicker than the thickness of the control conductive layer 8, the heat from the semiconductor element 4 with a large heat generation can be efficiently dissipated. In addition, other aspects are the same as those in the first embodiment, so detailed description is omitted.

[0070] In this case, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are also arranged to be higher than the upper surface of the terminal portion 2a of the lead frame 2, so that the heat generated in the semiconductor element 4 can be efficiently conducted to the outside of the sealing resin 9 from the upper surface side of the semiconductor element 4, and the cooling efficiency can be improved. As a result, the reliability of the semiconductor device can be improved.

[0071] Fig.10 FIG. 2 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with a second embodiment of the present invention. Fig.10 In the embodiment, the semiconductor device 200 includes a heat conducting member 1, a lead frame 2 as a circuit member, a solder 3 as a bonding material, a semiconductor element 4, a conductive spacer 5 as a connecting member, a resin insulating layer 6 as a resin layer, a main circuit conductive layer 7 as a first conductive layer, a control conductive layer 8 as a second conductive layer, a sealing resin 9 as a sealing member, and an opening 10 as a first opening. The thickness of the main circuit conductive layer 7 is thicker than that of the control conductive layer 8. In addition, the lead frame 2 has a terminal portion 2a as a terminal portion and a step portion (inclined portion) 2b.

[0072] like Fig.10 The main circuit conductive layer 7 shown can be formed by depositing the main circuit conductive layer 7 thicker by plating, and bonding thick copper metal plates by pressing, etc. Thus, the main circuit conductive layer 7 thicker than the control conductive layer 8 can be obtained.

[0073] In the semiconductor device 200 configured as described above, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are arranged above the upper surface of the terminal portion 2a of the lead frame 2, so that the heat generated in the semiconductor element 4 can be efficiently conducted to the outside of the sealing resin 9 from the upper surface side of the semiconductor element 4, and the cooling efficiency can be improved. As a result, the reliability of the semiconductor device 200 can be improved.

[0074] Furthermore, by making the thickness of the main circuit conductive layer 7 bonded to the semiconductor element 4 thicker than the thickness of the control conductive layer 8 , it is possible to efficiently dissipate the heat from the semiconductor element 4 which generates a large amount of heat.

[0075] Implementation method 3.

[0076] In the third embodiment, the thickness of the resin insulating layer 6 used in the second embodiment is different in that the thickness is thicker on the periphery of the semiconductor element 4 than on the outside of the periphery of the semiconductor element 4. In this way, the resin insulating layer 6 on the periphery of the semiconductor element 4 is thicker, so the insulation of the semiconductor device can be further improved. In addition, other aspects are the same as those of the second embodiment, so detailed description is omitted.

[0077] In this case, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are also arranged to be higher than the upper surface of the terminal portion 2a of the lead frame 2, so that the heat generated in the semiconductor element 4 can be efficiently conducted to the outside of the sealing resin 9 from the upper surface side of the semiconductor element 4, and the cooling efficiency can be improved. As a result, the reliability of the semiconductor device can be improved.

[0078] Fig.11 FIG. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with a third embodiment of the present invention. Fig.12 FIG. 2 is a schematic diagram showing a planar structure of a semiconductor device in Embodiment 3 of the present invention. Fig.11 In the embodiment, the semiconductor device 300 includes a heat conducting member 1, a lead frame 2 as a circuit member, a solder 3 as a bonding material, a semiconductor element 4, a conductive spacer 5 as a connecting member, a resin insulating layer 6 as a resin layer, a main circuit conductive layer 7 as a first conductive layer, a control conductive layer 8 as a second conductive layer, a sealing resin 9 as a sealing member, an opening 10 as a first opening, and a convex portion 13 of the resin insulating layer 6. The thickness of the main circuit conductive layer 7 is thicker than that of the control conductive layer 8. In addition, the convex portion 13 of the resin insulating layer 6 is formed on the outer periphery of the semiconductor element 4. The thickness of the convex portion 13 of the resin insulating layer 6 is thicker than the thickness of the resin insulating layer 6 outside the outer periphery of the semiconductor element 4. Furthermore, the lead frame 2 includes a terminal portion 2a as a terminal portion and a step portion (inclined portion) 2b.

[0079] like Fig.11 , 12 As shown in FIG. 1 , further, in order to improve the insulation of the semiconductor device, the resin insulating layer 6 on the outer periphery of the semiconductor element 4 is provided with a convex portion 13. In this embodiment, the convex portion 13 is pre-formed at the portion of the resin insulating layer 6 that contacts the outer periphery of the semiconductor element 4. Fig.11 As shown, the outer peripheral portion in contact with the semiconductor element 4 mounted on the lead frame 2 is thickened, and an opening 10 is formed by punching or the like in the electrode portion forming the circuit layer.

[0080] In the semiconductor device 300 configured as described above, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are arranged above the upper surface of the terminal portion 2a of the lead frame 2, so that the heat generated in the semiconductor element 4 can be efficiently conducted to the outside of the sealing resin 9 from the upper surface side of the semiconductor element 4, and the cooling efficiency can be improved. As a result, the reliability of the semiconductor device 300 can be improved.

[0081] Furthermore, by making the thickness of the main circuit conductive layer 7 bonded to the semiconductor element 4 thicker than the thickness of the control conductive layer 8 , it is possible to efficiently dissipate the heat from the semiconductor element 4 which generates a large amount of heat.

[0082] Furthermore, since the protrusions 13 are provided on the resin insulating layer 6 in contact with the outer periphery of the semiconductor element 4 , the insulation reliability of the semiconductor device 300 can be improved.

[0083] Implementation method 4.

[0084] In the fourth embodiment, the heat conducting member 1 used in the third embodiment is removed and the back side of the lead frame 2 is also sealed with the sealing resin 9 containing the filler with high thermal conductivity. In this way, the back side of the lead frame 2 is also sealed with the sealing resin containing the filler with high thermal conductivity, so that the insulation and heat dissipation of the semiconductor device can be improved. In addition, other aspects are the same as those of the third embodiment, so detailed description is omitted.

[0085] In this case, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are also arranged to be higher than the upper surface of the terminal portion 2a of the lead frame 2, so that the heat generated in the semiconductor element 4 can be efficiently conducted to the outside of the sealing resin 9 from the upper surface side of the semiconductor element 4, and the cooling efficiency can be improved. As a result, the reliability of the semiconductor device can be improved.

[0086] Fig.13 FIG. 4 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with a fourth embodiment of the present invention. Fig.13 In the figure, the semiconductor device 400 includes a lead frame 2 as a circuit component, a solder 3 as a bonding material, a semiconductor element 4, a conductive spacer 5 as a connecting component, a resin insulating layer 6 as a resin layer, a main circuit conductive layer 7 as a first conductive layer, a control conductive layer 8 as a second conductive layer, a sealing resin 9 as a sealing component, an opening 10 as a first opening, and a convex portion 13 of the resin insulating layer 6. The thickness of the main circuit conductive layer 7 is thicker than that of the control conductive layer 8. In addition, the convex portion 13 is formed on the outer peripheral portion of the resin insulating layer 6 that is in contact with the semiconductor element 4. Furthermore, the lead frame 2 has a terminal portion 2a and a step portion (inclined portion) 2b as a terminal portion.

[0087] exist Fig.13 In the embodiment, a sealing resin 9 is also formed on the back side of the lead frame 2. Thus, the lead frame 2 is enclosed by the sealing resin 9. A filler with high thermal conductivity is used for the sealing resin 9, for example, a metal oxide such as silicon dioxide and aluminum oxide, a nitride such as aluminum nitride and boron nitride. The sealing resin 9 contains a filler containing at least one of a metal oxide and a nitride.

[0088] In this embodiment, if Fig.13As shown, the sealing resin 9 has the function of ensuring the insulation of the lead frame 2 and the main circuit conductive layer 7 and the function of dissipating the heat from the semiconductor element 4 simultaneously with the function of the resin frame by including the whole. Therefore, the distance from the lower surface of the sealing resin 9 to the back side of the lead frame 2, that is, the thickness 14 of the sealing resin 9 on the back side of the lead frame 2 and the distance from the upper surface of the main circuit conductive layer 7 to the upper surface of the sealing resin 9, that is, the thickness 14 of the sealing resin 9 on the upper side of the main circuit conductive layer 7 are preferably 0.1 mm or more and 1.0 mm or less from the viewpoint of the heat dissipation and insulation of the semiconductor device. When the thickness 14 is thinner than 0.1 mm, the insulation cannot be ensured. In addition, when the thickness 14 is thicker than 1.0 mm, the heat dissipation is sometimes deteriorated. Therefore, the range of the thickness 14 is preferably 0.1 mm or more and 1.0 mm or less.

[0089] In the semiconductor device 400 configured as described above, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are arranged above the upper surface of the terminal portion 2a of the lead frame 2, so that the heat generated in the semiconductor element 4 can be efficiently conducted to the outside of the sealing resin 9 from the upper surface side of the semiconductor element 4, and the cooling efficiency can be improved. As a result, the reliability of the semiconductor device 400 can be improved.

[0090] Furthermore, since the thickness of the main circuit conductive layer 7 bonded to the semiconductor element 4 is made thicker than the thickness of the control conductive layer 8 , the heat from the semiconductor element 4 which generates a large amount of heat can be efficiently dissipated.

[0091] Furthermore, since the protrusions 13 are provided on the resin insulating layer 6 in contact with the outer periphery of the semiconductor element 4 , the insulation reliability of the semiconductor device 400 can be improved.

[0092] Furthermore, since the back surface side of the lead frame 2 is also sealed with the sealing resin 9 containing a filler having high thermal conductivity, the insulation and heat dissipation properties of the semiconductor device 400 can be improved.

[0093] Implementation method 5.

[0094] In the fifth embodiment, the circuit component 2 used in the third embodiment is replaced with an insulating circuit substrate 15, and the back side of the insulating circuit substrate 15 is also sealed with a sealing resin 9. In this way, the insulating circuit substrate 15 is used, and the back side of the insulating circuit substrate 15 is also sealed with a sealing resin, so that the insulation and heat dissipation of the semiconductor device can be improved. In addition, other aspects are the same as those of the third embodiment, so detailed description is omitted.

[0095] In this case, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are also arranged to be above the upper surface of the terminal 17 of the insulating circuit substrate 15, so that the heat generated in the semiconductor element 4 can be efficiently conducted to the outside of the sealing resin 9 from the upper surface side of the semiconductor element 4, and the cooling efficiency can be improved. As a result, the reliability of the semiconductor device can be improved.

[0096] Fig.14 FIG. 2 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with a fifth embodiment of the present invention. Fig.14 In the embodiment, the semiconductor device 500 includes an insulating circuit substrate 15 as a circuit component, a solder 3 as a bonding material, a semiconductor element 4, a conductive spacer 5 as a connecting component, a resin insulating layer 6 as a resin layer, a main circuit conductive layer 7 as a first conductive layer, a control conductive layer 8 as a second conductive layer, a sealing resin 9 as a sealing component, an opening 10 as a first opening, a convex portion 13 of the resin insulating layer 6, and a terminal 17 as a terminal portion. The thickness of the main circuit conductive layer 7 is thicker than that of the control conductive layer 8. In addition, the convex portion 13 is formed around the region of the resin insulating layer 6 that is in contact with the semiconductor element 4.

[0097] The insulating circuit substrate 15 has metal layers 15c and 15b on both sides (front and back) of the insulating layer 15a. For the insulating circuit substrate 15, a substrate containing fillers and resin such as a plate-like printed wiring substrate can be used, for example, a substrate in which a metal rolled material such as copper is attached to both sides of ceramics such as alumina, aluminum nitride, and silicon nitride.

[0098] In this embodiment, if Fig.14 As shown, the terminal 17 is bonded to the metal layer 15c on the surface of the insulating circuit substrate 15 by the solder 3. Therefore, when the sealing resin 9 is used, the insulating circuit substrate 15 is formed by clamping the terminal 17 with the mold so that the insulating circuit substrate 15 floats from the bottom surface inside the mold (the surface of the lower mold). Then, the sealing resin 9 also spreads to the back side of the insulating circuit substrate 15. The portion of the terminal 17 protruding into the mold is sealed inside the sealing resin 9 after being sealed with the sealing resin 9. The portion of the terminal 17 clamped by the mold protrudes from the inside of the sealing resin 9 to the outside after being sealed with the sealing resin 9. The upper surface of the semiconductor element 4 is arranged to be closer to the surface side of the insulating circuit substrate 15 than the upper surface of the terminal 17 of the insulating circuit substrate 15. That is, it is arranged in a manner that the distance from the upper surface of the terminal 17 inside the sealing resin 9 to the upper surface of the sealing resin 9 is smaller than the distance from the upper surface of the semiconductor element 4 to the upper surface of the sealing resin 9.

[0099] In addition, if Fig.14As shown, the sealing resin 9 has the function of ensuring the insulation of the insulating circuit substrate 15 and the main circuit conductive layer 7 and the function of dissipating the heat from the semiconductor element 4 simultaneously with the function of the resin frame by including the entire semiconductor device 500. Therefore, the distance from the lower surface of the sealing resin 9 to the back side of the metal layer 15b of the insulating circuit substrate 15, that is, the thickness 14 of the sealing resin 9 on the back side of the metal layer 15b, and the distance from the upper surface of the main circuit conductive layer 7 to the upper surface of the sealing resin 9, that is, the thickness 14 of the sealing resin 9 on the upper side of the main circuit conductive layer 7, are preferably 0.1 mm or more and 1.0 mm or less from the viewpoint of the heat dissipation and insulation of the semiconductor device. When the thickness 14 is thinner than 0.1 mm, the insulation cannot be ensured. In addition, when the thickness 14 is thicker than 1.0 mm, the heat dissipation is sometimes deteriorated. Therefore, the range of the thickness 14 is preferably 0.1 mm or more and 1.0 mm or less.

[0100] Fig.15 FIG. 2 is a schematic diagram showing a cross-sectional structure of another semiconductor device in Embodiment 5 of the present invention. Fig.15 In the embodiment, the semiconductor device 501 includes an insulating circuit substrate 15 as a circuit component, a solder 3 as a bonding material, a semiconductor element 4, a conductive spacer 5 as a connecting component, a resin insulating layer 6 as a resin layer, a main circuit conductive layer 7 as a first conductive layer, a control conductive layer 8 as a second conductive layer, a sealing resin 9 as a sealing component, an opening 10 as a first opening, a convex portion 13 of the resin insulating layer 6, and a terminal 17 as a terminal portion. The thickness of the main circuit conductive layer 7 is thicker than that of the control conductive layer 8. In addition, the convex portion 13 is formed around the area of ​​the resin insulating layer 6 that is in contact with the semiconductor element 4. Furthermore, a cooler 20 is provided on the upper surface and the lower surface of the semiconductor device 501 via a grease 21.

[0101] like Fig.15 As shown in FIG. 1 , the cooling performance can be improved by providing the cooler 20 on the upper surface and the lower surface of the semiconductor device. The cooler 20 can also be provided on only one of the upper surface and the lower surface according to the required cooling capacity.

[0102] Fig.16 FIG. 2 is a schematic diagram showing a cross-sectional structure of another semiconductor device in Embodiment 5 of the present invention. Fig.16In the embodiment, the semiconductor device 510 includes an insulating circuit substrate 15 as a circuit component, a solder 3 as a bonding material, a semiconductor element 4, a conductive spacer 5 as a connecting component, a resin insulating layer 6 as a resin layer, a main circuit conductive layer 7 as a first conductive layer, a control conductive layer 8 as a second conductive layer, a sealing resin 9 as a sealing component, an opening 10 as a first opening, a convex portion 13 of the resin insulating layer 6, and a terminal 17 as a terminal portion. The thickness of the main circuit conductive layer 7 is thicker than that of the control conductive layer 8. In addition, the convex portion 13 is formed around the region of the resin insulating layer 6 that is in contact with the semiconductor element 4. Furthermore, the structure is set to expose the back surface of the metal layer 15c on the back surface of the insulating circuit substrate 15 from the sealing resin 9.

[0103] Here, the terminal 17 of the insulating circuit substrate 15 inside the sealing resin 9 is arranged above the mounting portion (region) of the semiconductor element 4 on the surface (upper surface) of the insulating circuit substrate 15. The semiconductor element 4 is arranged on the surface of the insulating circuit substrate 15. The upper surface of the semiconductor element 4 is arranged closer to the surface side of the insulating circuit substrate 15 than the upper surface of the terminal 17 of the insulating circuit substrate 15. That is, the distance (h1) from the upper surface of the terminal 17 of the insulating circuit substrate 15 inside the sealing resin 9 to the upper surface of the sealing resin 9 is smaller than the distance (h2) from the upper surface of the semiconductor element 4 to the upper surface of the sealing resin 9. By such an arrangement, the insulation withstand voltage between the metal layer 15c on the back side of the insulating layer of the insulating circuit substrate 15 and the terminal 17 of the insulating circuit substrate 15 can be improved.

[0104] In addition, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are arranged at a position closer to the upper surface side of the sealing resin 9 than the upper surface of the terminal 17 of the insulating circuit substrate 15 inside the sealing resin 9. In addition, the upper surface of the terminal 17 of the insulating circuit substrate 15 inside the sealing resin 9 is arranged at a position higher than the upper surface of the semiconductor element 4. Therefore, by efficiently conducting the heat generated on the upper surface side of the semiconductor element 4 to the outside of the sealing resin 9 and dissipating the heat, the cooling efficiency can be improved. As a result, the reliability of the semiconductor devices 500, 501, and 510 can be improved. In particular, in a usage condition such as requiring operation in a high temperature state, it becomes effective to use heat dissipation in multiple places.

[0105] In the semiconductor devices 500, 501, and 510 configured as described above, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are arranged above the upper surface of the terminal 17 of the insulating circuit substrate 15, so that the heat generated in the semiconductor element 4 can be efficiently conducted to the outside of the sealing resin 9 from the upper surface side of the semiconductor element 4, and the cooling efficiency can be improved. As a result, the reliability of the semiconductor devices 500, 501, and 510 can be improved.

[0106] Furthermore, by making the thickness of the main circuit conductive layer 7 bonded to the semiconductor element 4 thicker than the thickness of the control conductive layer 8 , it is possible to efficiently dissipate the heat from the semiconductor element 4 which generates a large amount of heat.

[0107] Furthermore, since the protrusions 13 are provided on the resin insulating layer 6 in contact with the outer periphery of the semiconductor element 4 , the insulation reliability of the semiconductor devices 500 , 501 , and 510 can be improved.

[0108] Implementation method 6.

[0109] In the sixth embodiment, the insulating circuit substrate 15 used in the fifth embodiment is different in that the through hole 16 is provided in order to improve the heat dissipation. In this way, the through hole 16 is provided in the insulating circuit substrate 15, and a copper column or the like is inserted into the through hole 16 to connect the metal layer 15b and the metal layer 15c, so that the heat conductivity of the metal layer 15c from the insulating circuit substrate 15 can be improved. In addition, other aspects are the same as those in the fifth embodiment, so the detailed description is omitted.

[0110] In this case, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are also arranged to be above the upper surface of the terminal 17 of the insulating circuit substrate 15, so that the heat generated in the semiconductor element 4 can be efficiently conducted to the outside of the sealing resin 9 from the upper surface side of the semiconductor element 4, and the cooling efficiency can be improved. As a result, the reliability of the semiconductor device can be improved.

[0111] Fig.17 FIG. 2 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with a sixth embodiment of the present invention. Fig.17 In the embodiment, the semiconductor device 600 includes an insulating circuit substrate 15 as a circuit component, a solder 3 as a bonding material, a semiconductor element 4, a conductive spacer 5 as a connecting component, a resin insulating layer 6 as a resin layer, a main circuit conductive layer 7 as a first conductive layer, a control conductive layer 8 as a second conductive layer, a sealing resin 9 as a sealing component, an opening 10 as a first opening, a convex portion 13 of the resin insulating layer 6, a through hole 16 as a through hole, and a terminal 17 as a terminal portion. The thickness of the main circuit conductive layer 7 is thicker than that of the control conductive layer 8. In addition, the convex portion 13 is formed around the area of ​​the resin insulating layer 6 that is in contact with the semiconductor element 4.

[0112] The insulating circuit substrate 15 has metal layers 15c and 15b on both sides (front and back) of the insulating layer 15a. The insulating circuit substrate 15 has a through hole 16 that penetrates the insulating circuit substrate 15. A copper column or the like is inserted into the through hole 16 to connect the metal layer 15c and the metal layer 15b.

[0113] In this embodiment, if Fig.17As shown, the terminal 17 is joined to the metal layer 15c on the surface of the insulating circuit substrate 15 by the solder 3. Therefore, when the sealing resin 9 is molded, the insulating circuit substrate 15 is molded by clamping the terminal 17 with the mold so that the insulating circuit substrate 15 floats from the bottom surface inside the mold (the surface of the lower mold). The portion of the terminal 17 protruding into the mold is sealed inside the sealing resin 9 after being sealed with the sealing resin 9. The portion of the terminal 17 clamped by the mold protrudes from the inside of the sealing resin 9 to the outside after being sealed with the sealing resin 9. It is configured in a manner that the distance from the upper surface of the terminal 17 to the upper surface of the sealing resin 9 is smaller than the distance from the upper surface of the semiconductor element 4 to the upper surface of the sealing resin 9.

[0114] In addition, if Fig.17 As shown, the sealing resin 9 has the function of ensuring the insulation of the insulating circuit substrate 15 and the main circuit conductive layer 7 and the function of dissipating the heat from the semiconductor element 4 simultaneously with the function of the resin frame by including the entire semiconductor device 600. Therefore, the distance from the lower surface of the sealing resin 9 to the back side of the metal layer 15b of the insulating circuit substrate 15, that is, the thickness 14 of the sealing resin 9 on the back side of the metal layer 15b, and the distance from the upper surface of the main circuit conductive layer 7 to the upper surface of the sealing resin 9, that is, the thickness 14 of the sealing resin 9 on the upper side of the main circuit conductive layer 7, are preferably 0.1 mm or more and 1.0 mm or less from the viewpoint of the heat dissipation and insulation of the semiconductor device. When the thickness 14 is thinner than 0.1 mm, the insulation cannot be ensured. In addition, when the thickness 14 is thicker than 1.0 mm, the heat dissipation is sometimes deteriorated. Therefore, the range of the thickness 14 is preferably 0.1 mm or more and 1.0 mm or less.

[0115] In the semiconductor device 600 configured as described above, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are arranged above the upper surface of the terminal 17 of the insulating circuit substrate 15, so that the heat generated in the semiconductor element 4 can be efficiently conducted to the outside of the sealing resin 9 from the upper surface side of the semiconductor element 4, and the cooling efficiency can be improved. As a result, the reliability of the semiconductor device 600 can be improved.

[0116] Furthermore, by making the thickness of the main circuit conductive layer 7 bonded to the semiconductor element 4 thicker than the thickness of the control conductive layer 8 , it is possible to efficiently dissipate the heat from the semiconductor element 4 which generates a large amount of heat.

[0117] Furthermore, since the convex portion 13 is provided on the resin insulating layer 6 in contact with the outer periphery of the semiconductor element 4 , the insulation reliability of the semiconductor device 600 can be improved.

[0118] Implementation 7

[0119] In the present embodiment 7, the conductive spacer 5 used for connecting the lead frame 2 and the main circuit conductive layer 7 and the control conductive layer 8 used in the embodiment 1 is different in that it is provided as a protrusion 2c provided integrally with the lead frame 2. In this way, the protrusion 2c is provided on the lead frame 2, and the lead frame 2 and the main circuit conductive layer 7 and the control conductive layer 8 are connected using the protrusion 2c, so that the poor connection between the lead frame 2 and the main circuit conductive layer 7 and the control conductive layer 8 can be prevented. In addition, other aspects are the same as those in the embodiment 1, so the detailed description is omitted.

[0120] Fig.18 FIG. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor device in accordance with a seventh embodiment of the present invention.

[0121] In the figure, the semiconductor device 700 includes a heat conducting component 1, a lead frame 2 as a circuit component, a solder 3 as a bonding material, a semiconductor element 4, a conductive spacer 5 as a connecting component, a resin insulating layer 6 as a resin layer, a main circuit conductive layer 7 as a conductive layer (first conductive layer), a control conductive layer 8 as a conductive layer (second conductive layer), and a sealing resin 9 as a sealing component.

[0122] In addition, the lead frame 2 has a terminal portion 2a and a step portion (inclined portion) 2b as a terminal portion, and has a protrusion 2c. The protrusion 2c is used to electrically and thermally connect the lead frame 2 to the main circuit conductive layer 7 and the control conductive layer 8. When viewed in cross section and in a plan view, the area of ​​the protrusion 2c is larger than the area of ​​the opening 10 of the resin insulating layer 6 at the connection portion between the lead frame 2 and the main circuit conductive layer 7 and the control conductive layer 8. As a result, poor connection between the lead frame 2 and the main circuit conductive layer 7 and the control conductive layer 8 can be prevented.

[0123] Furthermore, the protrusion 2c can be formed by forging or the like in the process before or after the production of the lead frame 2 by punching. Alternatively, the protrusion 2c can be formed by making a part of the lead frame 2 thick and then thinning the thickness of the part other than the protrusion 2c by cutting or the like. When the protrusion 2c is produced by forging or cutting, if the thickness of the lead frame 2 is thin, it cannot withstand the processing by forging or cutting and cracks occur, so the thickness of the lead frame 2 is preferably 0.3 mm or more.

[0124] In the semiconductor device 700 configured as described above, the upper surfaces of the main circuit conductive layer 7 and the control conductive layer 8 are arranged above the upper surface of the terminal portion 2a of the lead frame 2, so that the heat generated in the semiconductor element 4 can be efficiently conducted to the outside of the sealing resin 9 from the upper surface side of the semiconductor element 4, and the cooling efficiency can be improved. As a result, the reliability of the semiconductor device 700 can be improved.

[0125] In addition, a protrusion 2c is integrally provided with the lead frame 2 so that the area of ​​the protrusion 2c is larger than the area of ​​the opening 10 of the connection portion between the lead frame 2 and the main circuit conductive layer 7 and the control conductive layer 8 of the resin insulating layer 6, thereby preventing poor connection between the lead frame 2 and the main circuit conductive layer 7 and the control conductive layer 8.

[0126] Implementation method 8.

[0127] Embodiment 8 is an embodiment in which the semiconductor devices according to Embodiments 1 to 7 are applied to a power converter. The present invention is not limited to a specific power converter, but the following describes a case in which the present invention is applied to a three-phase inverter as Embodiment 8.

[0128] Fig.19 This is a block diagram showing the configuration of a power conversion system to which a power conversion device according to Embodiment 8 of the present invention is applied.

[0129] Fig.19 The power conversion system shown includes a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a DC power supply, and supplies DC power to the power conversion device 2000. The power supply 1000 can be composed of various power supplies, for example, it can be composed of a DC system, a solar cell, a storage battery, or a rectifier circuit connected to an AC system, an AC / DC converter, etc. In addition, the power supply 1000 can also be composed of a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

[0130] The power conversion device 2000 is a three-phase inverter connected between the power source 1000 and the load 3000, which converts the DC power supplied from the power source 1000 into AC power and supplies the AC power to the load 3000. Fig.19 The main converter 2001 is provided with: a main converter circuit 2001 that converts DC power input from a power source 1000 into AC power for output; and a control circuit 2003 that outputs a control signal for controlling the main converter circuit 2001 to the main converter circuit 2001 .

[0131] The load 3000 is a three-phase motor driven by the AC power supplied from the power conversion device 2000. The load 3000 is not limited to a specific use, and is a motor mounted on various electrical devices, for example, used as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0132] The power conversion device 2000 is described in detail below. The main conversion circuit 2001 includes a switch element and a freewheeling diode (not shown) built into a semiconductor device 2002. The DC power supplied from the power supply 1000 is converted into AC power by switching the switch element, and is supplied to the load 3000. There are various examples of the specific circuit structure of the main conversion circuit 2001, but the main conversion circuit 2001 of this embodiment is a 2-level three-phase full-bridge circuit, which can be composed of 6 switch elements and 6 freewheeling diodes connected in anti-parallel with each switch element. The main conversion circuit 2001 is composed of a semiconductor device 2002 corresponding to any of the above-mentioned embodiments 1 to 5, which has each switch element, each freewheeling diode, etc. built in. With respect to the 6 switch elements, upper and lower branches are formed for every 2 switch elements connected in series, and each upper and lower branch constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminal of each upper and lower branch, that is, the three output terminals of the main conversion circuit 2001, is connected to the load 3000.

[0133] In addition, the main conversion circuit 2001 is provided with a driving circuit (not shown) for driving each switching element. The driving circuit may be built into the semiconductor module 2002, or may be a structure that has the driving circuit independently of the semiconductor module 2002. The driving circuit generates a driving signal for driving the switching element of the main conversion circuit 2001, and supplies it to the control electrode of the switching element of the main conversion circuit 2001. Specifically, according to the control signal from the control circuit 2003 described later, a driving signal for turning the switching element into a conducting state and a driving signal for turning the switching element into a cut-off state are output to the control electrode of each switching element. When the switching element is maintained in the conducting state, the driving signal is a voltage signal (conduction signal) above the threshold voltage of the switching element, and when the switching element is maintained in the cut-off state, the driving signal becomes a voltage signal (cut-off signal) below the threshold voltage of the switching element.

[0134] The control circuit 2003 controls the switch elements of the main conversion circuit 2001 in such a manner that the desired power is supplied to the load 3000. Specifically, the time (on-time) when each switch element of the main conversion circuit 2001 should be in the on state is calculated according to the power to be supplied to the load 3000. For example, the main conversion circuit 2001 can be controlled by PWM control that modulates the on-time of the switch element according to the voltage to be output. In addition, a control instruction (control signal) is output to the drive circuit of the main conversion circuit 2001 in such a manner that an on signal is output to the switch element that should be in the on state and an off signal is output to the switch element that should be in the off state at each time point. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switch element according to the control signal.

[0135] In the power conversion device according to the eighth embodiment configured as described above, the semiconductor device according to any of the first to seventh embodiments is applied as the semiconductor device 2002 of the main conversion circuit 2001 , so that reliability can be improved.

[0136] In this embodiment, an example of applying the present invention to a 2-level three-phase inverter is described, but the present invention is not limited thereto and can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is used, but a 3-level or multi-level power conversion device may also be used. When power is supplied to a single-phase load, the present invention may also be applied to a single-phase inverter. In addition, when power is supplied to a DC load, the present invention may also be applied to a DC / DC converter or an AC / DC converter.

[0137] In addition, the application of the power conversion device of the present invention is not limited to the case where the above-mentioned load is an electric motor. For example, it can be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system.

[0138] The above embodiments should be considered to be illustrative and non-restrictive in all aspects. The scope of the present invention is not shown by the scope of the above embodiments but by the claims, including all changes within the meaning and scope equivalent to the claims. In addition, the invention can also be formed by appropriately combining multiple constituent elements disclosed in the above embodiments.

Claims

1. A semiconductor device comprising: A circuit component having a front surface and a back surface, and having a planar portion; a terminal portion formed above the surface of the planar portion of the circuit component and parallel to the planar portion; a semiconductor element, the upper surface of which is located below the upper surface of the terminal portion, and is formed on the surface of the planar portion of the circuit component; a resin layer disposed on the semiconductor element and having a plurality of first openings through which the semiconductor element and a connecting member are exposed, the connecting member being disposed on the planar portion of the circuit member where the semiconductor element is not disposed and being at the same height as the semiconductor element; A conductive layer, arranged on the resin layer, with the entire upper surface being located above the upper surface of the terminal portion, joined to the semiconductor element at the plurality of first openings, and connected to the connection member exposed from the plurality of first openings where the semiconductor element is not exposed; as well as a sealing member having an upper surface parallel to the planar portion and integrally sealing the circuit member, the semiconductor element, the resin layer, the conductive layer, and a portion of the terminal portion; When the circuit component is a lead frame, the bottom of the connection component is connected to the terminal portion via the flat portion and the inclined portion of the circuit component where the semiconductor element is not arranged, or When the circuit component is an insulating circuit substrate having metal layers on the front and back surfaces of an insulating layer, the terminal portion is connected via the planar portion of the circuit component where the semiconductor element is not arranged.

2. The semiconductor device according to claim 1, in, The resin layer has a second opening that opens to include a region other than a region where the semiconductor element is arranged on the surface of the circuit component in a plan view and is filled with the sealing member.

3. The semiconductor device according to claim 1 or 2, in, The thickness of the resin layer on the outer periphery of the semiconductor element is thicker than the thickness of the resin layer outside the outer periphery of the semiconductor element.

4. The semiconductor device according to claim 1, in, The connection component is provided integrally with the circuit component.

5. The semiconductor device according to claim 1, 2 or 4, in, The conductive layer includes a first conductive layer bonded to a main electrode of the semiconductor element and a second conductive layer bonded to a control electrode of the semiconductor element, and the first conductive layer is thicker than the second conductive layer.

6. The semiconductor device according to claim 1, in, A heat conducting member is provided on the rear surface of the circuit member, and a lower surface of the heat conducting member is exposed from the sealing member.

7. The semiconductor device according to claim 5, in, The sealing member includes a filler including at least one of a metal oxide and a nitride.

8. The semiconductor device according to claim 7, in, A distance from an upper surface of the sealing member to an upper surface of the first conductive layer and a distance from a lower surface of the sealing member to a rear surface of the circuit member are 0.1 mm or more and 1 mm or less.

9. The semiconductor device according to claim 1, in, The insulating layer of the insulating circuit substrate includes a through hole for electrically connecting a metal layer on a surface of the insulating layer and a metal layer on a back surface of the insulating layer.

10. The semiconductor device according to any one of claims 1, 2, 4, 6 to 9, in, A cooler is provided on at least one of the upper surface and the lower surface of the sealing member.

11. A power conversion device comprising: A main conversion circuit, comprising the semiconductor device according to any one of claims 1 to 10, the main conversion circuit converting input power and outputting the power; and The control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

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