Memory controller and operating method thereof

Abstract

Provided herein may be a memory controller and an operation method thereof. The memory controller may be configured to control a memory device and includes: a request counter configured to generate a count value by counting the number of requests received from a host, and when the count value matches a preset reference value, calculate an arrival time period, the arrival time period being a time period between a time point when the count value is generated and a time point when the count value matches the reference value; a power mode setting component configured to determine an optimal power mode corresponding to the memory device and the memory controller based on the arrival time period; and a command controller configured to determine a time point for outputting a command for performing an operation corresponding to a corresponding request based on the optimal power mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims the benefit of Korean Patent Application No. 10-2019-0055275, filed on May 10, 2019, which is hereby incorporated by reference in its entirety for all purposes. Technical Field

[0003] Various embodiments of the present disclosure relate generally to electronic devices, and more particularly, to a memory controller and a method of operating a memory controller. Background Art

[0004] Generally, a storage device is a device that stores data under the control of a host device such as a computer, a smartphone, or a smart board. Depending on the type of device provided for storing data, examples of storage devices can be divided into devices that store data on a disk such as a hard disk drive (HDD), a solid-state drive (SSD), or a memory card that stores data in a semiconductor memory (particularly a nonvolatile memory).

[0005] The storage device may include a memory device in which data is stored and a memory controller configured to process or operate the stored data or data to be stored in the memory device. The memory device may be divided into a volatile memory and a non-volatile memory. By way of non-limiting example, representative examples of non-volatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FRAM). Summary of the invention

[0006] Various embodiments of the present disclosure are directed to a memory controller and method of operating a memory controller in which commands may be delayed based on power consumption limitations of a memory device.

[0007] One embodiment of the present disclosure may provide a computer memory storage device having a memory device having computer executable instructions embedded therein, and having a memory controller, which, when executing a command to control the memory device, performs a method for reducing computer processing time by increasing the power consumed by the memory device and the memory controller that is executing the command, the computer memory storage device comprising: a memory controller circuit having a request counter to count the number of requests received from a host and calculate an arrival time period when the number of requests matches a preset reference value; a power mode setting circuit configured to use the arrival time period to select a maximum power mode for the memory device and the memory controller from a plurality of power modes; and a command controller having a restricted power management table including a plurality of power modes and determining a delay time period for executing one or more received requests, wherein the arrival time period is a time period between a time point from when counting is started to a time point when the number of requests matches a reference value, and wherein the computer memory storage device minimizes the amount of time to process the received requests in the selected power mode.

[0008] One embodiment of the present disclosure may provide a computer memory storage device having a memory device having computer executable instructions embedded therein, and having a memory controller, which, when executing a command to control the memory device, performs a method for reducing computer processing time by increasing the power consumed by the memory device and the memory controller that is executing the command, the computer memory storage device comprising: the memory controller, comprising: a power mode setting component, configured to receive a power mode setting request from a host for determining an optimal power mode for the memory device and the memory controller, and determine the optimal power mode based on the power mode setting request; and a command controller, configured to determine a time point for outputting a command for performing an operation corresponding to a corresponding request received from the host to the memory device based on the optimal power mode.

[0009] One embodiment of the present disclosure may provide a method of operating a memory controller configured to control a memory device, the method comprising: receiving a request from a host; generating a count value by counting the number of requests received from the host; calculating an arrival time period, the expiration time period being a time period between a time point at which the count value is generated and a time point at which the count value matches a preset reference value; determining a highest power mode corresponding to a memory device and a memory controller among a plurality of power modes based on the arrival time period; and increasing power consumption to the highest power mode, which is allowed to perform operations corresponding to corresponding requests received from the host to the memory device, wherein the computer memory storage device minimizes the amount of time to process the received request in the selected power mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 The present invention is shown in Figure 1 A block diagram of the structure of a memory device.

[0012] Figure 3 The present invention is shown in Figure 1 Schematic diagram of multiple dies included in a memory device.

[0013] Figure 4 It is shown Figure 1 A diagram of an embodiment of a configuration of a memory controller.

[0014] Figure 5 It is shown Figure 1 A diagram of an embodiment of a configuration of a memory controller.

[0015] Figure 6 is a diagram showing the embodiment of the present disclosure. Figure 4 and Figure 5 Schematic diagram of a power mode table included in a power mode setting circuit of FIG.

[0016] Figure 7 The present invention is shown in Figure 4 and Figure 5 A diagram of the configuration of a command controller.

[0017] Figure 8 The present invention is shown in Figure 7 An illustration of the power consumption limits included in the power management table.

[0018] Figure 9A-9C is a diagram illustrating a breakdown of power consumption required to execute commands according to an embodiment of the present disclosure.

[0019] Fig. 10A and Fig. 10B is a diagram illustrating power consumption required to execute a command in an intermediate power mode according to an embodiment of the present disclosure.

[0020] Fig.11A and Fig. 11B The present invention is shown in Fig. 10B Graph showing power consumption when commands in are delayed.

[0021] Fig. 12A and Fig. 12B The present invention is shown in Fig. 10A A graph of the power consumption when commands are delayed.

[0022] Fig.13 The present invention is shown in Fig. 10A and Fig. 10B Graph of peak power consumption when commands in are delayed.

[0023] Figure 14A-Figure 14C is a diagram illustrating a delay of a command when total power consumption exceeds a power consumption limit according to an embodiment of the present disclosure.

[0024] Fig.15 is a diagram for describing the operation of a memory controller according to an embodiment of the present disclosure.

[0025] Fig.16 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0026] Fig.17 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0027] Fig.18 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0028] Fig.19 The present invention is shown in Figure 1 A diagram of an example of a memory controller.

[0029] Fig. 20 is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0030] Fig.21 is a block diagram illustrating a solid state drive (SSD) system using a storage device according to an embodiment of the present disclosure.

[0031] Fig. 22 is a block diagram illustrating a user system using a storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The specific structural or functional descriptions of the embodiments of the present disclosure introduced in this specification or application are only used to illustrate the embodiments of the present disclosure. These descriptions should not be interpreted as limiting the embodiments described in the specification or application.

[0033] The present disclosure will now be described in detail based on the embodiments. However, the present disclosure can be embodied in a variety of different forms and should not be interpreted as being limited to the embodiments described herein, but should be interpreted as covering modifications, equivalents or substitutions that fall within the thought and technical scope of the present disclosure. However, it should be understood that this specification is not used to limit the present disclosure to those exemplary embodiments, and the present disclosure not only covers the exemplary embodiments, but also includes various substitutions, modifications, equivalents and other embodiments that fall within the spirit and scope of the present disclosure.

[0034] It should be understood that although the terms "first", "second", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0035] It should be understood that when an element is referred to as being "coupled" or "connected" to another element, it can be directly coupled or connected to the other element, or there can be an intermediate element between them. Conversely, it should be understood that when an element is referred to as being "directly coupled" or "directly connected" to another element, there are no intermediate elements. Other expressions that explain the relationship between elements (such as "between," "directly between," "adjacent," or "directly adjacent") should be interpreted in the same manner.

[0036] The terms used herein are only used to describe specific embodiments and are not intended to be limiting. In the present disclosure, unless the context clearly indicates otherwise, the singular also includes the plural. It will be further understood that the terms "including", "having", etc., when used in the specification, specify the presence of the mentioned features, integers, steps, operations, elements, parts and / or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or combinations thereof.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that the terms used herein should be interpreted as having the same meaning as in the context of this specification and the relevant art, and should not be interpreted as idealized or overly formal unless explicitly defined herein.

[0038] Detailed description of functions and structures known to those skilled in the art will be omitted to avoid confusing the subject matter of the present disclosure. The purpose is to omit unnecessary description to make the subject matter of the present disclosure clear.

[0039] Various embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings showing preferred embodiments of the present disclosure, so that those skilled in the art can easily realize the technical idea of ​​the present disclosure.

[0040] Figure 1 is a block diagram illustrating a storage device 50 according to an embodiment of the present disclosure.

[0041] Reference Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 .

[0042] The storage device 50 may be a device configured to store data under the control of the host 300. Non-limiting examples of the device include cellular phones, smart phones, MP3 players, notebook computers, desktop computers, game consoles, TVs, tablet PCs, and in-vehicle infotainment systems.

[0043] The storage device 50 may be manufactured as any of various storage devices according to a host interface as a communication system communicating with the host 300. For example, the storage device 50 may be configured as any of various storage devices such as an SSD, a multimedia card (MMC), an embedded multimedia card (eMMC), a reduced size multimedia card (RS-MMC), a micro MMC type multimedia card, a secure digital card (SD), a mini SD, a micro SD type card, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a PCI express (PCI-E) type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0044] The memory device 50 may be manufactured in the form of any of a variety of package types, such as a package-on-package (POP) type, a system-in-package (SIP) type, a system-on-chip (SOC) type, a multi-chip package (MCP) type, a chip-on-board (COB) type, a wafer-level fabrication package (WFP) type, and a wafer-level stacked package (WSP) type.

[0045] The memory controller 200 may control operations of the memory device 50 .

[0046] When power is applied to the memory device 50, the memory controller 200 may execute firmware (FW). In the case where the memory device 100 is a flash memory device, the memory controller 200 may execute firmware such as a flash translation layer (FTL) for controlling communication between the host 300 and the memory device 100.

[0047] In one embodiment, the memory controller 200 may include a request counter 210. The request counter 210 may count requests received from the host 300. For example, the number of times a request is received may be counted or incremented each time a request is received from the host 300. Each request received from the host 300 may be any one of a program request, a read request, and an erase request.

[0048] The request counter 210 may generate a count value by counting the number of requests received from the host 300. The request counter 210 may increase the count value by "1" each time a request is received from the host 300. In this example, the request counter 210 counts the number of requests by incrementing the count value each time a request is received from the host 300 until the count value reaches a reference value.

[0049] When the count value matches the reference value, the request counter 210 may calculate an arrival time period. The arrival time period may be a time period from the time point when the host 300 receives the first request to the time point when the count value matches the reference value. The optimal power to be consumed by the memory device 100 and the memory controller 200 may be determined based on the arrival time period.

[0050] In one embodiment, the memory controller 200 may include a power mode setting circuit 220 having circuits. The power mode setting circuit 220 may determine an optimal power mode for the memory device 100 and the memory controller 200 from a plurality of power modes using the arrival time period. The plurality of power modes may be power modes used to determine power consumption limits of the memory device 100 and the memory controller 200. For example, the power mode setting circuit 220 may determine an optimal power mode in which the memory device 100 and the memory controller 200 may operate optimally. In another example, the power mode setting circuit 220 may determine a peak power consumption mode indicating a maximum power that may be consumed in the memory device 100 and the memory controller 200.

[0051] In one embodiment, the memory controller 200 may include a command controller 230. The command controller 230 may receive a request from the host 300. The command controller 230 may output a command CMD for performing an operation corresponding to the request received from the host 300 to the memory device 100.

[0052] The command controller 230 may determine a time point to output commands based on the power mode. These commands may indicate the performance of an operation corresponding to a corresponding request received from the host 300. In other words, the command controller 230 may determine a time point to output a command for performing an operation corresponding to a corresponding request received from the host.

[0053] The memory device 100 may store data therein. The memory device 100 may operate under the control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells configured to store data therein. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. Each memory block may include a plurality of pages. In one embodiment, each page may be a unit for storing data in the memory device 100 or reading stored data from the memory device 100. Each memory block may also be a unit for erasing data.

[0054] In one embodiment, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphic double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory device, a resistive random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), or a spin transfer torque random access memory (STT-RAM). In this specification, for ease of explanation, it is assumed that the memory device 100 is a NAND flash memory.

[0055] In one embodiment, the memory device 100 may be implemented as a three-dimensional array structure, such as a flash memory. The present disclosure may be applied to a flash memory having a charge storage layer formed by a conductive floating gate (FG) and a charge trap flash memory (CTF) having a charge storage layer formed by an insulating layer.

[0056] In one embodiment, each memory cell included in the memory device 100 may be formed of a single-level cell (SLC) capable of storing one data bit. Alternatively, each memory cell included in the memory device 100 may be formed of a multi-level cell (MLC) capable of storing two data bits, a triple-level cell (TLC) capable of storing three data bits, or a quad-level cell (QLC) capable of storing four data bits.

[0057] The memory device 100 can receive a command and an address from the memory controller 200 and access an area of ​​the memory cell array selected by the address. In other words, the memory device 100 can perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 can perform a write (program) operation, a read operation, and an erase operation. During a programming operation, the memory device 100 can program data to an area selected by an address. During a read operation, the memory device 100 can read data from an area selected by an address. During an erase operation, the memory device 100 can erase data from an area selected by an address.

[0058] Under the control of the memory controller 200 , the memory device 100 may perform a program operation or an erase operation using a set or predetermined operating voltage.

[0059] In one embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 300, and convert the LBA into a physical block address (PBA) indicating an address of a memory cell in the memory device 100 where the data is to be stored. In addition, the memory controller 200 may store mapping information indicating a mapping relationship between the LBA and the PBA in a buffer memory.

[0060] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request from the host 300. During a program operation, the memory controller 200 may provide a program command, a PBA, and data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and a PBA to the memory device 100.

[0061] In one embodiment, the memory controller 200 may autonomously or automatically generate a program command, address, and data without receiving a request from the host 300, and send the command, address, and related data to the memory device 100. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0062] In one embodiment, the memory controller 200 may control at least two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 in an interleaved or alternating manner in order to improve operation performance.

[0063] The host 300 may communicate with the storage device 50 using at least one of various communication methods, such as universal serial bus (USB), serial AT attachment (SATA), serial attached SCSI (SAS), high-speed inter-chip (HSIC), small computer system interface (SCSI), peripheral component interconnect (PCI), PCI Express (PCIe), non-volatile memory express (NVMe), universal flash memory (UFS), secure digital (SD), multimedia card (MMC), embedded MMC (eMMC), dual in-line memory module (DIMM), registered DIMM (RDIMM) and load-reduced DIMM (LRDIMM) communication methods.

[0064] Figure 2 The present invention is shown in Figure 1 Block diagram of the structure of a memory device

[0065] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 125 .

[0066] The memory cell array 110 may include a plurality of memory blocks BLK1-BLKz. The memory blocks BLK1-BLKz are connected to the address decoder 121 through the row lines RL, and are connected to the read / write circuit 123 through the bit lines BL1-BLm. Each memory block BLK1-BLKz may include a plurality of memory cells. In one embodiment, the plurality of memory cells in the memory cell array 110 may be a plurality of nonvolatile memory cells.

[0067] Memory cells included in the memory cell array 110 may be divided into a plurality of memory blocks according to intended applications. System information such as various setting information required to control the memory device 100 may be stored in the plurality of memory blocks.

[0068] Each of the first to z-th memory blocks BLK1-BLKz includes a plurality of memory cell strings (not shown). The first to m-th memory cell strings are coupled to the first to m-th bit lines BL1-BLm, respectively. Each of the first to m-th memory cell strings includes a drain select transistor, a plurality of memory cells coupled in series with each other, and a source select transistor. The drain select transistor DST is coupled to the drain select line DSL.

[0069] The first to nth memory cells (not shown) of the memory cell array 110 are coupled to the first to nth word lines, respectively. The source select transistor SST is coupled to the source select line SSL. The drain of the drain select transistor DST is coupled to the corresponding bit line. The drain select transistors DST of the first to mth cell strings are coupled to the first to mth bit lines BL1-BLm, respectively. The source of the source select transistor SST is coupled to the common source line CSL.

[0070] In one embodiment, a common source line CSL may be commonly coupled to the first to z-th memory blocks BLK1-BLKz. A drain selection line DSL, first to n-th word lines WL1-WLn, and a source selection line SSL are included in a row line RL. The drain selection line DSL, the first to n-th word lines WL1-WLn, and the source selection line SSL are controlled by an address decoder 121. The common source line CSL is controlled by a control logic 125. The first to m-th bit lines BL1-BLm are controlled by a read / write circuit 123.

[0071] The peripheral circuit 120 may include an address decoder 121 , a voltage generator 122 , a read / write circuit 123 , and a data input / output circuit 124 .

[0072] The address decoder 121 is coupled to the memory cell array 110 through the row lines RL. The address decoder 121 may operate under the control of the control logic 125. The address decoder 121 receives the address ADDR through the control logic 125.

[0073] In one embodiment, program operations and read operations of the memory device 100 may be performed on a page basis.

[0074] During a programming operation or a read operation, the address ADDR received from the control logic 125 may include a block address and a row address. The address decoder 121 may decode the block address from the received address ADDR. The address decoder 121 may use or select a corresponding one of the memory blocks BLK1-BLKz based on the decoded block address. The address decoder 121 may decode the row address in the received address ADDR. In response to the decoded row address, the address decoder 121 may apply a voltage provided from the voltage generator 122 to the row line RL and select a word line of the selected memory block.

[0075] During an erase operation, the address ADDR may include a block address. The address decoder 121 may decode the block address and select a memory block according to the decoded block address. The erase operation may be performed on the entirety or a portion of a memory block. During a partial erase operation, the address ADDR may include a block address and a row address. The address decoder 121 may select a corresponding one of the memory blocks BLK1-BLKz in response to the decoded block address.

[0076] For example, the address decoder 121 may decode a row address in the received address ADDR. In response to the decoded row address, the address decoder 121 may apply a voltage provided from the voltage generator 122 to the row line RL and select at least one word line of the selected memory block.

[0077] In one embodiment, the address decoder 121 may include a block decoder, a word line decoder, an address buffer, etc.

[0078] The voltage generator 122 may generate a plurality of voltages using an external power supply voltage and provide the same to the memory device 100. The voltage generator 122 may operate under the control of the control logic 125.

[0079] In one embodiment, the voltage generator 122 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 may be used as an operating voltage of the memory device 100.

[0080] In one embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 122 may include a plurality of pumping capacitors for receiving the internal power supply voltage, and generate a plurality of voltages by selectively activating the plurality of pumping capacitors under the control of the control logic 125. The generated voltages are applied to the selected word line by the address decoder 121.

[0081] During a program operation, the voltage generator 122 may generate a program pulse having a high voltage and a pass pulse having a voltage level lower than the program pulse. During a read operation, the voltage generator 122 may generate a read voltage and a pass voltage higher than the read voltage. During an erase operation, the voltage generator 122 may generate an erase voltage.

[0082] The read / write circuit 123 may include first to mth page buffers PB1-PBm. The first to mth page buffers PB1-PBm are coupled to the memory cell array 110 through first to mth bit lines BL1-BLm, respectively. The first to mth page buffers PB1-PBm may operate under the control of the control logic 125.

[0083] The first to mth page buffers PB1-PBm may communicate data with the data input / output circuit 124. During a program operation, the first to mth page buffers PB1-PBm may receive data DATA to be stored through the data input / output circuit 124 and the data lines DL.

[0084] During a programming operation, when a programming pulse is applied to a selected word line, the first to mth page buffers PB1-PBm may transmit data received through the data input / output circuit 124 to the selected memory cells through the bit lines BL1-BLm. The memory cells in the selected page are programmed based on the transmitted data. The memory cells coupled to the bit lines to which a programming enable voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cells coupled to the bit lines to which a programming inhibition voltage (e.g., a power supply voltage) is applied may be retained. During a programming verification operation, the first to mth page buffers PB1-PBm may read page data from the selected memory cells through the bit lines BL1-BLm.

[0085] During a read operation, the read / write circuit 123 may read data from memory cells in a selected page through the bit lines BL and output the read data DATA to the data input / output circuit 124. During an erase operation, the read / write circuit 123 may float the bit lines BL.

[0086] In one embodiment, the read / write circuit 123 may include a column selection circuit.

[0087] The data input / output circuit 124 is coupled to the first to mth page buffers PB1-PBm through data lines DL. The data input / output circuit 124 may operate under the control of the control logic 125. During a program operation, the data input / output circuit 124 may receive data to be stored from an external controller (not shown).

[0088] The control logic 125 is connected to the address decoder 121, the voltage generator 122, the read / write circuit 123, and the data input / output circuit 124. The control logic 125 can control the overall operation of the memory device 100. The control logic 125 can receive a command CMD and an address ADDR from an external controller. The control logic 125 can control the address decoder 121, the voltage generator 122, the read / write circuit 123, and the data input / output circuit 124 in response to the command CMD.

[0089] Figure 3 The present invention is shown in Figure 1 Schematic diagram of multiple dies included in a memory device.

[0090] Reference Figure 3, the memory device 100 may include first to fourth dies DIE1-DIE4. The first to fourth dies DIE1-DIE4 may be coupled to the memory controller 200 through first to fourth channels CH1-CH4, respectively. Each of the first to fourth dies DIE1-DIE4 may include a plurality of planes. Each of the plurality of planes may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of pages.

[0091] Figure 3 The memory device 100 includes first to fourth dies DIE1 - DIE4 , but embodiments contemplated by the present disclosure are not limited thereto, and the number of dies included in the memory device 100 may be increased to a greater number.

[0092] In one embodiment, the memory device 100 may include a plurality of dies. Operations may be independently performed in each of the plurality of dies. The memory controller 200 may independently control the corresponding operations performed in the first to fourth dies DIE1-DIE4 through channels CH1-CH4.

[0093] For example, the memory controller 200 may control the first die DIE1 through the first channel CH1, the second die DIE2 through the second channel CH2, the third die DIE3 through the third channel CH3, and the fourth die DIE4 through the fourth channel CH4. Therefore, the memory controller 200 may output a command CMD, an address, and data to each of the first to fourth dies DIE1-DIE4 through its corresponding channel so as to perform an operation on a corresponding one of the first to fourth dies DIE1-DIE4. Based on the command CMD, address, and data received through the corresponding one of the first to fourth channels CH1-CH4, an operation may be performed on each of the first to fourth dies DIE1-DIE4. The operation performed on each of the first to fourth dies DIE1-DIE4 may be a programming (writing) operation, a reading operation, or an erasing operation. The data of the first to fourth dies DIE1-DIE4 may be transmitted to the memory controller 200 through the first to fourth channels CH1-CH4, respectively.

[0094] Power consumption may be controlled in operations performed on a plurality of dies under the control of the memory controller 200. The limit power consumption (LPC) is the peak power consumption in the memory device 100 and the memory controller 200, and may be preset or predetermined.

[0095] The power consumption used when performing operations on the first to fourth dies DIE1-DIE4 cannot exceed the LPC. Therefore, the operations performed in the first to fourth dies DIE1-DIE4 cannot be performed in a state exceeding the LPC.

[0096] In conventional technology, the power consumed in multiple dies is kept below a predetermined level without exceeding the LPC, so that the stability of the storage device can be ensured. In other words, although the LPC of the storage device can be set to a higher level, the LPC is fixed in order to ensure the stability of the storage device. Since the LPC is fixed, the power consumption of the storage device may not increase to the LPC or more. In other words, in order to keep the LPC relatively low in the case of high power consumption by the user, the time spent on performing the operation may be increased. Therefore, it is necessary to change the LPC according to the user's power usage or consumption pattern.

[0097] Various embodiments of the present disclosure may provide a method of determining LPC of the memory device 100 and the memory controller 200 based on power consumption of a user and a method of determining whether to delay a command CMD for a period of time when power consumption of the memory device 100 and the memory controller 200 exceeds the LPC.

[0098] According to the present disclosure, unlike the prior art, the LPC is determined by the power consumption pattern of the user. Therefore, the LPC may be higher or lower than the conventional LPC. In addition, by performing an operation with a higher LPC, the storage device may perform an operation corresponding to a command faster than before, and by performing an operation with a lower LPC, the storage device may perform an operation corresponding to a command more stably than before.

[0099] Figure 4 It is shown Figure 1 A diagram of an embodiment of a configuration of a memory controller.

[0100] Reference Figure 4 , the memory controller 200 may include a request counter 210 , a power mode setting circuit 220 , and a command controller 230 .

[0101] The request counter 210 may count requests received from the host 300. The request received from the host 300 may be a program (write) request, a read request, or an erase request. The request counter 210 may count requests received from the host 300 and generate a count value. The count value may be a cumulative value.

[0102] In one embodiment, the request counter 210 may receive a plurality of requests from the host 300. Therefore, each time a request is received from the host 300, the request counter 210 may generate a count value that increases by "1".

[0103] In detail, before receiving a request from the host 300, the count value may be initialized to "0" as a default value. Subsequently, if the request counter 210 receives a request from the host 300, the request counter 210 may count the requests received from the host 300 and generate a count value of "1". If the request counter 210 receives a request from the host 300 again, the request counter 210 may increase the count value by "1" to generate a count value of "2".

[0104] The request counter 210 may include a preset reference value. The preset reference value may be a value used to determine the power consumption mode of the user. For example, the time point at which the count value counted by the request counter 210 matches the preset reference value may be different depending on the power usage of the user. In other words, the arrival time period (the time period from the time point at which the count value is generated to the time point at which the count value matches the preset reference value) may change according to the power usage of a specific user.

[0105] Since the arrival period ARV_PERIOD varies according to the power consumption of the user, it is necessary to set the LPC of the memory device 100 and the memory controller 200 to different values ​​for different users. Therefore, the arrival period ARV_PERIOD may refer to the power consumption mode of the user. In other words, in the case where the user has a short arrival period ARV_PERIOD, the power consumption of the user may be relatively high. On the contrary, in the case where the user has a long arrival period ARV_PERIOD, the power consumption of the user may be relatively low. Therefore, it is necessary to set the LPC of the user with the short arrival period ARV_PERIOD to a large value, and set the LPC of the user with the long arrival period ARV_PERIOD to a small value.

[0106] If the count value counted by the request counter 210 matches the preset reference value, the request counter 210 may calculate or output the arrival time period ARV_PERIOD. The arrival time period ARV_PERIOD may be a time period from the time point when the count value is generated to the time point when the count value matches the reference value. The request counter 210 may provide the calculated arrival time period ARV_PERIOD to the power mode setting circuit 220.

[0107] The power mode setting circuit 220 may determine the power mode of the memory device 100 and the memory controller 200 based on the arrival time period ARV_PERIOD. In detail, the power mode setting circuit 220 may receive the arrival time period ARV_PERIOD from the request counter 210. The power mode setting circuit 220 may determine the power mode corresponding to the arrival time period ARV_PERIOD for the memory device 100 and the memory controller 200.

[0108] The power mode setting circuit 220 may include a power mode table storing an arrival time period ARV_PERIOD corresponding to a corresponding power mode and an LPC corresponding to the peak power consumption of the memory device 100 and the memory controller 200. The power mode determined by the power mode setting circuit 220 may be any one of a plurality of power modes included in the power mode table. As an example, the power mode setting circuit 220 may determine that a power mode in a section corresponding to the arrival time period ARV_PERIOD received from the request counter 210 is an optimal power mode for the memory device 100 and the memory controller 200.

[0109] Based on the power mode, an LPC corresponding to the peak power consumption of the memory device 100 and the memory controller 200 may be determined.

[0110] In one embodiment, when the arrival time period ARV_PERIOD is relatively long, the power mode setting circuit 220 may determine that the power mode corresponding to the lower power consumption is the optimal power mode of the memory device 100 and the memory controller 200, and determine the appropriate LPC. On the contrary, when the arrival time period ARV_PERIOD is relatively short or reduced, the power mode setting circuit 220 may determine that the power mode reflecting the higher power consumption is the optimal power mode of the memory device 100 and the memory controller 200, and determine the appropriate LPC.

[0111] The power mode setting circuit 220 may determine the power modes of the memory device 100 and the memory controller 200 and then provide power mode setting information PMSET_INF to the command controller 230. The power mode setting information PMSET_INF may include information about the power mode determined by the power mode setting circuit 220.

[0112] The command controller 230 may output a command CMD based on the power mode setting information PMSET_INF. In one example, the command controller 230 may receive a request from the host 300 and output a command CMD for performing an operation corresponding to the request to the memory device 100. In this case, the command controller 230 may determine whether to delay the command output time point by a delay time.

[0113] In one embodiment, power may be consumed to perform an operation corresponding to a request received from the host 300. The request received from the host 300 may be a request for any one of a plurality of dies included in the memory device 100, or a request for at least two or more of the plurality of dies. As the number of requests received from the host 300 increases, power consumption may increase.

[0114] The command controller 230 may determine the LPC of the memory device 100 and the memory controller 200 based on the power mode setting information PMSET_INF. In other words, the command controller 230 may determine the LPC corresponding to the power mode for each command or operation.

[0115] Once the LPC is determined, the command controller 230 may sum the power consumption required to perform the operation corresponding to the request received from the host 300. In other words, the command controller 230 may sum the power consumption required for the memory device 100 to execute a plurality of commands. The value obtained by summing the power consumption required for the memory device 100 to execute the commands may correspond to the summed power consumption.

[0116] The command controller 230 may determine the output time point of the command CMD by comparing the summed power consumption with the LPC, that is, whether to delay the command CMD for a delay time. If the summed power consumption is equal to or less than the LPC, the command controller 230 may not delay these commands. However, if the summed power consumption is greater than the LPC, any command to be executed on the memory device 100 may be delayed. The delay time of the command may be a minimum time period that makes the summed power consumption not exceed the LPC.

[0117] The following will refer to Figure 7 The configuration of the command controller 230 and the operation of determining whether to delay the command CMD for a delay time are described in more detail.

[0118] Figure 5 It is shown Figure 1 2 is a diagram of an embodiment of a configuration of a memory controller 200.

[0119] refer to Figure 4 and Figure 5 , the memory controller 200 may include a power mode setting circuit 220 and a command controller 230. For clarity, Figure 5 The request counter 210 is omitted from the components of the memory controller 200 shown.

[0120] The power mode setting circuit 220 may receive a power mode setting request PMSET_REQ from the host 300. The power mode setting request PMSET_REQ may be a request for setting a power mode of the memory device 100 and the memory controller 200.

[0121] The power modes of the memory device 100 and the memory controller 200 may be set in response to a power mode setting request PMSET_REQ from the host 300. In other words, regardless of Figure 4Regardless of the arrival time period ARV_PERIOD, the power mode of the memory device 100 and the memory controller 200 can be set in response to the power mode setting request PMSET_REQ of the host 300. According to the power mode, the peak power consumption indicating the maximum power that can be consumed in the memory device 100 and the memory controller 200 can be determined.

[0122] In one embodiment, the power mode setting circuit 220 may include a power mode table storing information of power modes corresponding to respective arrival time periods. Figure 5 As shown, since the power mode can be determined in response to the power mode setting request PMSET_REQ of the host 300, the power mode setting circuit 220 can determine that the power mode (corresponding to the power mode setting request PMSET_REQ from the power mode table included in the host 300) is the optimal power mode for the memory device 100 and the memory controller 200 regardless of the arrival time period ARV_PERIOD.

[0123] In one embodiment, the power mode setting circuit 220 may receive a power mode setting request PMSET_REQ from the host 300 and set an optimal power mode. Based on the power mode set by the power mode setting circuit 220, the peak power consumption, ie, LPC, of ​​the memory device 100 and the memory controller 200 may be determined.

[0124] If the power mode is set in response to the power mode setting request PMSET_REQ from the host 300 , the power mode setting circuit 220 may provide the command controller 230 with power mode setting information PMSET_INF including information on the set power mode.

[0125] The command controller 230 may output a command CMD based on the power mode setting information PMSET_INF. For example, the command controller 230 may receive a request from the host 300 and output a command CMD for performing an operation corresponding to the request to the memory device 100. Here, the command controller 230 may determine whether to delay the command output time point for a period of time.

[0126] The operation of the command controller 230 may determine the LPC corresponding to the power mode based on the power mode setting information PMSET_INF. Thereafter, if the LPC is determined, the command controller 230 may determine whether to delay the command CMD for a period of time by comparing the LPC with the summed power consumption obtained by summing the power consumption required for the memory device 100 to execute a plurality of commands.

[0127] Figure 6 The present invention includes Figure 4and Figure 5 Schematic diagram of a power mode table in the power mode setting circuit 220.

[0128] refer to Figure 6 , the power mode setting circuit 220 may include a power mode table, such as the example table shown.

[0129] exist Figure 6 In the table of FIG. 21 , the first column indicates an arrival time period ARV_PERIOD. The arrival time period ARV_PERIOD may be a time period from a time point at which a count value counted by the request counter 210 is reset or generated to a time point at which the count value matches a reference value. The arrival time period ARV_PERIOD may be generated by the request counter 210 and provided to the power mode setting circuit 220.

[0130] Figure 6 The second column in indicates a power mode (“POWER MODE”). According to the power mode, a peak power consumption (PPC) indicating a maximum power that can be consumed in the memory device 100 and the memory controller 200 may be determined.

[0131] In one embodiment, the power mode table may include information about the power mode corresponding to the corresponding arrival time period. In other words, the arrival time period corresponds to the corresponding power mode, or the LPC as the peak power consumption of the memory device and the memory controller may be stored in the power mode table. Any power mode included in the power mode table may be determined as the optimal power mode for the memory device 100 and the memory controller 200.

[0132] By description and reference Figure 6 , the arrival time period ARV_PERIOD can be divided into three time periods, namely, below the threshold time period D1, between the threshold time periods D1 and D2, and above the threshold time period D2. In one embodiment, D1 can be one day and D2 can be ten days. In other embodiments, the number of sections included in the power mode table can be increased. In other words, the power mode setting circuit 220 can subdivide the arrival time period ARV_PERIOD into various time periods for determining the power mode.

[0133] Therefore, according to the section to which the arrival period ARV_PERIOD belongs, the power mode POWER MODE of the memory device 100 and the memory controller 200 may be determined.

[0134] In one embodiment, when the arrival period ARV_PERIOD is equal to or less than D1 (for example, ARV_PERIOD is equal to or less than one day), the power mode POWER MODE may be determined as the maximum power mode MAX_MODE. In other words, in "MAX_MODE", "the arrival period ARV_PERIOD is short" or similar expressions may indicate that the power consumption used by the user is relatively high. Therefore, in order to be able to execute a large number of commands to the memory device 100, the LPC may be set to a relatively high value. Therefore, when the arrival period ARV_PERIOD is short or shortened, the power mode setting circuit 220 may determine that the power mode for setting a higher power as the LPC is the optimal power mode for the memory device 100 and the memory controller 200.

[0135] In the case where the power mode setting circuit 220 sets the power mode to the maximum power mode MAX_MODE, the number of commands executed on the memory device 100 can be increased. In other words, the commands can be simultaneously executed on a plurality of dies included in the memory device 100. In addition, a large number of commands can be executed on the memory device 100 without delaying the commands.

[0136] In another embodiment, the arrival time period ARV_PERIOD is greater than the threshold time period D2 (e.g., ARV_PERIOD is greater than 10 days), and the power mode may be determined to be the minimum power mode MIN_MODE. In other words, the phrase "the arrival time period ARV_PERIOD is longer" or similar expressions may indicate that the power consumption used by the user is relatively low. Therefore, LPC may be set to a low value so that the number of commands to be executed on the memory device 100 is reduced. Thus, when the arrival time period ARV_PERIOD increases, the power mode setting circuit 220 may determine that the power mode for setting the lower power consumption as LPC is the optimal power mode for the memory device 100 and the memory controller 200.

[0137] In case the power mode setting circuit 220 sets the power mode to the minimum power mode MIN_MODE, commands may be executed only on some of the plurality of dies included in the memory device 100. In addition, commands to be executed on the memory device 100 may be delayed for a period of time.

[0138] In yet another embodiment, when the arrival time period ARV_PERIOD is greater than D1 and equal to or less than D2 (for example, ARV_PERIOD is greater than 1 day and equal to or less than 10 days), the power mode may be determined as the middle power mode MID_MODE. If the power mode is determined as the middle power mode MID_MODE, LPC may be set to a value greater than the minimum power mode MIN_MODE and less than the maximum power mode MAX_MODE.

[0139] In one embodiment, the number of segments or time period divisions included in the power mode table and the number of power modes corresponding to the corresponding segments can be changed. For example, the segment to which the arrival time period ARV_PERIOD belongs can be subdivided in various ways, and different divisions correspond to different POWER MODEs.

[0140] Figure 7 The present invention is shown in Figure 4 and Figure 5 2 is a diagram of a configuration of the command controller 230.

[0141] Reference Figure 7 , the command controller 230 may include a limit power management table 231 , a command delay determiner 233 , and a command output circuit 235 .

[0142] In one embodiment, the restricted power management table 231 may include information about the LPC. As an example, the restricted power management table 231 may include information about Figure 4 and Figure 5 The information about the LPC corresponding to the power mode (“POWER MODE”) determined by the power mode setting circuit 220 of the memory controller 200 may be included in the limit power management table 231 . The information about the LPC corresponding to the various power modes may be included in the limit power management table 231 .

[0143] The command delay determiner 233 may receive a request from the host 300. The request received from the host 300 may be a program request, a read request, or an erase request. The command delay determiner 233 may determine whether to delay a command CMD for performing an operation corresponding to the request. The command delay determiner 233 may determine whether to delay the command CMD based on the power mode and the LPC.

[0144] The command delay determiner 233 may receive power mode setting information PMSET_INF from the power mode setting circuit 220. The power mode setting information PMSET_INF may include information about a power mode determined by the power mode setting circuit 220. The power mode may determine a peak power consumption (PPC) of the memory device 100 and the memory controller 200.

[0145] In one example, the command delay determiner 233 may provide an LPC request LPC_REQ to the limit power management table 231 based on the power mode setting information PMSET_INF. The LPC may be the maximum power that may be consumed in the memory device 100 and the memory controller 200. The LPC corresponding to the power mode in the limit power management table 231 may be provided to the command delay determiner 233.

[0146] The command delay determiner 233 may generate delay information DELAY_INF regarding whether any one command is delayed and a time corresponding to the delay based on the LPC.

[0147] For example, the command delay determiner 233 may compare the LPC with the summed power consumption. The summed power consumption may be power consumption obtained by summing the maximum value of power consumption required to execute a plurality of commands or operation requests. The command delay determiner 233 may compare the LPC with the summed power consumption, thereby determining whether to delay at least one of the commands CMD.

[0148] In one embodiment, if the summed power consumption obtained by summing the peak power consumptions required to execute a plurality of commands is equal to or less than the LPC, the command delay determiner 233 may decide to execute all commands without delay. On the contrary, if the summed power consumption is greater than the LPC, the command delay determiner 233 may determine to delay at least one command.

[0149] In one embodiment, if the summed power consumption exceeds the LPC, at least one command may be delayed to prevent the summed power consumption from exceeding the LPC. Therefore, assuming that one command is delayed, the command delay determiner 233 may determine the order of commands corresponding to the summed power consumption to include the delay time. In addition, the command delay determiner 233 may adjust the order of commands corresponding to the summed power consumption to reflect the delay.

[0150] In one embodiment, if all the summed power consumption (including the power consumption associated with the delayed command) exceeds the LPC, the command delay determiner 233 may determine to delay another command. Subsequently, assuming that two commands are delayed, the command delay determiner 233 may determine the summed power consumption to include two delay times.

[0151] In one embodiment, if the summed power consumption (including power consumption associated with delaying commands) does not exceed the LPC, a minimum delay time that causes the summed power consumption to not exceed the LPC can be determined. In other words, the command can be executed as quickly as possible within a time range where the summed power consumption does not exceed the LPC, thereby increasing or optimizing the operating speed relative to the power consumption.

[0152] The command delay determiner 233 may generate delay information DEALY_INF. In the case where the command delay determiner 233 has determined not to delay the command, the command delay determiner 233 may generate delay information DELAY_INF indicating that the command is not to be delayed. On the other hand, if the delay determiner 233 has determined to delay at least one command, the command delay determiner 233 may generate delay information DELAY_INF including information about the delayed command and the corresponding delay time.

[0153] The command delay determiner 233 may provide delay information DELAY_INF to the command output circuit 235 .

[0154] The command output circuit 235 may output the command CMD to the memory device 100 based on the delay information DELAY_INF.

[0155] In the case where the delay information DELAY_INF includes information that the commands are not delayed, the command output circuit 235 may output the commands simultaneously. The commands output from the command output circuit 235 may be output to any one of the plurality of dies of the memory device 100 through a plurality of corresponding channels.

[0156] On the other hand, in the case where the delay information DELAY_INF includes information that the command is delayed and information about the delay time, the command output circuit 235 may delay any one of the commands and output the delayed command. That is, if the summed power consumption exceeds the LPC, when the memory device 100 simultaneously performs operations corresponding to a plurality of commands, the command output circuit 235 may sequentially delay any one of the commands.

[0157] Figure 8 It is shown that the Figure 7 FIG. 2 is a diagram of the LPC in the restricted power management table 231.

[0158] refer to Figure 8 , Figure 8 The first column in indicates a power mode (“POWER MODE”), and the second column indicates an LPC (“LIMIT POWER CONSUMPTION, LPC”). According to the power mode of the first column, a peak power consumption (PPC), i.e., an LPC indicating a maximum power that can be consumed in the memory device 100 and the memory controller 200, can be determined.

[0159] exist Figure 8 In the example, it is assumed that the first limit power consumption LPC1 is greater than the second limit power consumption LPC2, and the second limit power consumption LPC2 is greater than the third limit power consumption LPC3.

[0160] In one embodiment, the power mode may be any one of a maximum power mode MAX_MODE, an intermediate power mode MIN_MODE, and a minimum power mode MIN_MODE. The power mode may be determined according to an arrival time period ARV_PERIOD. When the count value counted by the request counter 210 matches a preset reference value, the arrival time period ARV_PERIOD may be calculated. The arrival time period ARV_PERIOD may be a time period between a time point at which a count value is generated and a time point at which the count value matches a reference value.

[0161] In one embodiment, the power mode can be Figure 6 In other embodiments, if the arrival time period ARV_PERIOD is further subdivided and the number of levels included in the power mode table is increased, the power mode may be any one of a plurality of power modes corresponding to a greater number of segments or levels.

[0162] In one embodiment, if the power mode is determined to be the maximum power mode MAX_MODE, the LPC may correspond to the first limited power consumption LPC1.

[0163] In one embodiment, if the result of the calculation of the arrival time period ARV_PERIOD indicates that the arrival time period ARV_PERIOD is relatively short, the power mode POWER MODE may be determined to correspond to the maximum power mode MAX_MODE. In this case, the peak power consumption (ie, LPC) of the memory device 100 and the memory controller 200 is set to a relatively high value.

[0164] The phrase "arrival time period ARV_PERIOD is short (or relatively short)" indicates that the power consumption of the memory device 100 and the memory controller 200 is relatively high. Therefore, in this case, it is necessary to set the LPC to a relatively high value. If the LPC is set to a high value, the power capacity in the memory device 100 and the memory controller 200 is increased. Therefore, the operation speed can be increased, and the time taken to execute an operation or a command can be reduced.

[0165] If the arrival time period is short, Figure 6 The power mode (“POWER MODE”) in the memory device 100 is determined to be the maximum power mode MAX_MODE. If the power mode is determined to be the maximum power mode MAX_MODE, the first limit power consumption LPC1 corresponding to the maximum power mode MAX_MODE may be set to LPC. Therefore, the memory device 100 and the memory controller 200 may consume power within a range defined by the first limit power consumption LPC1.

[0166] In one embodiment, if the power mode is determined to be the minimum power mode MIN_MODE, the LPC may be determined to be the third limited power consumption LPC3.

[0167] When the arrival period ("ARV_PERIOD") is calculated and determined to be long or relatively long (e.g., ARV_PERIOD is greater than 10 days), the corresponding power mode may be determined to be the minimum power mode MIN_MODE. In the case where the arrival period ARV_PERIOD is determined to be long, the peak power consumption (i.e., LPC) of the memory device 100 and the memory controller 200 needs to be set to a relatively low value.

[0168] The phrase "arrival time period ARV_PERIOD is long (or relatively long)" indicates that the power consumption of the memory device 100 and the memory controller 200 is relatively low. Therefore, in this case, it is necessary to set the LPC to a relatively low value. If the LPC is set to a low value, the power consumption of the memory device 100 and the memory controller 200 can be prevented from increasing rapidly, and can be operated in a low power mode, thereby enhancing the operational reliability thereof. If the LPC can be set to a relatively low value, the total power consumption may not increase or decrease rapidly. That is, the probability of erroneous operation due to excessive or insufficient power consumption can be reduced.

[0169] If the peak power consumption of the memory device 100 and the memory controller 200 needs to be set to a low value, the power mode can be determined as the minimum power mode MIN_MODE. If the power mode is determined to be the minimum power mode MIN_MODE, the third limited power consumption LPC3 corresponding to the minimum power mode MIN_MODE can be set to LPC. Therefore, the memory device 100 and the memory controller 200 can consume power within the range defined by the third limited power consumption LPC3.

[0170] In one embodiment, when the power mode is determined to be the middle power mode MID_MODE, the LPC may correspond to the second limited power consumption LPC2.

[0171] When the result of calculating the arrival time period ARV_PERIOD indicates that the arrival time period ARV_PERIOD is a time period included in a specific section (for example, ARV_PERIOD is greater than one day and equal to or less than ten days), the power mode ("POWERMODE") may be determined as the middle power mode MID_MODE. If the arrival time period ARV_PERIOD is determined to be a time period included in the specific section, the peak power consumption (ie, LPC) of the memory device 100 and the memory controller 200 is set to an intermediate value.

[0172] If the power mode is determined to be the middle power mode MID_MODE, the second limit power consumption LPC2 corresponding to the middle power mode MID_MODE may be set to LPC. In other words, if the power mode POWER MODE is the middle power mode MID_MODE, the second limit power consumption LPC2 (which is less than the first limit power consumption LPC1 corresponding to the maximum power mode MAX_MODE and greater than the third limit power consumption LPC3 corresponding to the minimum power mode MIN_MODE) may be determined to be LPC. Therefore, the memory device 100 and the memory controller 200 may consume power within the range defined by the second limit power consumption LPC2.

[0173] 9A to 9C is a diagram illustrating a breakdown of power consumption required to execute commands according to an embodiment of the present disclosure.

[0174] 9A to 9C The power consumption of commands of the storage device in different power modes is shown. Fig.9A shows the power consumption in a minimum power mode (such as MIN_MODE); Fig. 9B shows the power consumption in an intermediate power mode (such as MIN_MODE): and Fig. 9C The power consumption in a maximum power mode (such as MAX_MODE) is shown.

[0175] exist 9A to 9C In , the horizontal axis indicates the time to execute a command, and the vertical axis indicates the power consumption as a function of time. 9A to 9C In the example, power consumption can be the power consumption level within a period of time, or the total power consumption within a period of time.

[0176] In one embodiment, 9A to 9C The information reflected in the Figure 4 and Figure 5 For example, the best power mode for executing the command may be provided to the command controller 230. In addition, the power consumption limit of the power mode for executing the command may be provided by the command controller 230. The command may instruct the memory device to perform a programming operation, a read operation, or an erase operation.

[0177] 9A to 9C The power consumption according to the commands of various power modes is shown. In one embodiment, the power consumption of the power mode determined by the command is shown.

[0178] exist Fig.9A In , a command to be executed on the memory device 100 is executed during a time period between 0 and ta, and the power consumption during the time period between 0 and ta may be PC1. Fig. 9BIn , the command to be executed on the memory device 100 is executed during the time period between 0 and ta, and the power consumption during the time period between 0 and tb may be PC2a, and the power consumption during the time period between tb and ta may be PC2b. Fig. 9C , the command to be executed on the memory device 100 is executed during the time period between 0 and ta. The power consumption during the time period between 0 and tc may be PC3a, the power consumption during the time period between tc and tb may be PC3b, the power consumption during the time period between tb and tc' may be PC3d, and the power consumption during the time period between tc' and ta may be PC3c.

[0179] refer to 9A to 9C , PC1 can be the average of PC2a and PC2b. PC1 can be subdivided into PC2a and PC2b. In other words, Fig. 9B It is shown Fig.9A A diagram showing the division of power consumption over time. Throughout the specification, power consumption may be expressed as a power level or total power consumption during the period.

[0180] Similarly, PC2a can be the average of PC3a and PC3b. PC2b can be the average of PC3c and PC3d. In other words, PC2a can be subdivided into PC3a and PC3b, and PC2b can be subdivided into PC3c and PC3d. Therefore, Fig. 9C It is shown Fig. 9B A diagram showing the division of power consumption over time is shown.

[0181] Can be obtained from FIG. 9A to FIG. 9C In other words, the degree of power consumption subdivision can be increased from the minimum power mode MIN_MODE to the maximum power mode MAX_MODE in sequence. In the case where the power consumption is subdivided, the delay time of the command being delayed can be reduced. That is, because the delay time is determined based on the subdivided power consumption, the delay time can be reduced.

[0182] In detail, based on the comparison result of LPC and summed power consumption, the command controller 230 determines whether to delay at least one of the commands, and if so, determines the delay time. The summed power consumption may be the power consumption obtained by summing the peak power consumption required to execute each command. In the case where the power consumption is not subdivided, the command determined to be delayed may be executed after commands other than the command determined to be delayed have been completely executed. In other words, the time point at which the command determined to be delayed is executed may be determined as the time point at which other commands are completed.

[0183] If the power consumption is subdivided, the summed power consumption can be calculated for each time segment. Fig. 9B and Fig. 9CIn the example, the time is divided into subdivisions, and the summed power consumption can be calculated corresponding to each time segment. The command controller 230 can determine the delay time between time segments in each power mode. FIG. 9A to FIG. 9C Reduce latency.

[0184] exist Fig.9A In the case of , since the power consumption is not subdivided, even when the command is delayed, the maximum value of the summed power consumption does not change. In other words, since the memory device 100 and the memory controller 200 operate in the minimum power mode MIN_MODE, if commands other than the command determined to be delayed are completely executed, the command determined to be delayed can be executed. Thus, by subdividing the power consumption, the command determined to be delayed can be executed without advancing the delay time of the command.

[0185] Fig. 9B It is shown Fig.9A A diagram showing the breakdown of the power consumption. Fig. 9C It is shown Fig. 9B If the summed power consumption obtained by summing the peak power consumption among the power consumptions required to execute the commands is greater than the LPC, as determined by the memory controller 230, it may be determined that at least one command is delayed.

[0186] Here, reference Fig. 9B and Fig. 9C When at least one command is delayed, a delay time may be determined. A minimum delay time that causes the summed power consumption to not exceed LPC may be determined based on the delay time. The delay time may be determined in a time period between 0 and ta.

[0187] Fig. 10A and Fig. 10B is a diagram illustrating power consumption required to execute a command in an intermediate power mode according to an embodiment of the present disclosure.

[0188] More specifically, Fig. 10A and Fig. 10B is a diagram showing power consumption required to execute different commands when the power mode is the middle power mode MID_MODE. Fig. 10A and Fig. 10B , the horizontal axis indicates the time to execute a command, and the vertical axis indicates the power consumption as a function of time.

[0189] Fig. 10A and Fig. 10B The power consumption required to execute different commands in the intermediate power mode MID_MODE (i.e., in one power mode) is shown. Fig. 10A shows the power consumption required to execute the first command, and Fig. 10BThe power consumption required to execute the second command is shown. The number of commands to be executed on the memory device 100 is not limited in the embodiments contemplated by the present disclosure, and the number of commands can be increased without restriction.

[0190] In one embodiment, the power consumption for executing multiple commands can be changed in various ways. In addition, the power consumption of each command can be changed as a function of time.

[0191] exist Fig. 10A In , the power consumption in the time period between 0 and tb may be Pa+Pb, and the power consumption in the time period between tb and ta may be Pb. Fig. 10B In the example, the power consumption in the time period between 0 and tb may be Pb, and the power consumption in the time period between tb and ta may be Pa+Pb.

[0192] refer to Figure 8 , Fig. 10A and Fig. 10B , since the operation mode of the memory device 100 and the memory controller 200 is determined to be the middle power mode MID_MODE, LPC can be determined to be the second limited power consumption LPC2. Therefore, the power consumption of the memory device 100 and the memory controller 200 cannot exceed the second limited power consumption LPC2. If the power consumption of each command exceeds LPC2, any command can be delayed.

[0193] In one embodiment, if the first and second commands are executed simultaneously, the power consumption required to execute the first and second commands is required to be equal to or less than the second limited power consumption LPC2. In the case where the summed power consumption required to execute the first and second commands is equal to or less than the second limited power consumption LPC2, the first and second commands can be executed simultaneously. However, in the case where the summed power consumption required to execute the first and second commands exceeds the second limited power consumption LPC2, either of the first and second commands can be delayed.

[0194] In the case where the power consumption required to execute the first and second commands exceeds the second limited power consumption LPC2, it can be determined that the first or second command is delayed. If it can be determined that either of the first and second commands is delayed, the delay time can be determined based on the power consumption summed by the corresponding delay times. In other words, the minimum delay time that generates the summed power consumption that does not exceed LPC can be determined.

[0195] Reference will be made to Figures 11 to Fig.13 Describe in detail the method for determining the minimum delay time.

[0196] Fig.11A and Fig. 11B The present invention is shown in Fig. 10B Graph showing power consumption when commands in are delayed.

[0197] refer to Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B , Fig.11A and Fig. 11B Shown in Fig. 10B After the command (i.e., the second command) is delayed due to power consumption exceeding LPC, the summed power consumption is obtained by summing the power consumption required to execute the first and second commands. Fig.11A and Fig. 11B middle, Fig. 10B The delay time Δt of the second command may be greater than 0 and less than ta. Fig.11A and Fig. 11B , the horizontal axis indicates the time to execute a command, and the vertical axis indicates the power consumption as a function of time.

[0198] refer to Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B , Fig.11A and Fig. 11B The summed power consumption obtained by summing the power consumption required to execute the first command and the power consumption required when the second command is delayed is shown. Fig.11A The case where the delay time Δt of the second command is greater than 0 and less than tb is shown. Fig. 11B The case where the delay time Δt of the second command is greater than tb and less than ta is shown.

[0199] The delay time Δt of the second command cannot exceed ta. In other words, if the delay time Δt of the second command exceeds ta, the delay time Δt cannot be reduced because the second command is executed after the first command is executed. Therefore, it is assumed that the delay time Δt does not exceed ta.

[0200] In one embodiment, Fig.11A The power consumption in the time period between 0 and Δt of may be Pa+Pb. In other words, since the second command has been delayed, the power consumption in the time period between 0 and Δt may be at least the power consumption required to execute the first command between 0 and tb.

[0201] exist Fig.11A In the example, the power consumption in the time period between Δt and ta may be the power consumption required to execute the first and second commands. In other words, the power consumption in the time period between Δt and ta may be the power consumption required to execute the first and second commands after the delay time Δt has passed.

[0202] refer to Fig. 10A , Fig. 10B and Fig.11A, the power consumption in the time period between △t and tb may be Pa+2*Pb, the power consumption in the time period between tb and tb+△t may be 2*Pb, and the power consumption in the time period between tb+△t and ta may be Pa+2*Pb. In other words, the power consumption required in the time period between △t and tb may be obtained by dividing the power consumption Pa+Pb required to execute the first command by the power consumption Pa+Pb required to execute the first command. Fig. 10A and Fig. 10B The power consumption required in the time period between tb and tb+Δt may be 2*Pb obtained by summing the power consumption Pb required to execute the first command and the power consumption Pb required to execute the second command. The power consumption required in the time period between tb+Δt and ta may be Pa+2*Pb obtained by summing the power consumption Pb required to execute the first command and the power consumption Pa+Pb required to execute the second command.

[0203] Fig.11A The power consumption required in the time period between ta and ta+Δt of the second command may be Pa+Pb. In other words, since the second command has been delayed, the power consumption in the time period between ta and ta+Δt may be Pa+Pb. Fig. 10B The power consumption required for the second command in .

[0204] Therefore, when the delay time Δt of the second command is greater than 0 and less than tb, the peak power consumption may be Pa+2*Pb.

[0205] In one embodiment, Fig. 11B The power consumption required in the time period between 0 and tb of the execution may be Pa+Pb, and the power consumption required in the time period between tb and Δt may be Pb. In other words, since the second command has been delayed and Δt is greater than tb, the power consumption in the time period between 0 and Δt may be Pb. Fig. 10A The power consumption required for the first command in .

[0206] exist Fig. 11B In the example, the power consumption in the time period between Δt and ta may be the power consumption required to execute the first and second commands. In other words, the power consumption in the time period between Δt and ta may be the power consumption required to execute the first and second commands after the delay time Δt has elapsed when Δt is greater than tb. Fig. 10A and Fig. 10B , the power consumption required in the time period between Δt and ta may be 2*Pb obtained by summing the power consumption Pb required to execute the first command and the power consumption Pb required to execute the second command.

[0207] In one embodiment, Fig. 11B Execute in the time period between ta and tb+△t Fig. 10BThe power consumption required for the delayed command may be Pb, and the power consumption required in the time period between tb+Δt and ta+Δt may be Pa+Pb. In other words, since the second command has been delayed, the power consumption in the time period between ta and ta+Δt may be the power consumption required to execute the second command.

[0208] Therefore, when the delay time Δt of the second command is greater than tb and less than ta, the peak power consumption may be Pa+Pb.

[0209] Fig.11A and Fig. 11B Shows when Fig. 10B The power consumption when the command (i.e., the second command) is delayed. Therefore, when the delay time △t of the second command is greater than 0 and less than tb, the peak power consumption can be Pa+2*Pb. When the delay time △t of the second command is greater than tb and less than ta, the peak power consumption can be Pa+Pb.

[0210] Fig. 12A and Fig. 12B The present invention is shown in Fig. 10A A graph of the power consumption when commands are delayed.

[0211] refer to Fig. 10A , Fig. 10B , Fig. 12A and Fig. 12B , Fig. 12A and Fig. 12B Shown in Fig. 10A The summed power consumption is obtained by summing the power consumption required to execute the first and second commands after the command (ie, the first command) is delayed. Fig. 12A and Fig. 12B In , the delay time Δt is represented by a negative number, and both the first and second commands are represented by negative numbers, so that the first command follows the second command, and the second command has a negative value but precedes the first command. Fig. 12A and Fig. 12B Thus, the summed power consumption obtained by summing the power consumption required to execute the first and second commands after the first command is delayed is shown.

[0212] exist Fig. 12A and Fig. 12B , the horizontal axis indicates the time to execute a command, and the vertical axis indicates the power consumption as a function of time.

[0213] Fig. 10B The delay time Δt of the second command can be greater than -ta and less than 0. Therefore, Fig. 10A The delay time Δt of the first command may be greater than 0 and less than ta.

[0214] The delay time -Δt of the first command cannot exceed ta in the negative direction. In other words, if the delay time -Δt of the first command exceeds -ta in the negative direction, the delay time -Δt cannot be reduced because the first command is executed after the second command is executed. Therefore, it is assumed that the delay time -Δt does not exceed -ta.

[0215] refer to Fig. 10A , Fig. 10B , Fig. 12A and Fig. 12B , Fig. 12A and Fig. 12B The total power consumption obtained by summing the power consumption required when the first command is delayed and the power consumption required when the second command is delayed is shown. Fig. 12A The case where the delay time Δt of the second command is greater than −tb and less than 0 is shown. Fig. 12A The case where the delay time Δt of the first command is greater than 0 and less than tb is shown. Fig. 12B The case where the delay time Δt of the second command is greater than -ta and less than -tb is shown. Fig. 12A The case where the delay time Δt of the first command is greater than tb and less than ta is shown.

[0216] In one embodiment, Fig. 12A The power consumption required in the time period between -ta-Δt and -ta of the first command may be Pb. In other words, since the first command has been delayed, the power consumption in the time period between -ta-Δt and -ta may be Pb. Fig. 10B The power consumption required for the second command.

[0217] exist Fig. 12A In the example, the power consumption in the time period between -ta and -Δt may be the power consumption required to execute the first and second commands. In other words, the power consumption in the time period between -ta and -Δt may be the power consumption required to execute the first and second commands after the delay time Δt has passed.

[0218] In detail and with reference Fig. 10A and Fig. 10B, the power consumption in the time period between -ta and -tb-△t may be Pa+2*Pb, the power consumption in the time period between -tb-△t and -tb may be 2*Pa+2*Pb, and the power consumption in the time period between -tb and -△t may be Pa+2*Pb. The power consumption required in the time period between -ta and -tb-△t may be Pa+2*Pb obtained by summing the power consumption Pb required to execute the first command and the power consumption Pa+Pb required to execute the second command. In other words, the power consumption required in the time period between -tb-△t and -tb may be 2*Pa+2*Pb obtained by summing the power consumption Pa+Pb required to execute the first command and the power consumption Pa+Pb required to execute the second command. In other words, the power consumption required in the time period between -tb and -△t may be Pa+2*Pb obtained by summing the power consumption Pa+Pb required to execute the first command and the power consumption Pb required to execute the second command.

[0219] exist Fig. 12A The power consumption required in the time period between -Δt and 0 may be Pb. In other words, since the first command has been delayed, the power consumption in the time period between -Δt and 0 may be the power consumption required to execute the first command.

[0220] Therefore, when the delay time Δt of the first command is greater than 0 and less than tb, the peak power consumption may be 2*Pa+2*Pb.

[0221] In one embodiment, Fig. 12B The power consumption required in the time period between -ta-Δt and -tb-Δt may be Pb, and the power consumption required in the time period between -tb-Δt and -ta may be Pa+Pb. In other words, since the first command has been delayed, the power consumption in the time period between -ta-Δt and -ta may be the power consumption required to execute the second command.

[0222] exist Fig. 12B , the power consumption in the time period between -ta and -Δt may be the power consumption required to execute the first and second commands. In other words, the power consumption in the time period between -ta and -Δt may be the power consumption required to execute the first and second commands after the delay time Δt has elapsed. The power consumption required in the time period between -ta and -Δt may be 2*Pa+2*Pb obtained by summing the power consumption Pa+Pb required to execute the first command and the power consumption Pa+Pb required to execute the second command.

[0223] In one embodiment, Fig. 12BThe power consumption required in the time period between -Δt and -tb may be Pa+Pb, and the power consumption required in the time period between -tb and 0 may be Pb. In other words, since the first command has been delayed, the power consumption in the time period between -Δt and 0 may be the power consumption required to execute the first command.

[0224] Therefore, when the delay time Δt of the first command is greater than tb and less than ta, the peak power consumption may be 2*Pa+2*Pb.

[0225] Fig. 12A Shows when Fig. 10A The power consumption when the command (i.e., the first command) is delayed. Therefore, when the delay time Δt of the first command is greater than 0 and less than tb, the peak power consumption can be 2*Pa+2*Pb. Fig. 12B In the example, when the delay time Δt of the first command is greater than tb and less than ta, the peak power consumption may be 2*Pa+2*Pb. In other words, when the first command is delayed, the peak power consumption may be 2*Pa+2*Pb regardless of the delay time Δt.

[0226] Fig.13 The present invention is shown in Fig. 10A and Fig. 10B Graph of peak power consumption when commands in are delayed.

[0227] refer to Fig. 10A , Fig. 10B and Fig.13 , Fig.13 The horizontal axis indicates the delay time Δt of the command, and the vertical axis indicates the required peak power consumption (PPC) as a function of the delay time Δt. Fig.13 Shows when Fig. 10B The first command (ie, the second command) is delayed based on the PPC required by the function of the delay time Δt. If the delay time Δt is less than 0, the first command may be delayed instead of the second command.

[0228] exist Fig.13 In the embodiment, it is assumed that the power mode of the memory device 100 and the memory controller 200 is the middle power mode ("MID_MODE"), and the LPC corresponding to the middle power mode is the second limited power consumption ("LPC2"). In other words, the power consumption required in the memory device 100 and the memory controller 200 cannot exceed the second limited power consumption LPC2.

[0229] exist Fig.13 In the example, it is also assumed that the summed power consumption 2*Pa+2*Pb required to execute the first and second commands exceeds the second limited power consumption LPC2.

[0230] refer to Fig. 12A , Fig. 12B and Fig.13 , when the delay time Δt is greater than -ta and less than 0, the peak power consumption (PPC) may be 2*Pa+2*Pb. In other words, the peak power consumption required when the first command is delayed may be 2*Pa+2*Pb.

[0231] However, since the peak power consumption (PPC) 2*Pa+2*Pb required when the first command is delayed exceeds the second limit power consumption LPC2, the first command cannot be delayed.

[0232] In one embodiment, when the PPC required when the first command is delayed does not exceed the second limit power consumption LPC2, the delay time Δt may be determined within a range of -ta to 0. Here, the fact that the delay time Δt is a negative number may mean that the first command is delayed. Therefore, the minimum absolute value of the second limit power consumption LPC2 that enables the PPC to not exceed the absolute value of the delay time Δt may be determined as the delay time Δt of the first command.

[0233] refer to Fig.11A , FIG. 11B to FIG. 13 , when the delay time △t is greater than 0 and less than tb, PPC may be Pa+2*Pb. When the delay time △t is greater than tb and less than ta, PPC may be Pa+Pb. In other words, the peak power consumption required when the second command is delayed may be Pa+2*Pb or Pa+Pb.

[0234] In one embodiment, since the required PPC is Pa+2*Pb when the delay time Δt is greater than 0 and less than tb, the PPC may exceed the second limited power consumption LPC2. Therefore, the delay time Δt cannot fall between 0 and tb.

[0235] In one embodiment, since the required PPC is Pa+Pb when the delay time Δt is greater than tb and less than ta, the PPC may not exceed the second limited power consumption LPC2. Therefore, the delay time Δt may be between tb and ta.

[0236] Thus, the minimum delay time for PPC not to exceed the second limited power consumption LPC2 can be determined based on the summed power consumption required to execute the first and second commands after the second command is delayed, so that Δt is at least tb. Therefore, in the case of executing the first and second commands at the same time, after the first command has been output, the second command can be output at the minimum delay time tb.

[0237] Fig.14A , Fig. 14B and Fig. 14C is a diagram illustrating a delay of a command when the summed power consumption exceeds the LPC according to an embodiment of the present disclosure.

[0238] Specifically, FIG. 14A to FIG. 14C Commands delayed according to power modes of the memory device 100 and the memory controller 200 are shown. Fig.14A shows the delay of commands when the memory device 100 and the memory controller 200 are operated in the maximum power mode MAX_MODE, Fig. 14B shows the delay of commands in the intermediate power mode MID_MODE, and Fig. 14C The delay of the command in the minimum power mode MIN_MODE is shown. When the power mode is the maximum power mode MAX_MODE, LPC can be determined as the first limited power consumption LPC1. When the power mode is the intermediate power mode MID_MODE, LPC can be determined as the second limited power consumption LPC2. When the power mode is the minimum power mode MIN_MODE, LPC can be determined as the third limited power consumption LPC3.

[0239] exist FIG. 14A to FIG. 14C , it is assumed that the first to fourth commands CMD1-CMD4 are commands respectively executed in the first to fourth dies DIE1-DIE4 included in the memory device 100. Each of the first to fourth commands CMD1-CMD4 may be any one of a program command for performing a program operation, a read command for performing a read operation, or an erase command for performing an erase operation.

[0240] In one embodiment, Fig.14A The commands executed on each die in the maximum power mode MAX_MODE are shown.

[0241] In detail, commands may be executed simultaneously on the first to fourth dies DIE1-DIE4. However, the summed power consumption obtained by summing the PPCs required to execute the commands may exceed the first limit power consumption LPC1. When the summed power consumption exceeds the first limit power consumption LPC1, any one of the first to fourth commands CMD1-CMD4 may be delayed.

[0242] As an example, when the fourth command CMD4 of the first to fourth commands CMD1-CMD4 is delayed, the summed power consumption obtained by summing the PPC may not exceed the first limit power consumption LPC1. Therefore, when the fourth command CMD4 is delayed, the delay time may be determined based on the summed power consumption. Thereafter, the minimum delay time corresponding to the summed power consumption that does not exceed the first limit power consumption LPC1 may be determined or calculated.

[0243] Thus, in Fig.14AIn the embodiment, after executing the first to third commands CMD1 - CMD3 on the first to third dies DIE3 , the delayed fourth command CMD4 is executed with a minimum delay time within a certain range, so that the peak power consumption can be prevented from exceeding the first limit power consumption LPC1 .

[0244] In one embodiment, Fig. 14B The commands executed on each die in the middle power mode MID_MODE are shown.

[0245] In detail, commands can be executed simultaneously on the first to fourth dies DIE1-DIE4. However, the summed power consumption obtained by summing the PPCs required to execute the commands may exceed the second limit power consumption LPC2. When the summed power consumption exceeds the second limit power consumption LPC2, any one of the first to fourth commands CMD1-CMD4 may be delayed.

[0246] As an example, even if the fourth command CMD4 of the first to fourth commands CMD1-CMD4 is delayed, the summed power consumption obtained by summing PPC may still exceed the second limit power consumption LPC2. In this case, any one of the first to third commands CMD1-CMD3 may also be delayed.

[0247] If the third and fourth commands CMD3 and CMD4 among the first to fourth commands CMD1-CMD4 are delayed, the summed power consumption obtained by summing PPC may not exceed the second limited power consumption LPC2. Therefore, when the third and fourth commands CMD3 and CMD4 are delayed, the minimum delay time that generates the summed power consumption that does not exceed the second limited power consumption LPC2 may be used.

[0248] Thus, in Fig. 14B In the embodiment, after executing the first and second commands CMD1 and CMD2 on the first and second dies DIE1 and DIE2, the third and fourth commands CMD3 and CMD4 are delayed. The third and fourth commands CMD3 can be executed with a minimum delay time within a certain range, so that the peak power consumption in the determined summed power consumption can be prevented from exceeding the second limited power consumption LPC2.

[0249] In another example, if the third command CMD3 is executed after the first and second commands CMD1 and CMD2 are completed, it can be determined whether the summed power consumption obtained by summing the PPCs of the commands to be executed after the operation is completed exceeds the second limited power consumption LPC2. If the summed power consumption does not exceed the second limited power consumption LPC2, the third command CMD3 can be executed immediately after the operations of the first and second commands CMD1 and CMD2 are executed. If the summed power consumption exceeds the second limited power consumption LPC2, the minimum delay time for making the summed power consumption not exceed the second limited power consumption LPC2 can be re-determined based on the summed power consumption determined by the delay time.

[0250] In one embodiment, Fig. 14C The commands executed on each die in the minimum power mode MIN_MODE are shown.

[0251] In detail, commands may be executed simultaneously on the first to fourth dies DIE1-DIE4. However, the summed power consumption obtained by summing the PPCs required to execute the commands may exceed the third limit power consumption LPC3. When the summed power consumption exceeds the third limit power consumption LPC3, any one of the first to fourth commands CMD1-CMD4 may be delayed.

[0252] When the second to fourth commands CMD2-CMD4 of the first to fourth commands CMD1-CMD4 are delayed, the summed power consumption obtained by summing PPC may not exceed the third limit power consumption LPC3. Therefore, the first command CMD1 may be executed first. Since the power mode is the minimum power mode MIN_MODE, the only question is whether the command has been delayed, regardless of the delay time of the command.

[0253] If the operation of executing the first command CMD1 has been completed, it can be determined whether the summed power consumption obtained by summing the PPCs required to execute the second to fourth commands CMD2-CMD4 exceeds the third limited power consumption LPC3. In one embodiment, the fourth command CMD4 is delayed so that the summed power consumption obtained by summing the PPCs does not exceed the third limited power consumption LPC3. Therefore, the second and third commands CMD3 can be executed before the fourth command CMD4.

[0254] If the operations of executing the second and third commands CMD2 and CMD3 are completed, it can be determined whether the summed power consumption obtained by summing the PPC required to execute other commands exceeds the third limited power consumption LPC3. In one embodiment, since only the fourth command CMD4 needs to be executed, the fourth command CMD4 can be executed after the operations of executing the second and third commands CMD2 and CMD3 have been completed.

[0255] Fig.15 2 is a diagram for describing the operation of the memory controller 200 according to an embodiment of the present disclosure.

[0256] Reference Fig.15 In step S1501 , the memory controller 200 may count requests received from the host 300 and determine an arrival time period ARV_PERIOD.

[0257] In detail, the memory controller 200 may receive a request from the host 300. Each request received from the host 300 may be a program request, a read request, an erase request, or a power mode set request PMSET_REQ.

[0258] The memory controller 200 may generate a count value by counting the number of requests received from the host 300. Here, the power mode setting request PMSET_REQ may be excluded from the count to be counted by the memory controller 200. In other words, the memory controller 200 may count requests other than the power mode setting request PMSET_REQ among the requests received from the host 300.

[0259] The memory controller 200 may determine an arrival period ARV_PERIOD based on the count value. The arrival period ARV_PERIOD may be a period between a time point when the count value is generated and a time point when the count value matches a preset reference value.

[0260] In step S1503, the memory controller 200 may determine a power mode based on the arrival time period ARV_PERIOD. The power mode determined in step S1503 may be an optimal power mode for the memory device 100 and the memory controller 200. A peak power consumption (PPC) required in the memory device 100 and the memory controller 200 may be determined based on the power mode. The PPC may correspond to a limited power consumption (LPC).

[0261] In step S1505, the memory controller 200 may determine a time point to output a command for an operation corresponding to the request based on the power mode. In other words, the memory controller 200 may determine a time point to output a command for performing an operation corresponding to the corresponding request received from the host 300 based on the power mode.

[0262] In detail, if the power modes of the memory device 100 and the memory controller 200 are determined, the LPC corresponding to the power modes may be determined. The LPC may be the maximum power that may be consumed in the memory device 100 and the memory controller 200.

[0263] The memory controller 200 may compare the summed power consumption required to execute the command with the LPC. If the summed power consumption exceeds the LPC, the memory controller 200 may determine to delay at least one command and determine the delay time of the corresponding command, that is, the time point to output the command.

[0264] Fig.16 2 is a diagram for describing the operation of the memory controller 200 according to an embodiment of the present disclosure.

[0265] refer to Fig.15 and Fig.16 , steps S1601-S1607 may be steps performed in step S1501. Steps S1609 and S1611 may be steps performed in step S1503. Step S1613 may be the same or substantially the same as step S1505.

[0266] In detail, in step S1601, the memory controller 200 may receive a request from the host 300. Each request received from the host 300 may be a program request, a read request, an erase request, or a power mode set request PMSET_REQ.

[0267] A program request, a read request, or an erase request may be a request to perform an operation on at least one die included in the memory device 100. In other words, a program request, a read request, or an erase request may be a request to perform an operation on only one die or a request to perform an operation on multiple dies.

[0268] The power mode setting request PMSET_REQ may be a request for setting the power modes of the memory device 100 and the memory controller 200. In other words, the power mode setting request PMSET_REQ may be a request for setting the LPC of the memory device 100 and the memory controller 200, rather than a request for performing an operation on the memory device 100. The memory controller 200 may receive the power mode setting request PMSET_REQ from the host 300 and set the power modes of the memory device 100 and the memory controller 200.

[0269] In step S1603, the memory controller 200 may determine whether the request received from the host 300 is a power mode setting request PMSET_REQ. If the request received from the host 300 is not a power mode setting request PMSET_REQ, the process may proceed to step S1605. If the request received from the host 300 is a power mode setting request PMSET_REQ, the process may proceed to step S1611.

[0270] In step S1605, the memory controller 200 may generate a count value by counting the number of requests received from the host 300. The memory controller 200 may count the number of requests other than the power mode setting request PMSET_REQ. The memory controller 200 may accumulate and count the number of requests. The memory controller 200 may generate a count value by counting the number of requests. According to the count value generated by the memory controller 200, the optimal power mode of the memory device 100 and the memory controller 200 may be determined.

[0271] In step S1607, the memory controller 200 may determine whether the count value matches the preset reference value. The count value may be generated by counting the number of requests received from the host 300. Since the count value is generated by accumulating requests, the count value may be increased to the preset reference value. If the count value matches the current reference value, the process proceeds to step S1609. If the count value does not match the preset reference value, the process proceeds to step S1605 until the count value matches the preset reference value.

[0272] In step S1609, the memory controller 200 may determine an arrival period ARV_PERIOD, which is a period between a time point at which a counter value is generated and a time point at which the count value matches a preset reference value. The memory controller 200 may calculate the arrival period ARV_PERIOD to determine a power mode. In other words, the optimal power mode of the memory device 100 and the memory controller 200 may be based on the arrival period ARV_PERIOD.

[0273] In step S1611, the memory controller 200 may determine or set a power mode. The power mode may be determined based on the arrival time period ARV_PERIOD or the power mode setting request PMSET_REQ received from the host 300. Here, the determined power mode may be an optimal power mode for the memory device and the memory controller.

[0274] In detail, as the arrival time period ARV_PERIOD increases, the LPC determined in the power mode determined by the memory controller 200 as the optimal power mode for the memory device 100 and the memory controller 200 may be reduced. Also, as the arrival time period ARV_PERIOD decreases, the LPC determined in the power mode determined by the memory controller 200 as the optimal power mode for the memory device 100 and the memory controller 200 may be increased. The LPC may be the maximum power that may be consumed in the memory device 100 and the memory controller 200.

[0275] In one embodiment, the memory controller 200 may determine a power mode setting request PMSET_REQ. In other words, the memory controller 200 may receive a power mode setting request PMSET_REQ for determining the power modes of the memory device 100 and the memory controller 200 from the host 300, and then determine the power modes of the memory device 100 and the memory controller 200 based on the power mode setting request PMSET_REQ.

[0276] In step S1613, the memory controller 200 may determine a time point to output the command. In one embodiment, if the summed power consumption required to execute the command is equal to or less than the LPC, the commands may be simultaneously output to the memory device 100. If the summed power consumption is greater than the LPC, the commands cannot be simultaneously output, and at least one command may be delayed.

[0277] Fig.17 2 is a diagram for describing the operation of the memory controller 200 according to an embodiment of the present disclosure.

[0278] Reference Fig.17 In step S1701, the memory controller 200 may request an LPC corresponding to the set power mode (e.g., the command delay determiner 233 may provide an LPC request LPC_REQ to the limit power management table 231 based on the power mode setting information PMSET_INF). The power mode may be determined based on the arrival time period ARV_PERIOD or the power mode setting request PMSET_REQ received from the host 300. The LPC may be the maximum power that can be consumed in the memory device 100 and the memory controller 200.

[0279] In step S1703, the memory controller 200 may receive an LPC (e.g., an LPC corresponding to a power mode in the restricted power management table 231 may be provided to the command delay determiner 233). The LPC may be received from the restricted power management table. The restricted power management table may include information about the LPC. The restricted power management table may include information about the LPC corresponding to the power mode determined by the power mode setting circuit 220. Information about the LPC corresponding to various power modes may be included in the restricted power management table. Therefore, the restricted power management table may include information about various LPCs.

[0280] In one embodiment, the memory controller 200 may receive an LPC corresponding to a power mode. After receiving the LPC, the memory controller 200 may compare the LPC with a summed power consumption obtained by summing a PPC required to execute a command, and generate a result of the comparison.

[0281] In step S1705, the memory controller 200 may sum the PPC required to execute the command. In one embodiment, when the memory device executes the command, the power consumption as a function of time may change in various ways. However, since the power consumption of the memory device 100 and the memory controller 200 is limited, the memory controller 200 may sum the PPC required to execute the command and determine whether the summed power consumption exceeds the LPC.

[0282] In step S1707 , the memory controller 200 may determine whether to delay a command or determine a delay time based on the LPC and the summed power consumption.

[0283] In one embodiment, if the summed power consumption is equal to or less than the LPC, the memory controller 200 may determine that all commands will be executed. In other words, the memory controller 200 may determine that there is no delay in the commands.

[0284] In one embodiment, if the summed power consumption is greater than the LPC, the memory controller 200 may determine to delay at least one command. The delay time may be the minimum delay time possible so that the summed power consumption does not exceed the LPC.

[0285] Fig.18 2 is a diagram for describing the operation of the memory controller 200 according to an embodiment of the present disclosure.

[0286] refer to Fig.17 and Fig.18 , step S1801 and step S1705 are identical or substantially identical to each other. Steps S1803-S1813 may be steps for further elaborating or illustrating step S1707.

[0287] In step S1801, the memory controller 200 may sum the PPC required to execute the command. The memory controller 200 may determine whether to delay the command and the delay time based on the summed power consumption obtained by summing the PPC. In other words, since the power consumption of the memory device 100 and the memory controller 200 is limited, the memory controller 200 may sum the PPC required to execute the command and determine whether the summed power consumption exceeds the LPC.

[0288] In step S1803, the memory controller 200 may determine whether the summed power consumption is greater than the LPC. The LPC may be determined according to the power mode. The LPC may be the maximum power that can be consumed in the memory device 100 and the memory controller 200. In the case where the summed power consumption is not greater than the LPC, that is, if the summed power consumption is equal to or less than the LPC, the process proceeds to step S1805. In the case where the summed power consumption is greater than the LPC, the process proceeds to step S1807.

[0289] In step S1805, if the summed power consumption is equal to or less than the LPC, the memory controller 200 may execute all commands. In other words, since the summed power consumption does not exceed the maximum power that can be consumed in the memory device 100 and the memory controller 200, the memory controller 200 may determine that all commands will be executed without delay. In this case, the memory controller 200 may determine that no command is delayed.

[0290] In step S1807, the memory controller 200 may determine that at least one command is delayed. In one embodiment, the memory controller 200 may determine to delay at least one command because the peak power consumption required to execute the command is greater than the LPC. In other words, if all commands are executed, the power consumption of the memory device 100 and the memory controller 200 will exceed the LPC. Therefore, at least one command may be delayed.

[0291] In step S1809, the memory controller 200 may determine the summed power consumption by the delay time of the command. In other words, when any one command is delayed, the memory controller 200 may sum the power consumption by the delay time. That is, the memory controller 200 may sum the power consumption of each time segment determined by the delay time.

[0292] In one embodiment, if all the summed power consumption exceeds the LPC, the memory controller 200 may delay another command. In other words, if all the summed power consumption exceeds the LPC, the memory controller 200 may additionally delay one command and redetermine the delay time based on the power consumption summed by the delay time. The memory controller 200 may delay the command until the power consumption summed by the delay time does not exceed the LPC.

[0293] In step S1811, the memory controller 200 may determine a minimum delay time that does not exceed LPC for summing power consumption. In other words, the memory controller 200 may determine a time point for outputting a command for performing an operation corresponding to a corresponding request received from the host 300 based on the power mode so as not to exceed LPC.

[0294] In detail, the power consumption summed based on the delay time may be greater than or less than LPC. Therefore, the memory controller 200 may determine the minimum time in the delay time that does not make the summed power consumption exceed LPC to minimize the delay time and minimize the total time required to execute all commands.

[0295] In step S1813, the memory controller 200 may output a command at a time point based on the determined delay time. In one embodiment, if the memory controller 200 determines to delay the command, the command determined to be delayed may be output at the determined delay time. In one embodiment, if the summed power consumption is equal to or less than the LPC, the memory controller 200 may execute all commands simultaneously. The command may be processed by multiple dies.

[0296] Fig.19 The present invention is shown in Figure 1 A diagram of an example of a memory controller.

[0297] The memory controller 1000 is coupled to the host and the memory device. In response to a request from the host, the memory controller 1000 can access the memory device. For example, the memory controller 1000 can control the write operation, read operation, erase operation and background operation of the memory device. The memory controller 1000 can provide an interface between the memory device and the host. The memory controller 1000 can drive firmware for controlling the memory device.

[0298] Reference Fig.19 , the memory controller 1000 may include a processor 1010 , a memory buffer 1020 , an error correction code (ECC) circuit 1030 , a host interface 1040 , a buffer control circuit 1050 , a memory interface 1060 , and a bus 1070 .

[0299] The bus 1070 may provide a channel between components of the memory controller 1000 .

[0300] The processor 1010 may control the overall operation of the memory controller 1000 and perform logic operations. The processor 1010 may communicate with an external host through a host interface 1040 and communicate with a memory device through a memory interface 1060. In addition, the processor 1010 may communicate with a memory buffer 1020 through a buffer control circuit 1050. The processor 1010 may control the operation of a memory device by using the memory buffer 1020 as an operating memory, a cache memory, or a buffer memory.

[0301] The processor 1010 may perform the function of a flash translation layer (FTL). The processor 1010 may convert a logical block address (LBA) provided by a host into a physical block address (PBA) through the FTL. The FTL may receive the LBA and convert the LBA into the PBA using a mapping table. The address mapping method using the FTL may be modified in various ways according to the unit of mapping. Representative address mapping methods may include a page mapping method, a block mapping method, and a hybrid mapping method.

[0302] The processor 1010 may randomize data received from the host. For example, the processor 1010 may use a randomization seed to randomize data received from the host. The randomized data may be provided to the memory device as data to be stored and may be programmed to the memory cell array.

[0303] During a read operation, the processor 1010 may de-randomize data received from the memory device. For example, the processor 1010 may use a de-randomization seed to de-randomize data received from the memory device. The de-randomized data may be output to the host.

[0304] In one embodiment, the processor 1010 may drive software or firmware to perform a randomization operation or a de-randomization operation.

[0305] The memory buffer 1020 may be used as an operation memory, a cache memory, or a buffer memory of the processor 1010. The memory buffer 1020 may store codes and commands to be executed by the processor 1010. The memory buffer 1020 may store data to be processed by the processor 1010. The memory buffer 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

[0306] The ECC circuit 1030 may perform error correction. The ECC circuit 1030 may perform an ECC encoding operation based on data to be written to the memory device through the memory interface 1060. The ECC encoded data may be transmitted to the memory device through the memory interface 1060. The ECC circuit 1030 may perform an ECC decoding operation on data received from the memory device through the memory interface 1060. For example, the ECC circuit 1030 may be included in the memory interface 1060 as a component of the memory interface 1060.

[0307] The host interface 1040 may communicate with an external host under the control of the processor 1010. The host interface 1040 may perform communication using at least one of various communication methods, such as a universal serial bus (USB), a serial ST attachment (SATA), a serial attached SCSI (SAS), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), a peripheral component interconnect (PCI), PCI Express (PCIe), a non-volatile memory express (NVMe), a universal flash memory (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a load-reduced DIMM (LRDIMM) communication method.

[0308] The buffer control circuit 1050 may control the memory buffer 1020 under the control of the processor 1010 .

[0309] The memory interface 1060 may communicate with the memory device 100 under the control of the processor 1010. The memory interface 1060 may transmit commands, addresses, and data with the memory device through a channel.

[0310] For example, the memory controller 1000 may include neither the memory buffer 1020 nor the buffer control circuit 1050 .

[0311] For example, the processor 1010 may use code to control the operation of the memory controller 1000. The processor 1010 may load code from a nonvolatile memory device (eg, a read-only memory) provided in the memory controller 1000. Alternatively, the processor 1010 may load code from a memory device through the memory interface 1060.

[0312] For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may transmit data in the memory controller 1000. The control bus may transmit control information such as commands and addresses in the memory controller 1000. The data bus and the control bus may be separated from each other and may neither interfere with nor affect each other. The data bus may be coupled to the host interface 1040, the buffer control circuit 1050, the ECC circuit 1030, and the memory interface 1060. The control bus may be coupled to the host interface 1040, the processor 1010, the buffer control circuit 1050, the memory buffer 1020, and the memory interface 1060.

[0313] Fig. 20 is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0314] Reference Fig. 20 , the memory card system 2000 may include a memory controller 2100 , a storage device 2200 , and a connector 2300 .

[0315] The memory controller 2100 is coupled to the memory device 2200. The memory controller 2100 can access the memory device 2200. For example, the memory controller 2100 can control the read operation, write operation, erase operation, and background operation of the memory device 2200. The memory controller 2100 can provide an interface between the memory device 2100 and the host. The memory controller 2100 can drive firmware for controlling the memory device 2200. The memory device 2200 can communicate with the reference Figure 2 The memory device 100 is implemented in the same manner as described above.

[0316] In one embodiment, the memory controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface and a memory interface, and an ECC circuit.

[0317] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) based on a specific communication protocol. In one embodiment, the memory controller 2100 can communicate with an external device through at least one of various communication protocols, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer small interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), firmware, a universal flash memory (UFS), Wi-Fi, Bluetooth, and a non-volatile memory express (NVMe) protocol. In one embodiment, the connector 2300 can be defined by at least one of the various communication protocols mentioned above.

[0318] In one embodiment, the memory device 2200 may be implemented as any of a variety of non-volatile memory devices, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-torque magnetic RAM (STT-MRAM).

[0319] In one embodiment, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC or MMCmicro), an SD card (SD, miniSD, microSD or SDHC), or a Universal Flash Storage (UFS).

[0320] Fig.21 is a block diagram illustrating a solid state drive (SSD) system using a storage device according to an embodiment of the present disclosure.

[0321] Reference Fig.21 , the SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 may exchange a signal SIG with the host 3100 through a signal connector 3001, and may receive power PWR through a power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of flash memories 3221-322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0322] In one embodiment, the SSD controller 3210 may perform the above reference Figure 1 The functions of the memory controller 200 are described.

[0323] The SSD controller 3210 may control the plurality of flash memories 3221-322n in response to a signal SIG received from the host 3100. In one embodiment, the signal SIG may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined by at least one of various interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer small interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), firmware, a universal flash memory (UFS), Wi-Fi, Bluetooth, and a non-volatile memory express (NVMe) interface.

[0324] The auxiliary power supply 3230 may be coupled to the host 3100 through the power connector 3002. The auxiliary power supply 3230 may be provided with power PWR from the host 3100 and may be charged by the power PWR. The auxiliary power supply 3230 may provide power to the SSD 3200 when the power from the host 3100 is not smoothly performed. In one embodiment, the auxiliary power supply 3230 may be located inside the SSD 3200 or outside the SSD 3200. For example, the auxiliary power supply 3230 may be provided on a mainboard and may provide auxiliary power to the SSD 3200.

[0325] The buffer memory 3240 is used as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221-322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221-322n. The buffer memory 3240 may include a volatile memory (such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM) or a nonvolatile memory (such as FRAM, ReRAM, STT-MRAM, and PRAM).

[0326] Fig. 22 is a block diagram illustrating a user system using a storage device according to an embodiment of the present disclosure.

[0327] Reference Fig. 22, the user system 4000 may include an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .

[0328] The application processor 4100 may run components included in the user system 4000, an operating system (OS), or a user program. In one embodiment, the application processor 4100 may include a controller, an interface, a graphic engine, etc. for controlling components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0329] The memory module 4200 may be used as a main memory, a working memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a nonvolatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In one embodiment, the application processor 4100 and the memory module 4200 may be packaged based on a package on package (POP) and may then be provided as a single semiconductor package.

[0330] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), WiMAX, WLAN, UWB, Bluetooth or WI-FI communications. In one embodiment, the network module 4300 may be included in the application processor 4100.

[0331] The storage module 4400 may store data therein. For example, the storage module 4400 may store data received from the application processor 4100. Alternatively, the storage module 4400 may transmit the data stored in the storage module 4400 to the application processor 4100. In one embodiment, the storage module 4400 may be implemented as a non-volatile semiconductor memory device, such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory with a three-dimensional (3D) structure. In one embodiment, the storage module 4400 may be provided as a removable storage medium (i.e., a removable drive), such as a memory card or an external drive of the user system 4000.

[0332] For example, the storage module 4400 may include a plurality of non-volatile memory devices. The storage module 4400 may be the same as that described above with reference to Figure 1 The storage device 50 operates in the same manner as described.

[0333] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or outputting data to an external device. In one embodiment, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric device. The user interface 4500 may also include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a motor.

[0334] Various embodiments of the present disclosure may provide a memory controller and a method of operating the memory controller, the memory controller being configured to determine whether to delay a command and a delay time based on limited power consumption of a memory device.

[0335] Although the embodiments of the present disclosure have been disclosed, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure.

[0336] Therefore, the scope of the present disclosure must be determined by the appended claims and their equivalents rather than by the preceding description thereof.

[0337] In the embodiments discussed above, all steps may be selectively performed or skipped. In addition, the steps in each embodiment may not always be performed in a conventional order. In addition, the embodiments disclosed in this specification and the accompanying drawings are intended to help those skilled in the art to more clearly understand the present disclosure, rather than to limit the scope of the present disclosure. In other words, those of ordinary skill in the art to which the present disclosure belongs will be able to easily understand that various modifications are possible based on the technical scope of the present disclosure.

[0338] The embodiments of the present disclosure have been described with reference to the accompanying drawings, and the specific terms or words used in the description should be interpreted in accordance with the spirit of the present disclosure without limiting its subject matter. It should be understood that many changes and modifications of the basic disclosed concepts described herein will still fall within the spirit and scope of the present disclosure as defined by the attached claims and their equivalents.

Claims

1. A computer memory storage device having a memory device having computer executable instructions embedded therein and having a memory controller, the memory controller, when executing commands to control the memory device, performs a method of reducing computer processing time by increasing the power consumed by the memory device and the memory controller when executing the commands, the computer memory storage device comprising: A memory controller circuit having a request counter that counts the number of requests received from the host and calculates an arrival time period when the number of requests matches a preset reference value; a power mode setting circuit configured to use the arrival time period to select a maximum power mode for the memory device and the memory controller from a plurality of power modes; as well as a command controller having a restricted power management table including the plurality of power modes, and determining a delay time period for executing one or more received requests, wherein the arrival time period is a time period between a time point when counting starts and a time point when the number of the requests matches the reference value, and Wherein the computer memory storage device minimizes an amount of time to process a received request in the selected power mode.

2. The computer memory storage device of claim 1, wherein the power mode setting circuit comprises: a power mode table having a plurality of arrival time periods corresponding to a plurality of power modes; as well as A plurality of limited power consumption values ​​are used to limit the power consumed by the memory device and the memory controller.

3. The computer memory storage device of claim 2, wherein the power mode setting circuit selects a power mode from the power mode table that sets power consumption limits to process the received request in the selected power mode.

4. The computer memory storage device of claim 3, wherein the power mode setting circuit selects a first power mode for a first arrival time period, wherein the power mode setting circuit selects the second power mode for the second arrival time period, wherein the first arrival time period is greater than the second arrival time period, and The first power mode corresponds to lower power consumption, and the second power mode corresponds to higher power consumption.

5. The computer memory storage device of claim 1 , wherein the command controller further comprises: a limited power management table including information on limited power consumption corresponding to an optimal power mode; a command delay determiner configured to generate delay information and a delay time for at least one of the requests according to the limited power consumption; as well as a command output circuit configured to output a command based on the delay information, The limited power consumption is the peak power consumption of the memory device and the memory controller.

6. The computer memory storage device of claim 5, wherein the command delay determiner compares the limit power consumption with a summed power consumption obtained by summing peak power consumptions required to execute the commands, and determines whether to delay at least one of the commands by a delay time. 7 . The computer memory storage device of claim 6 , wherein the command delay determiner determines to delay at least one of the commands if the summed power consumption is greater than the limit power consumption.

8. The computer memory storage device of claim 6, wherein if the summed power consumption is equal to or less than the limit power consumption, the command delay determiner determines to execute all of the commands.

9. The computer memory storage device of claim 7, wherein when at least one of the commands is delayed, the command delay determiner determines the summed power consumption by the delay time.

10. The computer memory storage device of claim 9, wherein the command delay determiner determines a minimum delay time that generates a summed power consumption that does not exceed the limit power consumption.

11. A method of operating a memory controller configured to control a memory device in a computer memory storage device, the method comprising: Receive a request from the host; generating a count value by counting the number of requests received from the host; calculating an arrival time period, the arrival time period being a time period between a time point at which the count value is generated and a time point at which the count value matches a preset reference value; determining a delay period for executing one or more received requests; determining a highest power mode among a plurality of power modes corresponding to the memory device and the memory controller based on the arrival time period; as well as increasing power consumption to the highest power mode that is enabled to perform operations corresponding to corresponding requests received from the host to the memory device, Wherein the computer memory storage device minimizes an amount of time to process a received request in the selected power mode.

12. The method of claim 11 , wherein determining the highest power mode comprises: In a longer arrival time period, determining that one of the plurality of power modes is an optimal power mode by which lower power consumption is determined as a limit power consumption, the limit power consumption being power consumption as a peak power that can be consumed in the memory device and the memory controller; as well as In the shorter arrival time period, one of the plurality of power modes is determined to be the optimum power mode by which higher power consumption is determined as the limit power consumption.

13. The method according to claim 11, further comprising: determining a plurality of time points of outputting the command includes requesting and receiving information about limiting power consumption corresponding to an optimal power mode, The limited power consumption is a peak power that can be consumed in the memory device and the memory controller.

14. The method according to claim 13, wherein determining the time point of outputting the command further comprises: comparing the limited power consumption with a summed power consumption obtained by summing peak power consumptions required to execute the command, and generating a comparison result; as well as Determine whether to delay at least one of the commands for a delay time according to the comparison result.

15. The method of claim 14, wherein determining whether to delay at least one of the commands by the delay time comprises: If the summed power consumption is greater than the limited power consumption, at least one of the commands is delayed.

16. The method of claim 14, wherein determining whether to delay at least one of the commands by the delay time comprises: If the summed power consumption is equal to or less than the limit power consumption, it is determined whether all of the commands are executed.

17. The method of claim 15, wherein determining whether to delay at least one of the commands by the delay time comprises: When at least one of the commands is delayed, the summed power consumption is re-determined.

18. The method of claim 17, wherein determining whether to delay at least one of the commands and the delay time comprises: A minimum delay time that generates a summed power consumption that does not exceed the limited power consumption is determined.

19. The method of claim 17, wherein determining whether to delay at least one of the commands by the delay time comprises: If the summed power consumption determined by the delay time exceeds the limit power consumption, one of the commands is delayed, and the delay time is determined based on the summed power consumption.

Images