Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate having a pseudo gate structure, the pseudo gate structure comprising a first region, a second region and a third region distributed in a direction parallel to the substrate surface, the second region and the third region being parallel to each other, the first region being located between the second region and the third region, and the two ends of the first region being connected to one end of the second region and one end of the third region respectively; forming a dielectric layer on the substrate, the dielectric layer being located on the sidewall surface of the pseudo gate structure; removing part of the first region, forming a first groove in the dielectric layer and the pseudo gate structure, and the first groove runs from the second region to the third region; forming a first isolation layer in the first groove; after forming the first isolation layer, removing the pseudo gate structure, forming an initial gate opening in the dielectric layer; and forming a second isolation layer between the first isolation layer and the inner wall of the initial gate opening. The performance of the semiconductor structure thus formed is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Metal-Oxide-Semiconductor (MOS) field effect transistor is a voltage-controlled device that controls the change of output current by input voltage. It is currently widely used in various electronic circuits. The gate is an important component of the field effect transistor, and the structure of the gate has a significant impact on the performance of the device.

[0003] With the continuous development of semiconductor manufacturing technology, the gate line width, which is used to measure the process level of semiconductor manufacturing technology, is getting smaller and smaller. Small gate line width can reduce the driving voltage of the formed semiconductor device, thereby reducing power consumption; and small gate line width can also reduce the size of the formed semiconductor device, improve integration, increase the number of semiconductor devices per unit area, and thus reduce production costs.

[0004] However, the existing photolithography technology cannot meet the gate manufacturing process with a smaller line width. Self-aligned double patterning (SADP) technology can be used to prepare gates with a smaller line width, and thus is widely accepted and applied in the gate manufacturing process.

[0005] However, the performance of the gate structure prepared using the existing technology needs to be improved. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0007] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a pseudo gate structure, the pseudo gate structure comprising a first region, a second region and a third region distributed parallel to the surface direction of the substrate, the second region and the third region are parallel to each other, the first region is located between the second region and the third region, and the two ends of the first region are respectively connected to one end of the second region and one end of the third region; forming a dielectric layer on the substrate, the dielectric layer is located on the side wall surface of the pseudo gate structure; removing part of the first region, forming a first groove in the dielectric layer and the pseudo gate structure, and the first groove extends from the second region to the third region; forming a first isolation layer in the first groove; after forming the first isolation layer, removing the pseudo gate structure, forming an initial gate opening in the dielectric layer; forming a second isolation layer between the first isolation layer and the inner wall of the initial gate opening.

[0008] Optionally, the initial gate opening further includes: a first opening formed by removing the first region, a second opening formed by removing the second region, and a third opening formed by removing the third region.

[0009] Optionally, the method for forming the second isolation layer includes: forming a second isolation material layer on the inner wall of the initial gate opening and the side wall of the first isolation layer; removing the second isolation material layer on the surface of the second opening side wall and the second isolation material layer on the surface of the third opening side wall to form the second isolation layer.

[0010] Optionally, a method for forming the second isolation material layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0011] Optionally, the process of removing the second isolation material layer includes a wet etching process.

[0012] Optionally, the material of the second isolation layer is different from that of the first isolation layer.

[0013] Optionally, the material of the second isolation layer includes oxide; and the oxide includes silicon oxide.

[0014] Optionally, the material of the first isolation layer includes nitride or nitride carbide; the nitride or nitride carbide includes silicon nitride or silicon nitride carbide.

[0015] Optionally, the process for forming the first isolation layer includes: forming a first isolation material layer on the surface of the substrate and in the first groove; planarizing the first isolation material layer until the surface of the dummy gate structure is exposed, and forming a first isolation layer in the first groove.

[0016] Optionally, the formation process of the first isolation material layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0017] Optionally, the second region and the third region are parallel to the first direction; the formation method also includes: removing part of the second region, forming a second groove in the dielectric layer and the pseudo gate structure, the second groove passes through the second region along a second direction, and the second direction is perpendicular to the first direction; removing part of the third region, forming a third groove in the dielectric layer and the pseudo gate structure, the third groove passes through the third region along the second direction.

[0018] Optionally, the first groove, the second groove and the third groove are formed simultaneously.

[0019] Optionally, the method further includes: forming a third isolation layer in the second groove and the third groove.

[0020] Optionally, the third isolation layer and the first isolation layer are formed simultaneously.

[0021] Optionally, the method further includes: after forming the second isolation layer, forming a first gate structure in the second opening, and forming a second gate structure in the third opening.

[0022] Correspondingly, the technical solution of the present invention also provides a semiconductor structure formed by any of the above methods.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] In the technical solution of the present invention, after removing the pseudo gate structure, a second isolation layer is formed between the first isolation layer and the inner wall of the initial gate opening, and the second isolation layer fills the gap between the first isolation layer and the inner wall of the gate opening, thereby avoiding the formation of a gate structure in the gap between the first isolation layer and the inner wall of the gate opening when the first gate structure and the second gate structure are subsequently formed, thereby causing the first gate structure and the second gate structure to be bridged, thereby causing a short circuit in the semiconductor device, thereby improving the electrical performance of the semiconductor structure.

[0025] Furthermore, the material of the second isolation layer is different from that of the first isolation layer, which can avoid damaging the first isolation layer when forming the second isolation layer, thereby preventing the isolation effect of the first isolation layer from being affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 4 It is a schematic cross-sectional structure diagram of a semiconductor structure formation process;

[0027] Figures 5 to 11 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] As described in the background art, the performance of the gate structure prepared by the prior art needs to be improved. Now, the formation process of a semiconductor structure is described and analyzed.

[0029] Figures 1 to 4 It is a schematic diagram of the process of semiconductor structure formation.

[0030] Please refer to Figure 1 , providing a substrate 100 , wherein the substrate 100 has a sacrificial layer 103 and a mask sidewall 102 located on the sidewall of the sacrificial layer 103 .

[0031] Please refer to Figure 2, remove the sacrificial layer 103, and etch the substrate 100 using the mask sidewall 102 as a mask to form a substrate and a dummy gate structure 104 located on the substrate; after forming the dummy gate structure 104, form a dielectric layer 105 on the substrate, and the dielectric layer 105 is located on the sidewall of the dummy gate structure 104 and is flush with the top surface of the dummy gate structure 104.

[0032] Please refer to Figure 3 , removing part of the dummy gate structure 104, forming a groove (not shown) in the dielectric layer 105; and forming an isolation layer 110 in the groove.

[0033] Please refer to Figure 4 , remove the remaining dummy gate structure 104, and form a gate opening (not shown) in the dielectric layer 105; and form a first gate structure 106 and a second gate structure 107 in the gate opening.

[0034] In the process of forming the semiconductor structure, as the integration of devices becomes higher and higher, a smaller device size is required to meet the demand. Under the existing photolithography technology, a double pattern exposure process is required to form the dummy gate structure 104. In the process of forming the dummy gate structure 104 by the double pattern exposure process, the line end of the sacrificial layer 103 will gradually shrink, and the ends of the mask sidewalls 102 formed on the sidewalls of the sacrificial layer 103 will be connected, so that the ends of the dummy gate structure 104 formed by etching with the mask sidewalls 102 as a mask will be connected, and the ends of the dummy gate structure 104 need to be cut off so as to subsequently form the first gate structure 106 and the second gate structure 107 that are independent of each other. However, in the process of cutting off the ends of the dummy gate structure 104, since the ends of the dummy gate structure 104 are not cut off completely, the first gate structure 106 and the second gate structure 107 formed subsequently will be bridged to cause a short circuit, thereby affecting the electrical performance of the semiconductor structure.

[0035] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same. After removing the pseudo gate structure, a second isolation layer is formed between the first isolation layer and the inner wall of the initial gate opening. The second isolation layer fills the gap between the first isolation layer and the inner wall of the gate opening, thereby avoiding the formation of a gate structure in the gap between the first isolation layer and the inner wall of the gate opening when the first gate structure and the second gate structure are subsequently formed, thereby causing the first gate structure and the second gate structure to be bridged, thereby causing a short circuit in the semiconductor device, thereby improving the electrical performance of the semiconductor structure.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 5 to 11 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process according to an embodiment of the present invention.

[0038] Please refer to Figure 5 , providing a substrate 200, wherein the substrate 200 has a dummy gate structure, wherein the dummy gate structure includes a first region 201, a second region 202, and a third region 203 distributed in a direction parallel to the substrate surface, wherein the second region 202 and the third region 203 are parallel to each other, the first region 201 is located between the second region 202 and the third region 203, and two ends of the first region 201 are respectively connected to one end of the second region 202 and one end of the third region 203.

[0039] In this embodiment, the second region 202 and the third region 203 are parallel to the first direction X of the substrate surface.

[0040] The number of the dummy gate structures is one or more. In the present embodiment, the number of the dummy gate structures is multiple, and the multiple dummy gate structures are arranged in parallel along the first direction X.

[0041] The material of the substrate 200 is a semiconductor material. In this embodiment, the material of the substrate 200 is polycrystalline silicon. In other embodiments, the material of the substrate 200 includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0042] In this embodiment, in order to form a dummy gate structure with a smaller size, the dummy gate structure is formed by a self-aligned multi-patterning process.

[0043] Specifically, the method for forming the pseudo gate structure includes: forming a pseudo gate material layer on a substrate; forming a sacrificial layer on the pseudo gate material layer; after forming a mask sidewall on the sidewall of the pseudo gate material layer, removing the sacrificial layer; after removing the sacrificial layer, etching the pseudo gate material layer using the mask sidewall as a mask to form the pseudo gate structure on the substrate.

[0044] The sacrificial layer is projected onto the surface of the substrate 200 in a strip shape. The sacrificial layer includes a first side wall and a second side wall opposite to each other, and the first side wall and the second side wall are parallel to the length direction of the strip; the sacrificial layer also includes a third side wall connected to the first side wall and the second side wall on both sides, and the third side wall is projected onto the surface of the substrate 200, i.e., the end edge of the strip along the length direction. Due to the limitation of the photolithography resolution, the end edge of the strip has a convex arc shape in the length direction of the strip.

[0045] Correspondingly, the mask sidewall formed on the third sidewall surface is projected onto the surface of the substrate 200 in an arc shape, and a portion of the mask sidewall on the third sidewall surface is etched to form the first region 201 of the dummy gate structure. That is, the first region 201 of the dummy gate structure is projected onto the surface of the substrate 200 in an arc shape.

[0046] Please refer to Figure 6 , a dielectric layer 204 is formed on the substrate 200, and the dielectric layer 204 is located on the sidewall surface of the dummy gate structure.

[0047] In this embodiment, the material of the dielectric layer 204 includes silicon oxide. In other embodiments, the material of the dielectric layer 204 includes silicon nitride or silicon carbide.

[0048] The method for forming the dielectric layer 204 includes: forming a dielectric material layer (not shown) on the surface of the substrate 200, the top and sidewalls of the dummy gate structure; and planarizing the dielectric material layer until the top surface of the dummy gate structure is exposed to form the dielectric layer 204.

[0049] In this embodiment, the process of forming the dielectric material layer includes a chemical vapor deposition process.

[0050] The surface of the dielectric layer 204 is lower than or flush with the top surface of the dummy gate structure. In this embodiment, the surface of the dielectric layer 204 is flush with the top surface of the dummy gate structure.

[0051] Please refer to Figure 7 , a portion of the first region 201 is removed, and a first groove 205 is formed in the dielectric layer 204 and the dummy gate structure, and the first groove 205 penetrates from the second region 202 to the third region 203 .

[0052] In this embodiment, the formation method further includes: removing a portion of the second region 202, forming a second groove 206 in the dielectric layer 204 and the dummy gate structure, wherein the second groove 206 penetrates the second region 202 along a second direction Y, and the second direction Y is perpendicular to the first direction X; removing a portion of the third region 203, forming a third groove 207 in the dielectric layer 204 and the dummy gate structure, wherein the third groove 207 penetrates the third region 203 along the second direction Y.

[0053] In this embodiment, the first groove 205, the second groove 206 and the third groove 207 are formed at the same time. In other embodiments, the first groove 205, the second groove 206 and the third groove 207 can be formed at different times.

[0054] In this embodiment, the process of removing part of the first region 201 includes an anisotropic dry etching process.

[0055] In this embodiment, the process of removing a portion of the second region 202 and a portion of the third region 203 includes an anisotropic dry etching process.

[0056] The first groove 205 is used for subsequently forming a first isolation layer and a second isolation layer to isolate the second region 202 and the third region 203 .

[0057] The second groove 206 is used for subsequently forming a third isolation layer to isolate the second region 202 to form more discrete gate structures.

[0058] The third groove 207 is used to subsequently form a third isolation layer to isolate the third region 203 to form more discrete gate structures.

[0059] Please refer to Figure 8 , a first isolation layer 208 is formed in the first groove 205 .

[0060] The formation process of the first isolation layer 208 includes: forming a first isolation material layer (not shown) on the surface of the substrate 200 and in the first groove 205 ; planarizing the first isolation material layer until the surface of the dummy gate structure is exposed, and forming the first isolation layer 208 in the first groove 205 .

[0061] The method for forming the first isolation material layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0062] In this embodiment, the method for forming the first isolation material layer includes an atomic layer deposition process. The first isolation material layer formed by the atomic layer deposition process has a denser structure and a better isolation effect.

[0063] The material of the first isolation layer 208 includes nitride or nitride carbide; in this embodiment, the nitride or nitride carbide includes silicon nitride or silicon nitride carbide.

[0064] In this embodiment, the method further includes: forming a third isolation layer 209 in the second groove 206 and the third groove 207 .

[0065] In this embodiment, the third isolation layer 209 is formed simultaneously with the first isolation layer 208. In other embodiments, the third isolation layer 209 and the first isolation layer 208 may be formed at different times.

[0066] In this embodiment, the first isolation layer 208 is used to isolate the second region 202 and the third region 203 to form separate second region 202 and third region 203. The third isolation layer 209 is used to isolate the second region 202 and the third region 203, respectively, so that the second region 202 forms a discrete gate structure, and the third region 203 forms a discrete gate structure, so as to form a plurality of device structures.

[0067] Please refer to Fig. 9 After forming the first isolation layer 208 , the dummy gate structure is removed to form an initial gate opening in the dielectric layer 204 .

[0068] In this embodiment, the initial gate opening includes: a first opening 212 formed by removing the first region 201 , a second opening 210 formed by removing the second region 202 , and a third opening 211 formed by removing the third region 203 .

[0069] The process of removing the dummy gate structure includes an anisotropic dry etching process or an isotropic wet etching process. In this embodiment, the process of removing the dummy gate structure includes an isotropic wet etching process.

[0070] In this embodiment, during the formation of the pseudo gate structure, since the end of the sacrificial layer is protruding, the end of the mask side wall formed on the side wall of the sacrificial layer is arc-shaped, and the pseudo gate structure is formed by etching the pseudo gate material layer with the mask side wall as a mask. The projection of the first area of ​​the pseudo gate structure on the substrate is also arc-shaped. Therefore, after the pseudo gate structure is subsequently removed to form an initial gate opening, the side wall of the first opening 212 is a curved surface, and a gap is easily generated between the side wall of the first isolation layer and the inner wall of the first opening 212. When the gate structure is subsequently formed at the initial gate opening, the gate material will also be deposited in the gap, so that the formed first gate structure and the second gate opening are bridged.

[0071] Please refer to Fig.10 , a second isolation layer 213 is formed between the first isolation layer 208 and the inner wall of the initial gate opening.

[0072] The method for forming the second isolation layer 213 includes: forming a second isolation material layer (not shown) on the inner wall of the initial gate opening and the side wall of the first isolation layer 208; removing the second isolation material layer on the side wall surface of the second opening 210 and the second isolation material layer on the side wall surface of the third opening 211 to form the second isolation layer 212.

[0073] The second isolation material layer is formed by a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the second isolation material layer is formed by an atomic layer deposition process.

[0074] The atomic layer deposition process can form a second isolation material layer with a relatively thin thickness and a dense structure between the first isolation layer 208 and the inner wall of the initial gate opening.

[0075] In this embodiment, the process of removing the second isolation material layer includes a wet etching process.

[0076] In this embodiment, the material of the second isolation layer 213 is different from the material of the first isolation layer 208 .

[0077] The material of the second isolation layer 213 includes oxide; in this embodiment, the oxide includes silicon oxide.

[0078] The material of the second isolation layer 213 is different from that of the first isolation layer 208. When a wet etching process is used to remove the second isolation material layer on the side wall surface of the second opening 210 and the second isolation material layer on the side wall surface of the third opening 211, the material of the second isolation layer 213 and the material of the first isolation layer 208 have different etching selectivities, which can prevent the wet etching process from damaging the first isolation layer 208, thereby affecting the isolation effect of the first isolation layer 208.

[0079] In this embodiment, the second isolation material layer on the side wall surface of the second opening 210 and the second isolation material layer on the side wall surface of the third opening 211 have a large contact area with the solution of the wet etching process, so the wet etching process has a faster etching rate for the second isolation material layer on the side wall surface of the second opening 210 and the second isolation material layer on the side wall surface of the third opening 211; the second isolation material layer in the first opening 212 has a smaller contact area with the solution of the wet etching process, so the wet etching process has a slower etching rate for the second isolation material layer in the first opening 212, thereby removing the second isolation material layer on the side wall surface of the second opening 210 and the second isolation material layer on the side wall surface of the third opening 211, and forming a second isolation layer 213 between the first isolation layer 208 and the inner wall of the initial gate opening.

[0080] A second isolation layer 213 is formed between the first isolation layer 208 and the inner wall of the initial gate opening. The second isolation layer 213 fills the gap between the first isolation layer 208 and the inner wall of the initial gate opening, thereby preventing the formation of a gate structure in the gap between the first isolation layer and the inner wall of the initial gate opening when the first gate structure and the second gate structure are subsequently formed, thereby causing the first gate structure and the second gate structure to be bridged, thereby causing a short circuit in the semiconductor device, thereby improving the electrical performance of the semiconductor structure.

[0081] Please refer to Fig.11 After forming a second isolation layer 213 between the first isolation layer 208 and the inner wall of the initial gate opening, a first gate structure 214 is formed in the second opening 210 , and a second gate structure 215 is formed in the third opening 211 .

[0082] In this embodiment, the first gate structure 214 and the second gate structure 215 are formed simultaneously.

[0083] The process of forming the first gate structure 214 and the second gate structure 215 includes a deposition process.

[0084] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by any of the above methods, please continue to refer to Fig.11 , including: a substrate; a first gate structure 214 located on the substrate; a second gate structure 215 located on the substrate; a dielectric layer 204 located on the substrate and on the sidewalls of the gate structure; a first isolation layer 208 and a second isolation layer 213 located between the first gate structure 214 and the second gate structure 215; and a third isolation layer 209 located between the first gate structure 214 and the second gate structure 215.

[0085] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, It is characterized in that include: A substrate is provided, wherein the substrate has a dummy gate structure, wherein the dummy gate structure comprises a first region, a second region, and a third region distributed in a direction parallel to a surface of the substrate, wherein the second region and the third region are parallel to each other, the first region is located between the second region and the third region, and two ends of the first region are respectively connected to one end of the second region and one end of the third region, a shape of the first region projected on the surface of the substrate is an arc, and the second region and the third region are parallel to the first direction; forming a dielectric layer on the substrate, wherein the dielectric layer is located on a sidewall surface of the dummy gate structure; Removing a portion of the first region, forming a first groove in the dielectric layer and the dummy gate structure, wherein the first groove extends from the second region to the third region, and a sidewall of the first groove exposes a portion of the surface of the first region in a first direction; forming a first isolation layer in the first groove; After forming the first isolation layer, removing the dummy gate structure, forming an initial gate opening in the dielectric layer, the initial gate opening comprising: removing a first opening formed by the first region; A second isolation layer is formed between the first isolation layer and the inner wall of the first opening.

2. The method for forming a semiconductor structure according to claim 1, It is characterized in that The initial gate opening further includes: a second opening formed by removing the second region and a third opening formed by removing the third region.

3. The method for forming a semiconductor structure according to claim 2, It is characterized in that The method for forming the second isolation layer includes: forming a second isolation material layer on the inner wall of the initial gate opening and the side wall of the first isolation layer; removing the second isolation material layer on the surface of the second opening side wall and the second isolation material layer on the surface of the third opening side wall to form the second isolation layer.

4. The method for forming a semiconductor structure according to claim 3, It is characterized in that The second isolation material layer is formed by a chemical vapor deposition process or an atomic layer deposition process.

5. The method for forming a semiconductor structure according to claim 3, It is characterized in that The process of removing the second isolation material layer includes a wet etching process.

6. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the second isolation layer is different from that of the first isolation layer.

7. The method for forming a semiconductor structure according to claim 6, It is characterized in that The material of the second isolation layer includes oxide; and the oxide includes silicon oxide.

8. The method for forming a semiconductor structure according to claim 6, It is characterized in that The material of the first isolation layer includes nitride or nitride carbide; the nitride or nitride carbide includes silicon nitride or silicon nitride carbide.

9. The method for forming a semiconductor structure according to claim 1, It is characterized in that The process for forming the first isolation layer includes: forming a first isolation material layer on the surface of the substrate and in the first groove; planarizing the first isolation material layer until the surface of the dummy gate structure is exposed, and forming a first isolation layer in the first groove.

10. The method for forming a semiconductor structure according to claim 9, It is characterized in that The formation process of the first isolation material layer includes a chemical vapor deposition process or an atomic layer deposition process.

11. The method for forming a semiconductor structure according to claim 1, It is characterized in that The formation method also includes: removing part of the second region, forming a second groove in the dielectric layer and the pseudo gate structure, the second groove penetrates the second region along a second direction, and the second direction is perpendicular to the first direction; removing part of the third region, forming a third groove in the dielectric layer and the pseudo gate structure, the third groove penetrates the third region along the second direction.

12. The method for forming a semiconductor structure according to claim 11, It is characterized in that The first groove, the second groove and the third groove are formed simultaneously.

13. The method for forming a semiconductor structure according to claim 11, It is characterized in that Also includes: A third isolation layer is formed in the second groove and the third groove.

14. The method for forming a semiconductor structure according to claim 13, It is characterized in that The third isolation layer is formed simultaneously with the first isolation layer.

15. The method for forming a semiconductor structure according to claim 2, It is characterized in that Also includes: After forming the second isolation layer, a first gate structure is formed in the second opening, and a second gate structure is formed in the third opening.

16. A semiconductor structure formed by the method according to any one of claims 1 to 15.

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