A flip-chip LED chip resistant to substrate warping and a preparation method thereof

Abstract

The present invention discloses a flip-chip LED chip resistant to substrate warping, which includes a stress buffer layer, a substrate, a light-emitting structure, a primary electrode structure, a passivation layer and a secondary electrode structure; the light-emitting structure is arranged on the front side of the substrate, the primary electrode structure is arranged on the light-emitting structure, the passivation layer is arranged on the primary electrode structure, and the secondary electrode structure is arranged on the passivation layer; the secondary electrode structure penetrates the passivation layer and is connected to the primary electrode structure; the stress buffer layer is arranged on the back side of the substrate. By implementing the present invention, the stress buffer layer can provide stress in the opposite direction to the packaging stress, effectively reducing the packaging warping, making the packaging substrate flat, improving the welding yield, and thus improving the overall yield of the flip-chip LED chip.

Description

Technical Field

[0001] The invention relates to the technical field of optoelectronic manufacturing, and in particular to a flip-chip LED chip resistant to substrate warping and a preparation method thereof. Background Art

[0002] Flip-chip LED chips are a new type of LED chips, which have better heat dissipation performance and light efficiency than ordinary regular LED chips. Therefore, they are widely used in various lighting products, including low-end applications such as bulbs and ceiling lamps, and high-end applications such as car lights and street lights. The packaging of flip-chip LED chips is quite different from that of traditional regular LED chips. Effective packaging is the key to the industrialization of flip-chip LED chips.

[0003] Flip-chip LED chips have high requirements for the flatness of the packaging substrate. If the substrate is not flat, the chip is easily damaged (see Figure 1 , due to the warping of the substrate, the stress is high, resulting in cracking of the passivation layer); at the same time, the warping of the substrate will also cause leakage, poor voltage and other defects, making the LED chip abnormally defective. According to statistics, when using ordinary substrates, the existing abnormal defect rate (VF<5.8V) can reach more than 15%, or even 65%; in addition, the warping of the substrate is also prone to low welding yield, leakage, and dead light problems. Therefore, how to increase the process window of flip-chip LED chips for poor packaging substrates is a problem that needs to be overcome in this field. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a flip-chip LED chip that is resistant to substrate warping, has strong bending resistance, and can effectively reduce the abnormal defect rate of packaging.

[0005] Another technical problem to be solved by the present invention is to provide a method for preparing a flip-chip LED chip that is resistant to substrate warping.

[0006] In order to solve the above technical problems, the present invention provides a flip-chip LED chip resistant to substrate warping, which includes a stress buffer layer, a substrate, a light-emitting structure, a primary electrode structure, a passivation layer and a secondary electrode structure;

[0007] The light emitting structure is disposed on the front side of the substrate, the primary electrode structure is disposed on the light emitting structure, the passivation layer is disposed on the primary electrode structure, and the secondary electrode structure is disposed on the passivation layer; the secondary electrode structure penetrates the passivation layer and is connected to the primary electrode structure;

[0008] The stress buffer layer is arranged on the back side of the substrate.

[0009] As an improvement of the above technical solution, the stress buffer layer is made of AlN or BN, and has a thickness of 0.3 to 6 μm.

[0010] As an improvement of the above technical solution, the secondary electrode structure includes a connection layer, a barrier layer, an elastic layer and an adhesion layer which are sequentially arranged on the passivation layer.

[0011] As an improvement of the above technical solution, the connection layer is made of Cr or Ti, and its thickness is 2 to 50 nm.

[0012] As an improvement of the above technical solution, the barrier layer includes a first barrier layer, a second barrier layer and a third barrier layer, the second barrier layer is made of Ni, and the first barrier layer and the third barrier layer are made of one of Au, Pt and Ti.

[0013] As an improvement of the above technical solution, the thickness of the first barrier layer and the third barrier layer is 100-500 nm, and the thickness of the second barrier layer is 50-200 nm.

[0014] As an improvement of the above technical solution, the barrier layer includes an Au layer, a Ni layer and an Au layer in sequence; or

[0015] The barrier layer includes a Ti layer, a Ni layer and a Ti layer in sequence; or

[0016] The barrier layer includes an Au layer, a Ni layer and a Pt layer in sequence.

[0017] As an improvement of the above technical solution, the elastic layer is a layer of AuSn alloy; or

[0018] The elastic layer includes multiple layers of Au layer, Sn layer and AuSn alloy layer;

[0019] The Sn content in the AuSn alloy layer is ≥80wt%, and the thickness of the elastic layer is ≥2.5μm;

[0020] The adhesion layer is made of Au or Pt and has a thickness of 10-100 nm.

[0021] As an improvement of the above technical solution, the substrate is sapphire, and the secondary electrode structure is parallel to the easy axis direction of the substrate.

[0022] Correspondingly, the present invention also discloses a method for preparing the above-mentioned flip-chip LED chip resistant to substrate warping, which comprises:

[0023] (1) providing a substrate;

[0024] (2) forming a light-emitting structure, a primary electrode structure, a passivation layer, and a secondary electrode structure in sequence on the front surface of the substrate to obtain a semi-finished product;

[0025] (3) Grinding and polishing the back side of the substrate, and forming a stress buffer layer on the back side of the ground and polished substrate, thereby obtaining a finished flip-chip LED chip that is resistant to substrate warping.

[0026] The implementation of the present invention has the following beneficial effects:

[0027] The flip-chip LED chip of the present invention has a stress buffer layer on the back of the substrate, which can provide stress in the opposite direction of the packaging stress, effectively reduce the packaging warping, make the packaging substrate flat, improve the welding yield, and thus improve the overall yield of the flip-chip LED chip. In addition, the secondary electrode of the present invention includes a connecting layer, a barrier layer, an elastic layer and an adhesion layer. This structure has stronger elasticity, protects the chip body from substrate stress pulling, and increases the process window of the flip-chip LED chip for poor packaging substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a defect diagram of existing flip-chip LED chip packaging;

[0029] Figure 2 It is a schematic diagram of the structure of a flip-chip LED chip resistant to substrate warping of the present invention;

[0030] Figure 3 is a schematic diagram of the easy axis direction of the sapphire substrate (substrate direction);

[0031] Figure 4 It is a schematic diagram of the easy axis direction of the sapphire substrate (crystal direction, looking down on the c-axis of the sapphire crystal);

[0032] Figure 5 is a schematic structural diagram of the first secondary electrode of the present invention;

[0033] Figure 6 is a schematic structural diagram of the second secondary electrode of the present invention;

[0034] Figure 7 The present invention is a flow chart of a method for preparing a flip-chip LED chip resistant to substrate warping. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. It is hereby stated that the directional terms such as up, down, left, right, front, back, inside, outside, etc. that appear or will appear in the text of the present invention are only based on the accompanying drawings of the present invention, and are not specific limitations of the present invention.

[0036] See also Figure 2The present invention provides a flip-chip LED chip resistant to substrate warping, which includes a stress buffer layer 1, a substrate 2, a light-emitting structure 3, a primary electrode structure 4, a passivation layer 5 and a secondary electrode structure 6; wherein the stress buffer layer 1 is arranged on the back side of the substrate 2, which can provide stress in the opposite direction to the packaging stress, thereby playing a role in alleviating the warping of the packaging substrate.

[0037] Specifically, the stress buffer layer 1 may be an AlN layer or a BN layer, but is not limited thereto. The thickness of the stress buffer layer 1 is 0.3 to 6 μm. When its thickness is less than 0.3 μm, the stress it provides is small and has little effect on correcting the warping of the substrate; when its thickness is greater than 6 μm, the stress provided is too large and is likely to cause reverse warping. Preferably, the thickness of the stress buffer layer is 1 to 4 μm, and may be 1 μm, 1.5 μm, 1.8 μm, 2.4 μm, 2.6 μm, 3 μm, or 3.5 μm, but is not limited thereto.

[0038] It should be noted that when flip-chip LED chips are soldered, the soldering temperature can be as high as 300°C. Due to the different thermal expansion coefficients of sapphire and GaN (light-emitting structure) [the thermal expansion coefficient of sapphire is (6-7)×10 -6 / K. The thermal expansion coefficient of GaN is 5.59×10 -6 / K, c-axis is 3.17×10 -6 / K], the substrate is subjected to GaN tensile stress during welding, and is prone to warping; therefore, in this embodiment, an AlN stress buffer layer is provided on the back of the substrate, and its thermal expansion coefficient is 3.5×10 -6 / K can provide tensile stress in the opposite direction to the GaN layer, thereby correcting the warping.

[0039] It should also be noted that in the prior art, AlN is often deposited on the front side of the substrate to play a buffering role. The main mechanism of action is that AlN can alleviate the lattice mismatch between the substrate and the GaN layer, thereby reducing the dislocation density and reducing the intracrystalline pressure. This is different from the mechanism of action in this embodiment.

[0040] The substrate 2 may be sapphire, silicon, or diamond, but is not limited thereto; preferably, sapphire is selected as the substrate 2.

[0041] The light emitting structure 3 includes an epitaxial layer 31, a transparent conductive layer 32, a reflective layer 33 and an exposed area. The epitaxial layer 31 includes a first semiconductor layer 311, a light emitting layer 312 and a second semiconductor layer 312 sequentially arranged on the substrate 2. The transparent conductive layer 32 is arranged on the second semiconductor layer 313, the reflective layer 33 is arranged on the transparent conductive layer 32, a hole 321 is arranged on the reflective layer 32, and the epitaxial layer 2 is etched as a whole to form an exposed area.

[0042] The primary electrode structure 4 includes a first electrode 41 and a second electrode 42 . The first electrode 41 is arranged in the exposed area and electrically connected to the first semiconductor layer 311 . The second electrode 42 is arranged on the reflective layer 33 and electrically connected to the transparent conductive layer 32 through the hole 321 , thereby achieving electrical connection with the second semiconductor layer 313 .

[0043] The passivation layer 5 is disposed on the reflective layer 33 , the primary electrode structure 4 and the surface of the exposed area, and a first hollow hole 51 is disposed at the first electrode 41 , and a second hollow hole 52 is disposed at the second electrode 42 .

[0044] The secondary electrode structure 6 includes a first secondary electrode 61 and a second secondary electrode 62, wherein the first secondary electrode 61 is electrically connected to the first electrode 41 through the first hollow hole 51, and the second secondary electrode 62 is electrically connected to the second electrode 42 through the second hollow hole 52. The first secondary electrode 61 and the second secondary electrode 62 have the same height and area. In order to alleviate the wafer warpage, the secondary electrode structure 6 should be distributed in the direction parallel to the easy axis of the sapphire substrate (reference Figure 3 , Figure 4 ), to avoid bending in the lattice direction. The secondary electrode 6 can be formed by Ebeam evaporation or Thermo evaporation, but is not limited thereto.

[0045] For further reference, Figure 5 , Figure 6 The first secondary electrode 61 and the second secondary electrode 62 each include a connection layer 611 / 621 , a barrier layer, an elastic layer 612 / 622 and an adhesion layer 613 / 623 which are sequentially arranged on the passivation layer 5 .

[0046] Among them, the connecting layer 611 / 621 is used to connect the primary electrode structure 4 and the secondary electrode structure 5. The specific material can be Cr and / or Ti, but it is not limited to this; it can be a single Cr layer, a single Ti layer, or a multi-layer Cr layer and / or Ti layer. The thickness of the connecting layer 611 / 612 is 2 to 50nm. When its thickness is less than 2nm, the bonding effect is too poor. When its thickness is greater than 50nm, it is easy to cause metal faults. Preferably, the thickness of the connecting layer 611 / 612 is 10 to 30nm, and can be 10nm, 13nm, 15nm, 19nm, 20nm, 22nm, 27nm, 29nm, but it is not limited to this.

[0047] Among them, the barrier layer can effectively prevent the diffusion of tin metal, so that it can combine with the substrate to form a eutectic and increase adhesion. Specifically, the barrier layer is a single-layer structure or a multi-layer stacked structure; when it is a single-layer structure, its material is Ni; when it is a stacked structure, its middle layer is Ni, and the materials of the stacked layers on both sides can be face-centered cubic or hexagonal closest packed metals, such as Au, Pt, Ti, etc., but not limited to this. Among them, Ni metal is easy to form fusion with other metals to prevent metal diffusion. Face-centered cubic or hexagonal closest packed metals have the highest number of atoms stacked on a single interface, which can effectively prevent metal diffusion.

[0048] Specifically, the barrier layer includes a first barrier layer 614 / 624, a second barrier layer 615 / 625 and a third barrier layer 616 / 626 in sequence; wherein the materials of the first barrier layer 614 / 624 and the third barrier layer 616 / 626 are Au and / or Pt and / or Ti, and the material of the second barrier layer 615 / 625 is Ni. The thickness of the first barrier layer 614 / 624 is 100-500nm, the thickness of the second barrier layer 615 / 625 is 50-200nm, and the thickness of the third barrier layer 616 / 626 is 100-500nm. If the thickness of the first barrier layer and the third barrier layer is greater than 500nm, it is easy to cause excessive voltage, affecting the energy efficiency of the flip-chip LED chip.

[0049] More specifically, in this embodiment, the barrier layer includes an Au layer, a Ni layer and an Au layer in sequence; in another embodiment of the present invention, the barrier layer includes a Ti layer, a Ni layer and a Ti layer in sequence; in another embodiment of the present invention, the barrier layer includes an Au layer, a Ni layer and a Pt layer in sequence.

[0050] The material of the elastic layer 612 / 622 is one or more of AuSn alloy, Au, and Sn; wherein the Sn content in the AuSn alloy is ≥80%. The elastic layer 612 / 622 is a single-layer structure or a stacked structure, for example, a single-layer structure of an AuSn alloy layer, or a structure of stacked multiple layers of Au, Sn, and AuSn alloy layers; the total thickness of the elastic layer is ≥2.5μm.

[0051] The material of the adhesion layer 613 / 623 is Au or Pt, but not limited thereto; its thickness is 10-100nm. If its thickness is less than 10nm, it cannot effectively shield the elastic layer; if its thickness is greater than 100nm, it will affect the subsequent packaging welding. Preferably, the thickness of the adhesion layer 613 / 623 is 30-80nm, and exemplary ones may be 32nm, 44nm, 49nm, 53nm, 66nm, 72nm, but not limited thereto.

[0052] Accordingly, see Figure 7 The present invention also provides a method for preparing the above-mentioned flip-chip LED chip resistant to substrate warping, which comprises the following steps:

[0053] S1: providing a substrate;

[0054] S2: forming a light-emitting structure, a primary electrode structure, a passivation layer and a secondary electrode structure in sequence on the front side of the substrate to obtain a semi-finished product;

[0055] Specifically, S2 includes:

[0056] S21: forming an epitaxial layer on the front side of the substrate;

[0057] The epitaxial layer 31 includes a first semiconductor layer 311 , a light emitting layer 312 and a second semiconductor layer 313 . Specifically, the first semiconductor layer 311 is an N-type gallium nitride layer, and the second semiconductor layer 313 is a P-type semiconductor layer, but the present invention is not limited thereto.

[0058] S22: performing photolithography and etching on the epitaxial layer to form an exposed area;

[0059] Specifically, a bare region penetrating to the first semiconductor layer 311 is formed on the epitaxial layer 31 by photolithography and etching processes. During etching, the easy axis direction of the substrate is selected for etching.

[0060] S23: forming a transparent conductive layer on the epitaxial layer;

[0061] Specifically, the transparent conductive layer 32 is formed on the second semiconductor layer 313 .

[0062] S24: forming a reflective layer on the transparent conductive layer;

[0063] Specifically, after the reflective layer is formed, it is necessary to perform photolithography on the reflective layer to form the hole 321 .

[0064] S25: forming a primary electrode structure on the reflective layer and the exposed area;

[0065] Specifically, the first electrode 41 and the second electrode 41 are formed by electron beam evaporation, thermal evaporation or magnetron sputtering. The first electrode 41 is arranged in the exposed area and is electrically connected to the first semiconductor layer 311, and the second electrode 42 is arranged on the reflective layer 33 and is electrically connected to the transparent conductive layer 32 through the hole 321, thereby achieving electrical connection with the second semiconductor layer 313.

[0066] S25: forming a passivation layer, and performing photolithography etching on the passivation layer to expose the first electrode and the second electrode;

[0067] Specifically, the passivation layer 5 is disposed on the reflective layer 33 , the primary electrode structure 4 and the surface of the exposed area; and a first hollow hole 51 is formed at the first electrode 41 and a second hollow hole 52 is formed at the second electrode 42 by a photolithography and etching process.

[0068] S26: forming a secondary electrode structure on the passivation layer to obtain a semi-finished product;

[0069] Specifically, the secondary electrode structure may be formed by Ebeam evaporation or Thermo evaporation.

[0070] S3: grinding and polishing the back side of the substrate, and forming a stress buffer layer on the back side of the ground and polished substrate, so as to obtain a finished flip-chip LED chip that is resistant to substrate warping.

[0071] Specifically, S3 includes:

[0072] S31: grinding and polishing the back side of the semi-finished substrate;

[0073] S32: forming a stress buffer layer on the back side of the ground and polished substrate, thereby obtaining a finished flip-chip LED chip that is resistant to substrate warping;

[0074] Specifically, the formation temperature of the stress buffer layer 1 is 500-800° C. The stress buffer layer 1 formed at this temperature can provide a large tensile stress during the packaging process to prevent warping.

[0075] It should be noted that the AlN layer traditionally disposed on the front side of the substrate is usually formed at a temperature above 900° C. in order to play its role in reducing dislocations. This is because when the formation temperature is low, the crystal nucleation and crystal orientation of AlN are poor, and the dislocation density cannot be effectively reduced.

[0076] The flip-chip LED chip of the present invention and the conventional flip-chip LED chip were packaged and the experimental results are shown in the following table:

[0077]

[0078] It can be seen from the table that when the warp-resistant substrate (D6018KCDN) is used, the flip-chip LED chip of this embodiment is not much different from the conventional flip-chip LED chip. However, when the ordinary substrate (D6018HJN) is used, the genuine rate of this embodiment is 100%, while the conventional flip-chip LED chip is only 82.99%, indicating that the flip-chip LED chip in this embodiment has a strong warp-resistant ability.

[0079] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A flip-chip LED chip resistant to substrate warping, characterized in that: It comprises a stress buffer layer, a substrate, a light-emitting structure, a primary electrode structure, a passivation layer and a secondary electrode structure; the substrate is sapphire, and the secondary electrode structure is parallel to the easy axis direction of the substrate; The light emitting structure is arranged on the front side of the substrate, the primary electrode structure is arranged on the light emitting structure, the passivation layer is arranged on the primary electrode structure, and the secondary electrode structure is arranged on the passivation layer; the secondary electrode structure penetrates the passivation layer and is connected to the primary electrode structure; the secondary electrode structure comprises a connection layer, a barrier layer, an elastic layer and an adhesion layer which are arranged on the passivation layer in sequence; The stress buffer layer is arranged on the back side of the substrate.

2. The flip-chip LED chip resistant to substrate warping according to claim 1, characterized in that: The stress buffer layer is made of AlN or BN and has a thickness of 0.3-6 μm.

3. The flip-chip LED chip resistant to substrate warping according to claim 1, characterized in that: The connection layer is made of Cr or Ti, and has a thickness of 2-50 nm.

4. The flip-chip LED chip resistant to substrate warping according to claim 1, characterized in that: The barrier layer includes a first barrier layer, a second barrier layer and a third barrier layer, the second barrier layer is made of Ni, and the first barrier layer and the third barrier layer are made of one of Au, Pt and Ti.

5. The flip-chip LED chip resistant to substrate warping according to claim 4, characterized in that: The thickness of the first barrier layer and the third barrier layer is 100-500 nm, and the thickness of the second barrier layer is 50-200 nm.

6. The flip-chip LED chip resistant to substrate warping according to claim 1, characterized in that: The barrier layer includes an Au layer, a Ni layer and an Au layer in sequence; or The barrier layer includes a Ti layer, a Ni layer and a Ti layer in sequence; or The barrier layer includes an Au layer, a Ni layer and a Pt layer in sequence.

7. The flip-chip LED chip resistant to substrate warping according to claim 1, characterized in that: The elastic layer is a AuSn alloy layer; or The elastic layer includes multiple layers of Au layer, Sn layer and AuSn alloy layer; The Sn content in the AuSn alloy layer is ≥80wt%, and the thickness of the elastic layer is ≥2.5μm; The adhesion layer is made of Au or Pt and has a thickness of 10-100 nm.

8. A method for preparing a flip-chip LED chip resistant to substrate warping according to any one of claims 1 to 7, characterized in that: include: (1) Providing a substrate; (2) forming a light-emitting structure, a primary electrode structure, a passivation layer and a secondary electrode structure in sequence on the front surface of the substrate to obtain a semi-finished product; (3) Grinding and polishing the back side of the substrate, and forming a stress buffer layer on the back side of the ground and polished substrate, thereby obtaining a finished flip-chip LED chip that is resistant to substrate warping.

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