Interface signal loopback test method, device, computer equipment and storage medium

Abstract

The present application relates to an interface signal loopback test method, device, computer equipment and storage medium. The method includes: sending a query instruction to a powered-on chip to be tested; the chip to be tested is in a low-level state; when receiving the status parameter returned by the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected; when not receiving the status parameter returned by the chip to be tested, determining that the signal channel corresponding to the chip to be tested fails to connect. This method can completely test all signals of the production chip or PCIE interface, including data signals, clocks and reference clock signals, avoiding the cumbersome process of testing with auxiliary equipment such as an oscilloscope, and realizing fast and efficient testing of the PCIE interface hardware and whether the internal modules are connected, thereby effectively improving the testing efficiency of the production chip.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an interface signal loopback test method, device, computer equipment and storage medium. Background Art

[0002] With the development of computer technology, the PCIE (peripheral component interconnect express) interface is widely used in hardware, and communication terminals are becoming more and more common in people's lives. In order to ensure the perfect operation of communication equipment networking, many devices are required to have loopback test functions so that they can remotely monitor whether the communication equipment is running properly. The chips or modules of terminal equipment need to be tested for hardware and interface function paths before leaving the factory, so testing whether the loopback function of communication equipment is qualified before leaving the factory has become one of the important tests.

[0003] However, the current loopback test method is limited to testing only data signals, and cannot test clock signals and reference clock signals. When testing the PCIE interface path, it is necessary to connect the master and slave devices to perform the interface path test, or an oscilloscope and other auxiliary equipment are required to perform separate tests. It takes a lot of manpower and energy to test, which easily leads to low testing efficiency of production chips. Summary of the invention

[0004] Based on this, it is necessary to provide an interface signal loopback test method, device, computer equipment and storage medium that can improve the efficiency of production chip testing in response to the above technical problems.

[0005] A method for testing an interface signal loopback, the method comprising:

[0006] Sending a query command to a powered-on chip to be tested; the chip to be tested is in a low level state;

[0007] In case of receiving the status parameter returned by the chip under test, determining that the signal channel corresponding to the chip under test is successfully connected;

[0008] In the case where the status parameter returned by the chip under test is not received, it is determined that the signal channel corresponding to the chip under test fails to connect.

[0009] In one of the embodiments, the signal channel corresponding to the chip to be tested includes a data signal channel and a clock signal channel.

[0010] In one embodiment, after sending the query instruction to the powered-on chip to be tested, the method further includes:

[0011] Detecting a state parameter of a ground line corresponding to each clock signal;

[0012] In the case where it is detected that the state parameter of the ground line is in a low level state, determining that the link corresponding to the clock signal is successfully connected;

[0013] When it is detected that the state parameter of the ground line is in a high-impedance state, it is determined that the link connection corresponding to the clock signal fails.

[0014] An interface signal loopback test device, the device comprising:

[0015] A sending module, used for sending a query instruction to a powered-on chip to be tested; the chip to be tested is in a low level state;

[0016] The determination module is used to determine that the signal channel corresponding to the chip under test is successfully connected when the status parameter returned by the chip under test is received; if the status parameter returned by the chip under test is not received, determine that the signal channel corresponding to the chip under test is unsuccessfully connected.

[0017] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0018] Sending a query command to a powered-on chip to be tested; the chip to be tested is in a low level state;

[0019] In case of receiving the status parameter returned by the chip under test, determining that the signal channel corresponding to the chip under test is successfully connected;

[0020] In the case where the status parameter returned by the chip under test is not received, it is determined that the signal channel corresponding to the chip under test fails to connect.

[0021] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the following steps:

[0022] Sending a query command to a powered-on chip to be tested; the chip to be tested is in a low level state;

[0023] In case of receiving the status parameter returned by the chip under test, determining that the signal channel corresponding to the chip under test is successfully connected;

[0024] In the case where the status parameter returned by the chip under test is not received, it is determined that the signal channel corresponding to the chip under test fails to connect.

[0025] A method for testing an interface signal loopback, the method comprising:

[0026] After performing a low level setting operation on the pin corresponding to each clock signal channel of the chip to be tested, powering on the chip to be tested;

[0027] Sending a query instruction to the chip to be tested;

[0028] In case of receiving the status parameter returned by the chip under test, determining that the signal channel corresponding to the chip under test is successfully connected;

[0029] In the case where the status parameter returned by the chip under test is not received, it is determined that the signal channel corresponding to the chip under test fails to connect.

[0030] In one embodiment, the step of setting the pin of each clock signal channel of the chip to be tested to a low level comprises:

[0031] A resistor with a preset value is externally connected to each clock signal channel;

[0032] A ground connection operation is performed on the pin corresponding to each of the clock signal channels.

[0033] In one embodiment, after sending the query instruction to the chip to be tested, the method further includes:

[0034] Detecting a state parameter of a ground line corresponding to each clock signal;

[0035] In the case where it is detected that the state parameter of the ground line is in a low level state, determining that the link corresponding to the clock signal is successfully connected;

[0036] When it is detected that the state parameter of the ground line is in a high-impedance state, it is determined that the link connection corresponding to the clock signal fails.

[0037] An interface signal loopback test device, the device comprising:

[0038] A setting module, used for performing a low level setting operation on the pin corresponding to each clock signal channel of the chip to be tested, and then powering on the chip to be tested;

[0039] A sending module, used for sending a query instruction to the chip to be tested;

[0040] The determination module is used to determine that the signal channel corresponding to the chip under test is successfully connected when the status parameter returned by the chip under test is received; if the status parameter returned by the chip under test is not received, determine that the signal channel corresponding to the chip under test is unsuccessfully connected.

[0041] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0042] After performing a low level setting operation on the pin corresponding to each clock signal channel of the chip to be tested, powering on the chip to be tested;

[0043] Sending a query instruction to the chip to be tested;

[0044] In case of receiving the status parameter returned by the chip under test, determining that the signal channel corresponding to the chip under test is successfully connected;

[0045] In the case where the status parameter returned by the chip under test is not received, it is determined that the signal channel corresponding to the chip under test fails to connect.

[0046] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the following steps:

[0047] After performing a low level setting operation on the pin corresponding to each clock signal channel of the chip to be tested, powering on the chip to be tested;

[0048] Sending a query instruction to the chip to be tested;

[0049] In case of receiving the status parameter returned by the chip under test, determining that the signal channel corresponding to the chip under test is successfully connected;

[0050] In the case where the status parameter returned by the chip under test is not received, it is determined that the signal channel corresponding to the chip under test fails to connect.

[0051] The above-mentioned interface signal loopback test method, device, computer equipment and storage medium send a query command to the powered-on chip to be tested, and the chip to be tested is in a low-level state. When receiving the status parameter returned by the chip to be tested, it is determined that the signal channel corresponding to the chip to be tested is successfully connected. When the status parameter returned by the chip to be tested is not received, it is determined that the signal channel corresponding to the chip to be tested fails to connect. As a result, all signals of the production chip or PCIE interface, including data signals, clocks and reference clock signals, can be fully tested, avoiding the cumbersome process of testing with auxiliary equipment such as an oscilloscope, and realizing rapid testing of the PCIE interface hardware and whether the internal modules are connected, thereby effectively improving the testing efficiency of the production chip.

[0052] The above-mentioned interface signal loopback test method, device, computer equipment and storage medium, after performing a low-level setting operation on the pins corresponding to each clock signal channel of the chip to be tested, the chip to be tested is powered on. A query instruction is sent to the chip to be tested, and when the status parameter returned by the chip to be tested is received, it is determined that the signal channel corresponding to the chip to be tested is successfully connected. When the status parameter returned by the chip to be tested is not received, it is determined that the signal channel corresponding to the chip to be tested fails to connect. As a result, after performing a low-level setting operation on the clock signal of the PCIE interface, the verification of the signal hardware path can be realized, avoiding the cumbersome process of testing with auxiliary equipment such as an oscilloscope, thereby effectively improving the test efficiency of the production chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 An application environment diagram of an interface signal loopback test method in an embodiment;

[0054] Figure 2 A schematic diagram of a flow chart of an interface signal loopback test method in one embodiment;

[0055] Figure 3A A schematic diagram of performing a loopback test on a chip to be tested in one embodiment;

[0056] Figure 3B A schematic diagram of a flow chart of a step of detecting a state parameter of a ground line corresponding to each clock signal in an embodiment;

[0057] Figure 4 A schematic diagram of a flow chart of an interface signal loopback test method in another embodiment;

[0058] Figure 5 A schematic flow chart of steps for setting a low level for the pin of each clock signal channel of a chip to be tested in one embodiment;

[0059] Figure 6 is a structural block diagram of an interface signal loopback test device in one embodiment;

[0060] Figure 7 is a structural block diagram of an interface signal loopback test device in another embodiment;

[0061] Figure 8 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0063] The interface signal loopback test method provided in this application can be applied to Figure 1 In the application environment shown. Among them, the terminal 102 communicates with the chip to be tested 104 through the network. The terminal 102 sends a query instruction to the powered-on chip to be tested 104, and the chip to be tested 104 is in a low level state. When the terminal 102 receives the status parameter returned by the chip to be tested 104, it determines that the signal channel corresponding to the chip to be tested 104 is successfully connected. When the terminal 102 does not receive the status parameter returned by the chip to be tested 104, it determines that the signal channel corresponding to the chip to be tested 104 fails to connect. Among them, the terminal 102 can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, and portable wearable devices.

[0064] In one embodiment, Figure 2 As shown, a method for testing an interface signal loopback is provided. Figure 1 The terminal in is used as an example to illustrate, including the following steps:

[0065] Step 202, sending a query instruction to the powered-on chip to be tested, and the chip to be tested is in a low level state.

[0066] PCI-Express (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. Its original name was "3GIO". It was proposed by Intel in 2001 to replace the old PCI, PCI-X and AGP bus standards. PCIe is a high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging, and quality of service (QOS) and other functions.

[0067] PCIe was renamed "PCI-Express", or "PCI-e" for short, after it was certified and released by PCI-SIG (PCI Special Interest Group). Its main advantage is its high data transmission rate, and it also has considerable development potential. The PCI-e interface is a high-speed communication interface that can be used for communication between board sets and between boards. With the widespread use of PCI-e interfaces in hardware, chips or modules need to undergo hardware and interface function path testing before leaving the factory, so testing whether the loopback function of communication equipment is qualified before the communication equipment leaves the factory has become one of the important tests. Before the chip or module leaves the factory, staff can use test tools to perform path testing on the produced chips to ensure that the chips can work properly after leaving the factory.

[0068] Specifically, the terminal is used as an example of a test device. The terminal can send a query instruction to the powered-on chip to be tested, and the chip to be tested is in a low-level state. Among them, the powered-on chip to be tested refers to the power-on operation of the chip to be tested, that is, the power supply operation of the chip to be tested within the normal voltage range is performed so that it can start working normally. The low-level state refers to the operation of setting the signal of the chip to be tested to a low level, so that it is in a low-level state. For example, the user terminal can use the AT command, that is, the user can use the AT command AT+GTSET="PCIEQU",0 to manually send a query command.

[0069] Step 204 : upon receiving the status parameter returned by the chip under test, determining whether the signal channel corresponding to the chip under test is successfully connected.

[0070] After the terminal sends a query command to the powered-on chip to be tested, the terminal determines that the signal channel corresponding to the chip to be tested is successfully connected when receiving the status parameter returned by the chip to be tested. Specifically, after the terminal sends a query command to the powered-on chip to be tested, when the PCI-e loopback test is successful, the status parameter pcieloopback ok will be returned, that is, when the user terminal receives the status parameter value returned by the chip to be tested, it can be determined that the signal channel corresponding to the chip to be tested is successfully connected, that is, when the user sees the return value, it can be confirmed that the PCIE loopback test is successful.

[0071] Step 206: When the status parameter returned by the chip under test is not received, it is determined that the signal channel corresponding to the chip under test fails to connect.

[0072] After the terminal sends a query command to the powered-on chip to be tested, the terminal determines that the signal channel connection corresponding to the chip to be tested fails when the status parameter returned by the chip to be tested is not received. Specifically, after the terminal sends a query command to the powered-on chip to be tested, when the PCI-e loopback test is successful, the status parameter pcieloopbackok will be returned, that is, when the user terminal receives the status parameter value returned by the chip to be tested, it can be determined that the signal channel corresponding to the chip to be tested is successfully connected, that is, when the user sees the return value, it can be confirmed that the PCI-e loopback test is successful. If the loopback test is unsuccessful, the data will not be returned, that is, when the user terminal does not receive the status parameter value returned by the chip to be tested, it can be determined that the signal channel connection corresponding to the chip to be tested fails, that is, when the user does not see the return value, it can be confirmed that the PCI-e loopback test fails. In this application, the PCIE module inside the chip to be tested or the module is configured with a register, and the PCIE timing inside the module is set to an RC module, that is, the purpose of PCIE communication is achieved, so that it can quickly verify whether the path state is reached. Among them, register configuration refers to the configuration of high and low levels of the circuit inside the chip to be tested.

[0073] The traditional PCI-e interface loopback test method is limited to only testing data signals, and cannot test clock signals and reference clock signals. When testing clock signals and reference clock signals on the production line, code logic or auxiliary equipment such as oscilloscopes are required to perform separate tests, resulting in low efficiency in testing production chips on the production line. For modules or chip production lines, users are concerned about whether the loopback of the PCI-e interface can be tested efficiently and stably. In this embodiment, by sending a query instruction to the powered-on chip to be tested, the chip to be tested is in a low level state. When receiving the status parameter returned by the chip to be tested, it is determined that the signal channel corresponding to the chip to be tested is successfully connected. When the status parameter returned by the chip to be tested is not received, it is determined that the signal channel corresponding to the chip to be tested fails to connect. As a result, all signals of the production chip or PCIE interface, including data signals, clocks, and reference clock signals, can be fully tested, avoiding the cumbersome process of testing with auxiliary equipment such as oscilloscopes, and realizing fast and efficient testing of the PCIE interface hardware and internal modules to see if they are connected, thereby effectively improving the test efficiency of the production chip.

[0074] In one embodiment, the signal channel corresponding to the chip to be tested includes a data signal channel and a clock signal channel. Figure 3AAs shown, it is a schematic diagram of loopback test on a chip to be tested. The signal transmitted by the PCIE interface is a differential signal, so RXO_P and RXO_M represent the positive and negative of the received signal respectively. TXO_P and TXO_M represent the positive and negative of the transmitted signal respectively. R represents recvice, i.e. receiving the signal. T represents send, i.e. sending information. When the PCIE protocol communicates, it is necessary to connect the received signal and the transmitted signal so that the test equipment can test the transceiver signal. The transmitted signal and the received signal are collectively referred to as data signals. For example, during the loopback test, the RX type signal and the TX type signal are short-circuited, and the terminal is used to test whether the hardware path of the data signal is normal. When performing the loopback test, ioctl will return test data, which is the relevant information of the PCIE connection status. Data link refers to the connected state of the PCIE interface data. At the same time, in the embodiment of the present application, the hardware path of the clock signal, i.e., the CLK type signal, can also be verified. For example, during the loopback test, the CLK signal is connected to the external device, and the CLK signal is grounded. The grounding line of the CLK signal is detected by the test terminal, avoiding the cumbersome process of testing with auxiliary equipment such as an oscilloscope, thereby realizing the verification of the hardware path of the CLK signal. In this embodiment, not only the Rx and Tx signals are short-circuited, and then the data is sent and received, but also, by grounding the CLK signal, the terminal can also perform corresponding detection operations on the grounding of the CLK signal, thereby realizing fast and efficient verification of the hardware path of the signal.

[0075] In one embodiment, Figure 3B As shown, after sending the query instruction to the powered-on chip to be tested, the method further includes the step of detecting the state parameter of the ground line corresponding to each clock signal, specifically including:

[0076] Step 302: Detect the state parameters of the ground line corresponding to each clock signal.

[0077] Step 304: When the state parameter of the ground line is detected to be in a low level state, it is determined that the link corresponding to the clock signal is successfully connected.

[0078] Step 306: When the state parameter of the ground line is detected to be in a high impedance state, it is determined that the link connection corresponding to the clock signal fails.

[0079] After the terminal sends a query command to the powered-on chip to be tested, the terminal can detect the state parameters of the ground line corresponding to each clock signal. Specifically, the terminal can detect the state parameters of the ground line corresponding to each clock signal. When the terminal detects that the state parameter of the ground line is in a low-level state, it is determined that the link connection corresponding to the clock signal is successful. When the terminal detects that the state parameter of the ground line is in a high-impedance state, it is determined that the link connection corresponding to the clock signal fails. Before the chip to be tested is powered on, the hardware can be adjusted accordingly. For example, Figure 3A As shown, the PCIE_CLK_REQ, REF_CLK_P and REF_CLK_M signals can be connected to 50 ohm resistors on the fixtures such as the production line, and the ground signal is connected. The ground signal refers to the ground connection operation of the pin or signal on the circuit board. The function of the ground signal is to pull the signal down. After the above-adjusted chip or module to be tested is powered on, it starts normally. Further, the terminal can detect the state parameters of the ground line corresponding to each clock signal of the above PCIE_CLK_REQ, REF_CLK_P and REF_CLK_M. When the terminal detects that the state parameter of the ground line corresponding to the PCIE_CLK_REQ signal is in a low level state, it is determined that the link connection corresponding to the PCIE_CLK_REQ signal is successful. When the terminal detects that the state parameter of the ground line corresponding to REF_CLK_M is in a high impedance state, it is determined that the link connection corresponding to the REF_CLK_M signal fails. As a result, by using register configuration and adjusting the resistance value of the hardware, the PCIE network card device can be fully simulated, and all signals of the chip or PCIE can be fully tested, including data signals, clocks, and reference clock signals, thereby realizing the verification of the hardware paths of all signals, thereby effectively improving the efficiency of production chip testing.

[0080] In one embodiment, Figure 4 As shown, a method for testing an interface signal loopback is provided. Figure 1 The terminal in is used as an example to illustrate, including the following steps:

[0081] Step 402 , after performing a low level setting operation on the pin corresponding to each clock signal channel of the chip to be tested, the chip to be tested is powered on.

[0082] Step 404: Send a query instruction to the chip to be tested.

[0083] Step 406: upon receiving the status parameter returned by the chip under test, determine whether the signal channel corresponding to the chip under test is successfully connected.

[0084] Step 408: When the status parameter returned by the chip under test is not received, it is determined that the signal channel corresponding to the chip under test fails to connect.

[0085] The terminal can perform a low-level setting operation on the pins corresponding to each clock signal channel of the chip to be tested, and then power on the chip to be tested. The chip to be tested can be installed in a terminal device. The terminal sends a query command to the powered-on chip to be tested, and when the terminal receives the status parameter returned by the chip to be tested, it is determined that the signal channel corresponding to the chip to be tested is successfully connected. When the terminal does not receive the status parameter returned by the chip to be tested, it is determined that the signal channel corresponding to the chip to be tested fails to connect. As a result, after the clock signal of the PCIE interface is set to a low level, the verification of the signal hardware path can be achieved, avoiding the cumbersome process of testing with auxiliary equipment such as an oscilloscope, thereby effectively improving the test efficiency of the production chip.

[0086] In one embodiment, Figure 5 As shown, the steps of performing a low level setting operation on the pin of each clock signal channel of the chip to be tested include:

[0087] Step 502: Connect a resistor with a preset value to each clock signal channel.

[0088] Step 504: ground the pins corresponding to each clock signal channel.

[0089] The terminal can perform a low-level setting operation on the pin corresponding to each clock signal channel of the chip to be tested, and then power on the chip to be tested. Specifically, the terminal can connect a resistor of a preset value to each clock signal channel, and perform a ground connection operation on the pin corresponding to each clock signal channel. For example, the resistor of the preset value can be set to a 50-ohm resistor, and the function of the grounding resistor is a protective measure to prevent electrical or electronic equipment from being struck by lightning. Among them, the grounding operation is an operation for setting a low level on the pin corresponding to each clock signal channel. For example, the terminal can verify the hardware path of the clock signal, i.e., the CLK-type signal, on the fixture of the production line. For example, the PCIE_CLK_REQ, REF_CLK_P, and REF_CLK_M signals respectively represent reference clock signals. The PCIE_CLK_REQ, REF_CLK_P and REF_CLK_M signals can be connected to resistors with preset values ​​of 50 ohms on fixtures such as production lines, and the pins corresponding to each clock signal channel of PCIE_CLK_REQ, REF_CLK_P and REF_CLK_M can be grounded. After the chip or module to be tested that is grounded is powered on, it can start normally. Furthermore, the terminal can detect the state parameters of the grounding line corresponding to each clock signal of the PCIE_CLK_REQ, REF_CLK_P and REF_CLK_M. As a result, by using register configuration and adjusting the resistance value of the hardware, the PCIE network card device can be fully simulated, and all signals of the chip or PCIE, including data signals, clocks and reference clock signals, can be efficiently tested, and the hardware paths of all signals can be verified, thereby effectively improving the efficiency of production chip testing.

[0090] In one embodiment, after sending the query instruction to the chip to be tested, the method further includes the step of detecting the state parameter of the ground line corresponding to each clock signal, specifically including:

[0091] The state parameter of the ground line corresponding to each clock signal is detected.

[0092] When the state parameter of the ground line is detected to be in a low level state, it is determined that the link corresponding to the clock signal is successfully connected.

[0093] When the state parameter of the ground line is detected to be in a high impedance state, it is determined that the link connection corresponding to the clock signal fails.

[0094] After the terminal sends a query instruction to the powered-on chip to be tested, the terminal can detect the state parameters of the ground line corresponding to each clock signal. Specifically, the terminal can detect the state parameters of the ground line corresponding to each clock signal. When the terminal detects that the state parameter of the ground line is in a low-level state, it is determined that the link connection corresponding to the clock signal is successful. When the terminal detects that the state parameter of the ground line is in a high-resistance state, it is determined that the link connection corresponding to the clock signal fails. Among them, before the chip to be tested is powered on, the hardware can be adjusted accordingly. For example, a 50-ohm resistor can be connected to the PCIE_CLK_REQ, REF_CLK_P, and REF_CLK_M signals on a fixture such as a production line, and the ground signal can be connected. After the above-adjusted chip or module to be tested is powered on, it starts normally. Further, the terminal can detect the state parameters of the ground line corresponding to each clock signal of the above PCIE_CLK_REQ, REF_CLK_P, and REF_CLK_M. When the terminal detects that the state parameter of the ground line corresponding to the PCIE_CLK_REQ signal is in a low-level state, it is determined that the link connection corresponding to the PCIE_CLK_REQ signal is successful. When the terminal detects that the state parameter of the ground line corresponding to REF_CLK_M is in a high-impedance state, it is determined that the link connection corresponding to the REF_CLK_M signal fails. As a result, by using register configuration and adjusting the resistance value of the hardware, the PCIE network card device is fully simulated, and all signals of the chip or PCIE can be fully tested, including data signals, clocks, and reference clock signals, realizing the verification of the hardware paths of all signals, thereby effectively improving the efficiency of production chip testing.

[0095] It should be understood that although Figure 1-5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1-5 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0096] In one embodiment, Figure 6 As shown, an interface signal loopback test device is provided, including: a sending module 602 and a determining module 604, wherein:

[0097] The sending module 602 is used to send a query instruction to the powered-on chip to be tested, which is in a low level state.

[0098] The determination module 604 is used to determine that the signal channel corresponding to the chip under test is successfully connected when the status parameter returned by the chip under test is received; if the status parameter returned by the chip under test is not received, determine that the signal channel corresponding to the chip under test is unsuccessfully connected.

[0099] In one embodiment, the device further includes: a detection module.

[0100] The detection module is used to detect the state parameters of the ground line corresponding to each clock signal; when the state parameters of the ground line are detected to be in a low level state, it is determined that the link connection corresponding to the clock signal is successful; when the state parameters of the ground line are detected to be in a high impedance state, it is determined that the link connection corresponding to the clock signal fails.

[0101] In one embodiment, Figure 7 As shown, an interface signal loopback test device is provided, including: a setting module 702, a sending module 704 and a determining module 706, wherein:

[0102] The setting module 702 is used to perform a low level setting operation on the pin corresponding to each clock signal channel of the chip to be tested, and then power on the chip to be tested.

[0103] The sending module 704 is used to send a query instruction to the chip to be tested.

[0104] The determination module 706 is used to determine that the signal channel corresponding to the chip under test is successfully connected when the status parameter returned by the chip under test is received; if the status parameter returned by the chip under test is not received, determine that the signal channel corresponding to the chip under test is unsuccessfully connected.

[0105] In one embodiment, the device further includes: a connection module.

[0106] The connection module is used to connect a resistor with a preset value to each clock signal channel, and to perform a ground connection operation on the pin corresponding to each clock signal channel.

[0107] In one embodiment, the device further includes: a detection module.

[0108] The detection module is used to detect the state parameters of the ground line corresponding to each clock signal; when the state parameters of the ground line are detected to be in a low level state, it is determined that the link connection corresponding to the clock signal is successful; when the state parameters of the ground line are detected to be in a high impedance state, it is determined that the link connection corresponding to the clock signal fails.

[0109] For the specific definition of the interface signal loopback test device, please refer to the definition of the interface signal loopback test method above, which will not be repeated here. Each module in the above-mentioned interface signal loopback test device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0110] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 8 As shown. The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, an interface signal loopback test method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a button, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0111] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0112] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the above-mentioned method embodiments when executing the computer program.

[0113] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0114] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An interface signal loopback test method, applied to a terminal device, the method include: Performing register configuration on the PCIE module inside the chip to be tested, and powering on the adjusted chip to be tested; wherein the register configuration refers to configuring the high and low levels of the circuit inside the chip to be tested; Sending a query command to the powered-on chip to be tested; the chip to be tested is installed in the terminal device and is in a low level state; In the case of receiving the status parameter returned by the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected; the signal channel corresponding to the chip to be tested includes a data signal channel and a clock signal channel; the clock signal channel includes a reference clock signal channel; wherein, when performing a loopback test on the data signal channel corresponding to the chip to be tested, the receiving signal and the transmitting signal are short-circuited to test whether the data signal channel is normal; when performing a loopback test on the reference clock signal channel corresponding to the chip to be tested, the reference clock signal is grounded to test whether the reference clock signal channel is normal; In the case where the status parameter returned by the chip under test is not received, it is determined that the signal channel corresponding to the chip under test fails to connect.

2. The method according to claim 1, It is characterized in that After sending the query instruction to the powered-on chip to be tested, the method further includes: Detecting a state parameter of a ground line corresponding to each clock signal; In the case where it is detected that the state parameter of the ground line is in a low level state, determining that the link corresponding to the clock signal is successfully connected; When it is detected that the state parameter of the ground line is in a high-impedance state, it is determined that the link connection corresponding to the clock signal fails.

3. The method according to claim 1, It is characterized in that The grounding operation of the reference clock signal comprises: A resistor with a preset value is externally connected to each reference clock signal channel; A pin corresponding to each reference clock signal channel is grounded.

4. The method according to claim 3, It is characterized in that The preset resistance is 50 ohms.

5. The method according to claim 1, It is characterized in that The grounding operation is used to set a low level on the outside of the pin corresponding to each reference clock signal channel.

6. An interface signal loopback test device, It is characterized in that The device comprises: A setting module is used to configure the registers of the PCIE module inside the chip to be tested, and to power on the adjusted chip to be tested; wherein the register configuration refers to configuring the high and low levels of the circuit inside the chip to be tested; A sending module, used for sending a query instruction to the powered-on chip to be tested; the chip to be tested is installed in a terminal device and is in a low level state; A determination module is used to determine that the signal channel corresponding to the chip to be tested is successfully connected when receiving the status parameters returned by the chip to be tested; the signal channel corresponding to the chip to be tested includes a data signal channel and a clock signal channel; the clock signal channel includes a reference clock signal channel; wherein, when a loopback test is performed on the data signal channel corresponding to the chip to be tested, the receiving signal and the transmitting signal are short-circuited to test whether the data signal channel is normal; when a loopback test is performed on the reference clock signal channel corresponding to the chip to be tested, the reference clock signal is grounded to test whether the reference clock signal channel is normal; if the status parameters returned by the chip to be tested are not received, it is determined that the signal channel corresponding to the chip to be tested has failed to connect.

7. The interface signal loopback test device according to claim 6, It is characterized in that The device also includes: A detection module is used to detect the state parameters of the ground line corresponding to each clock signal; when the state parameters of the ground line are detected to be in a low level state, it is determined that the link connection corresponding to the clock signal is successful; when the state parameters of the ground line are detected to be in a high impedance state, it is determined that the link connection corresponding to the clock signal fails.

8. The interface signal loopback test device according to claim 6, It is characterized in that The device also includes: The connection module is used to connect a resistor of a preset value to each reference clock signal channel; and to connect the pin corresponding to each reference clock signal channel to the ground.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program. It is characterized in that When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, It is characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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