Silicon-based integrated quantum chip, preparation and testing methods

Abstract

The present invention provides a silicon-based integrated quantum chip, preparation and testing method, which integrates superconducting nanowires above silicon waveguides, so that the superconducting nanowires and silicon waveguides form evanescent wave coupling through a silicon oxide covering layer, and waveguide-coupled on-chip single-photon detection can be realized; a higher evanescent wave absorption rate can be achieved through the silicon oxide covering layer located between the superconducting nanowires and the silicon waveguide, and the silicon oxide covering layer can act as a mask when growing superconducting nanowires to avoid damaging the silicon waveguide, so as to reduce the loss of the silicon waveguide; the silicon oxide covering layer with a smaller surface roughness after CMP can ensure the flatness of the superconducting nanowires, so as to reduce dark counts and improve quantum performance; a multi-channel silicon-based integrated quantum chip can be prepared. The present invention can achieve integration and scale, and reliably maintain the processing capability of high-fidelity single-photon signals.

Description

Technical Field

[0001] The present invention belongs to the field of quantum technology and relates to a silicon-based integrated quantum chip and a preparation and testing method. Background Art

[0002] Quantum chips integrate quantum circuits on a substrate to carry the function of quantum information processing. In recent years, many experiments have proved that quantum information processing has obvious advantages over traditional computers in solving certain computing problems, and the key to further expanding this advantage lies in whether it can be integrated and scaled. Traditional photon detectors require the cumbersome step of coupling photons to off-chip detectors through waveguide gratings, which is difficult to meet the needs of integration and scale.

[0003] Silicon-on-insulator (SOI) technology, with its rich active and passive devices, mature processing technology, and excellent compatibility, has always been the mainstream material system for large-scale integrated research. Therefore, applying silicon-based chips to the quantum field has become a hot topic in the current silicon-based integrated quantum chip research field. However, how to achieve integration, scale, and maintain high-fidelity single-photon signal processing capabilities has always been a challenge.

[0004] Therefore, it is necessary to provide a silicon-based integrated quantum chip, preparation and testing methods. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a silicon-based integrated quantum chip, preparation and testing methods, which are used to solve the problem that photon detectors in the prior art are difficult to integrate and scale.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a silicon-based integrated quantum chip, comprising the following steps:

[0007] Providing an SOI substrate, wherein the SOI substrate comprises a bottom silicon layer, a silicon oxide insulating layer and a top silicon layer stacked in sequence from bottom to top;

[0008] patterning the top silicon layer to form a silicon waveguide;

[0009] forming a silicon oxide capping layer covering the silicon waveguide;

[0010] A superconducting nanowire is formed on the silicon oxide capping layer, and the superconducting nanowire and the silicon waveguide form evanescent wave coupling through the silicon oxide capping layer.

[0011] Optionally, the step of forming the silicon oxide capping layer comprises:

[0012] forming a silicon oxide covering layer covering the silicon waveguide on a surface of the silicon waveguide;

[0013] The silicon oxide capping layer is thinned so that the thickness of the silicon oxide capping layer on the silicon waveguide is 20 nm to 50 nm, and the surface roughness of the silicon oxide capping layer is less than 1 nm.

[0014] Optionally, the material of the superconducting nanowire is NbN, Nb, TaN, MoSi, MoGe, NbTiN or WSi, and the thickness of the superconducting nanowire is 5 nm to 10 nm.

[0015] Optionally, the silicon-based integrated quantum chip includes N silicon waveguides, where N≥2 and is an integer.

[0016] The present invention also provides a silicon-based integrated quantum chip, the silicon-based integrated quantum chip comprising:

[0017] bottom silicon layer;

[0018] a silicon oxide insulating layer, the silicon oxide insulating layer being located on the bottom silicon layer;

[0019] A silicon waveguide, wherein the silicon waveguide is located on the silicon oxide insulating layer;

[0020] a silicon oxide covering layer, wherein the silicon oxide covering layer covers the silicon waveguide;

[0021] A superconducting nanowire is located on the silicon oxide capping layer, and the superconducting nanowire forms evanescent wave coupling with the silicon waveguide through the silicon oxide capping layer.

[0022] Optionally, the silicon oxide capping layer on the silicon waveguide has a thickness of 20 nm to 50 nm.

[0023] Optionally, the surface roughness of the silicon oxide capping layer is less than 1 nm.

[0024] Optionally, the superconducting nanowire is a NbN superconducting nanowire, a Nb superconducting nanowire, a TaN superconducting nanowire, a MoSi superconducting nanowire, a MoGe superconducting nanowire, a NbTiN superconducting nanowire or a WSi superconducting nanowire; the thickness of the superconducting nanowire is 5nm to 10nm, and the morphology of the superconducting nanowire includes a tortuous and meandering shape.

[0025] Optionally, the silicon-based integrated quantum chip includes N silicon waveguides, where N≥2 and is an integer.

[0026] The present invention also provides a method for testing a silicon-based integrated quantum chip, comprising the following steps:

[0027] Providing any of the above silicon-based integrated quantum chips;

[0028] Providing an optical fiber array, the optical fiber array comprising an upper cover plate, a lower cover plate and optical fibers, the number of the optical fibers corresponding to the silicon waveguide;

[0029] The optical fiber is coupled to the corresponding silicon waveguide, and the input optical signal is coupled into the silicon-based integrated quantum chip in a low-temperature constant temperature cavity with a temperature less than 2K, and the output optical signal is absorbed by the heterogeneously integrated superconducting nanowire and converted into an electrical signal for output.

[0030] As described above, the silicon-based integrated quantum chip, preparation and testing method of the present invention integrates superconducting nanowires above silicon waveguides, so that superconducting nanowires and silicon waveguides form evanescent wave coupling through a silicon oxide covering layer, and waveguide-coupled on-chip single-photon detection can be realized; a higher evanescent wave absorption rate can be achieved through the silicon oxide covering layer located between the superconducting nanowires and the silicon waveguide, and the silicon oxide covering layer can act as a mask when growing superconducting nanowires to avoid damaging the silicon waveguide, so as to reduce the loss of the silicon waveguide; the silicon oxide covering layer with a smaller surface roughness after CMP can ensure the flatness of the superconducting nanowires, so as to reduce dark counts and improve quantum performance; a multi-channel silicon-based integrated quantum chip can be prepared. The present invention can achieve integration and scale, and reliably maintain the processing capability of high-fidelity single-photon signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Shown is a schematic diagram of the process flow for preparing a silicon-based integrated quantum chip in the present invention.

[0032] Figure 2 Shown is a schematic diagram of the structure of the silicon-based integrated quantum chip in the present invention.

[0033] Figure 3 It is a schematic diagram of the structure after the silicon waveguide is formed in the present invention.

[0034] Figure 4 It is a schematic diagram of the structure after forming a silicon oxide capping layer in the present invention.

[0035] Figure 5 It is a schematic diagram of the structure after the silicon oxide capping layer is thinned in the present invention.

[0036] Figure 6 Display as Figure 2 Schematic diagram of the cross-sectional structure of the silicon-based integrated quantum chip along A-A'.

[0037] Figure 7a Shown is a schematic diagram of the top view of the optical fiber array in the present invention.

[0038] Figure 7b Shown is a side view schematic diagram of the optical fiber array in the present invention.

[0039] Figure 7c Display as Figure 7b Schematic diagram of the cross-sectional structure of the optical fiber array along BB'.

[0040] Component number description

[0041] 101 Bottom silicon layer

[0042] 102 Silicon oxide insulating layer

[0043] 103 Silicon Waveguide

[0044] 104 Silicon oxide capping layer

[0045] 105 Superconducting Nanowires

[0046] 201 Fiber Optic

[0047] 202 Upper cover

[0048] 203 Lower cover

[0049] d Thickness DETAILED DESCRIPTION

[0050] With the development of advanced micromachining technology, superconducting nanowires such as niobium nitride (NbN) films can be deposited on the surfaces of different materials. The inventors have found that integrating superconducting nanowires with silicon-based waveguides can produce waveguide evanescent wave-coupled superconducting nanowire single-photon detectors (SNSPDs) to form silicon-based integrated quantum chips. The silicon-based integrated quantum chips are distinguishable from traditional vertically incident superconducting single-photon detectors and off-chip photon detectors. The detection method using waveguide evanescent wave absorption can eliminate the tedious step of coupling photons from waveguide gratings to off-chip detectors, thereby achieving highly integrated on-chip single-photon detection, thereby achieving integration and scale, and maintaining high-fidelity single-photon signal processing capabilities.

[0051] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0053] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

[0054] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0055] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0056] See also Figure 1 This embodiment provides a method for preparing a silicon-based integrated quantum chip, comprising the following steps:

[0057] Providing an SOI substrate, wherein the SOI substrate comprises a bottom silicon layer, a silicon oxide insulating layer and a top silicon layer stacked in sequence from bottom to top;

[0058] patterning the top silicon layer to form a silicon waveguide;

[0059] forming a silicon oxide capping layer covering the silicon waveguide;

[0060] A superconducting nanowire is formed on the silicon oxide capping layer, and the superconducting nanowire and the silicon waveguide form evanescent wave coupling through the silicon oxide capping layer.

[0061] The method for preparing the silicon-based integrated quantum chip of this embodiment integrates the superconducting nanowire on top of the silicon waveguide, so that the superconducting nanowire and the silicon waveguide form evanescent wave coupling through the silicon oxide covering layer, which can realize on-chip single-photon detection of waveguide coupling, thereby realizing integration; a higher evanescent wave absorption rate can be achieved through the silicon oxide covering layer located between the superconducting nanowire and the silicon waveguide, and the silicon oxide covering layer can act as a mask when growing the superconducting nanowire to avoid damaging the silicon waveguide, so as to reduce the loss of the Si waveguide, so as to maintain the processing capability of high-fidelity single-photon signals.

[0062] See also Figure 2 to Figure 6 , which is a schematic diagram of the structure presented in each step of preparing the silicon-based integrated quantum chip in this embodiment.

[0063] For details, see Figure 2 In this embodiment, a silicon-based integrated quantum chip is provided. The silicon-based integrated quantum chip is a silicon-based integrated quantum chip with two input ends, that is, it includes two silicon waveguides 103, wherein the silicon-based integrated quantum chip uses grating coupling to couple the input optical signal from the silicon waveguide 103 on the left into the silicon-based integrated quantum chip, and after quantum interference occurs in the middle straight waveguide region, the output optical signal is absorbed by the heterogeneously integrated superconducting nanowire 105 through the silicon waveguide 103, and converted into an electrical signal output. Among them, the two silicon waveguides 103 are matched with the optical fiber array to realize the input of the optical signal, and the spacing between the two silicon waveguides 103 at the input end is 250μm. However, the specific structure of the silicon-based integrated quantum chip is not limited to this. The specific layout, morphology, number, etc. of the silicon waveguides can be adjusted accordingly as needed, and no excessive restrictions are made here. It can be understood that Figure 2 The relative position relationship between the silicon waveguide 103 and the superconducting nanowire 105 in the silicon-based integrated quantum chip is only shown in the figure. Therefore, the silicon oxide covering layer 104 between the silicon waveguide 103 and the superconducting nanowire 105 is not fully shown. Figure 3 to Figure 6 sectional structure diagram for understanding.

[0064] See also Figure 6 , displayed as Figure 2 The specific preparation steps of the silicon-based integrated quantum chip include:

[0065] First, see Figure 3 , providing an SOI substrate, wherein the SOI substrate includes a bottom silicon layer 101, a silicon oxide insulating layer 102 and a top silicon layer stacked in sequence from bottom to top, and patterning the top silicon layer to form a silicon waveguide 103.

[0066] Specifically, in this embodiment, the SOI substrate uses a 4-inch SOI wafer, and uses CMOS micromachining technology, such as electron beam exposure (EBL) and induced coupled plasma (ICP) technology to etch the top silicon layer to form the silicon waveguide 103. The silicon oxide insulating layer 102 in the SOI substrate can be directly used as the cladding of the silicon waveguide 103. Since the top silicon layer in the SOI substrate is used as the core layer, that is, the silicon waveguide 103, the refractive index n of the silicon waveguide 103 as the core layer is about 3.47, which has a large refractive index difference with the refractive index n of the silicon oxide insulating layer 102 as the cladding layer, which is about 1.45. Therefore, the waveguide device made of the SOI substrate as a material can have an extremely small size, which is conducive to large-scale integration of the device. The preparation and selection of the substrate are not limited to this.

[0067] Next, see Figure 4 and Figure 5 , forming a silicon oxide covering layer 104 covering the silicon waveguide 103.

[0068] As an example, the steps of forming the silicon oxide capping layer 104 include:

[0069] Forming a silicon oxide covering layer 104 covering the silicon waveguide 103 on the surface of the silicon waveguide 103;

[0070] The silicon oxide capping layer 104 is thinned so that the thickness d of the silicon oxide capping layer 104 on the silicon waveguide 103 is 20 nm to 50 nm, and the surface roughness of the silicon oxide capping layer 104 is less than 1 nm.

[0071] Specifically, Figure 4 As shown, a plasma enhanced chemical vapor deposition (PECVD) process can be used to first deposit a layer of the silicon oxide capping layer 104 with a thickness of 300nm to 10μm on the surface of the silicon waveguide, such as a value in any range of 300nm, 400nm, 500nm, 1μm, 5μm and 10μm, but not limited thereto; Next, refer to Figure 5, the silicon oxide capping layer 104 can be thinned by chemical mechanical polishing (CMP), so that the thickness d of the silicon oxide capping layer 104 located on the silicon waveguide 103 is 20nm to 50nm, such as 20nm, 30nm, 50nm, etc., but not limited to this. Among them, it is preferred that the thickness d of the silicon oxide capping layer 104 is 50nm, so that the silicon oxide capping layer 104 can play a good role in evanescent wave coupling, and can protect the silicon waveguide 103 to avoid damage to the silicon waveguide 103 when preparing the superconducting nanowire 105, and the thinner silicon oxide capping layer 104 can reduce stress problems and avoid adverse effects such as cracks. It is preferred that the surface roughness of the silicon oxide capping layer 104 after thinning is less than 1 nm, such as a value within any range of 0.2 nm, 0.5 nm, 0.8 nm, etc., but not limited thereto, so as to provide a relatively flat silicon oxide capping layer 104, so as to facilitate the subsequent formation of the superconducting nanowire 105 with good quality. In this embodiment, PECVD is used for deposition, and CMP is used for thinning, but the preparation process for forming the silicon oxide capping layer 104 is not limited thereto, and can be selected according to needs. Among them, the thickness of the silicon oxide capping layer 104 located on the silicon waveguide 103 is 50 nm, and the surface roughness of the silicon oxide capping layer 104 is 0.5 nm, so that the silicon oxide capping layer 104 can be used as the upper cladding layer of the silicon waveguide 103, and a higher evanescent wave absorption rate can be achieved, and the silicon oxide capping layer 104 can act as a mask when growing the superconducting nanowire 105 to avoid damaging the silicon waveguide 103, so as to reduce the loss of the silicon waveguide 103. The silicon oxide capping layer 104 with a smaller surface roughness after CMP can ensure the flatness of the superconducting nanowire 105 to reduce dark counts and improve quantum performance.

[0072] Next, referring to FIG. 6 , the superconducting nanowire 105 is formed on the silicon oxide capping layer 104 , and the superconducting nanowire 105 and the silicon waveguide 103 form evanescent wave coupling through the silicon oxide capping layer 104 .

[0073] As an example, the material of the superconducting nanowire 105 includes but is not limited to NbN, Nb, TaN, MoSi, MoGe, NbTiN or WSi. The material of the superconducting nanowire 105 can be selected according to needs.

[0074] As an example, the thickness of the superconducting nanowire 105 includes but is not limited to 5 nm to 10 nm; the width of the superconducting nanowire 105 includes but is not limited to 50 nm to 150 nm; the morphology of the superconducting nanowire 105 includes but is not limited to a zigzag shape.

[0075] Specifically, a superconducting nanowire material layer is formed first, and then the pattern of the superconducting nanowire 105 can be transferred to the superconducting nanowire material layer by electron beam exposure (EBL) and reactive ion etching (RIE) to obtain the patterned superconducting nanowire 105 .

[0076] The width of the superconducting nanowire 105 may be 50nm to 150nm, such as any value in the range of 50nm, 80nm, 100nm, 150nm, etc., but not limited thereto; the thickness of the superconducting nanowire 105 may be 5nm to 10nm, such as any value in the range of 5nm, 6nm, 7nm, 8nm, 9nm and 10nm, etc., but not limited thereto. The morphology of the superconducting nanowire 105 may be a zigzag shape, and each bend of the superconducting nanowire 105 may be a right angle or a U-shaped turn. Preferably, in this embodiment, the material of the superconducting nanowire 105 is NbN, its width is 100nm, its thickness is 7nm, and it is a zigzag shape. Of course, in other embodiments, the material, size and shape of the superconducting nanowire 105 can be changed according to actual needs, and are not limited to the listed cases.

[0077] In this embodiment, the superconducting nanowire 105 is integrated above the silicon waveguide 103, so that the superconducting nanowire 105 and the silicon waveguide 103 form evanescent wave coupling through the silicon oxide capping layer 104, which can realize on-chip single photon detection by waveguide coupling, thereby improving chip integration and reducing device size.

[0078] As an example, the silicon-based integrated quantum chip may include N silicon waveguides, where N is greater than or equal to 2 and is an integer, such as 4, 8, etc., so as to prepare a multi-channel silicon-based integrated quantum chip to further achieve device integration and scale. It can be understood that when the silicon waveguide 103 is multi-channel, the corresponding light array needs to be adaptively improved to form an optical fiber that can be aligned with the silicon waveguide 103.

[0079] See also Figure 2 and Figure 6 This embodiment also provides a silicon-based integrated quantum chip, which can be prepared by the above-mentioned preparation method, but is not limited thereto. In this embodiment, the silicon-based integrated quantum chip is directly prepared by the above-mentioned preparation process, so the preparation, structure, material, etc. of the silicon-based integrated quantum chip can refer to the above-mentioned embodiment.

[0080] Specifically, the silicon-based integrated quantum chip includes a bottom silicon layer 101, a silicon oxide insulating layer 102, a silicon waveguide 103, a silicon oxide capping layer 104 and a superconducting nanowire 105; wherein the silicon oxide insulating layer 104 is located on the bottom silicon layer 101, the silicon wave 103 is located on the silicon oxide insulating layer 104, the silicon oxide capping layer 104 covers the silicon waveguide 103, the superconducting nanowire 105 is located on the silicon oxide capping layer 104, and the superconducting nanowire 105 and the silicon waveguide 103 form evanescent wave coupling through the silicon oxide capping layer 104.

[0081] As an example, the thickness of the silicon oxide capping layer 104 on the silicon waveguide 103 is 20 nm to 50 nm, such as a value within any range of 20 nm, 30 nm, 50 nm, etc., but is not limited thereto.

[0082] Among them, the thickness d of the silicon oxide capping layer 104 is preferably 50 nm, so that the silicon oxide capping layer 104 can play a good role in evanescent wave coupling, and can protect the silicon waveguide 103 to avoid damage to the silicon waveguide 103 when preparing the superconducting nanowire 105. The thinner silicon oxide capping layer 104 can reduce stress problems and avoid adverse effects such as cracks.

[0083] As an example, the surface roughness of the silicon oxide capping layer 104 is less than 1 nm, such as a value within any range of 0.2 nm, 0.5 nm, 0.8 nm, etc., but not limited thereto, so as to provide a relatively flat silicon oxide capping layer 104 and facilitate the formation of the superconducting nanowires 105 with better quality.

[0084] As an example, the superconducting nanowire 105 includes but is not limited to NbN superconducting nanowire, Nb superconducting nanowire, TaN superconducting nanowire, MoSi superconducting nanowire, MoGe superconducting nanowire, NbTiN superconducting nanowire or WSi superconducting nanowire; the type of the superconducting nanowire 105 can be selected according to needs.

[0085] As an example, the thickness of the superconducting nanowire 105 includes but is not limited to 5 nm to 10 nm; the width of the superconducting nanowire 105 includes but is not limited to 50 nm to 150 nm; the morphology of the superconducting nanowire 105 includes but is not limited to a zigzag shape.

[0086] Specifically, the width of the superconducting nanowire 105 can be 50nm to 150nm, such as 50nm, 80nm, 100nm, 150nm, etc., but not limited to this; the thickness of the superconducting nanowire 105 can be 5nm to 10nm, such as 5nm, 6nm, 7nm, 8nm, 9nm and 10nm, etc., but not limited to this. The morphology of the superconducting nanowire 105 can be a zigzag shape, and each bend of the superconducting nanowire 105 can be a right angle or a U-shaped turn. Preferably, in this embodiment, the superconducting nanowire 105 is a NbN superconducting nanowire with a width of 100nm and a thickness of 7nm, and adopts a zigzag shape. Of course, in other embodiments, the type, size and shape of the superconducting nanowire 105 can be changed according to actual needs and are not limited to the listed cases.

[0087] This embodiment also provides a method for testing a silicon-based integrated quantum chip, comprising the following steps:

[0088] Providing the above-mentioned silicon-based integrated quantum chip;

[0089] Providing an optical fiber array, the optical fiber array comprising an upper cover plate, a lower cover plate and optical fibers, the number of the optical fibers corresponding to the silicon waveguide;

[0090] The optical fiber is coupled to the corresponding silicon waveguide, and the input optical signal is coupled into the silicon-based integrated quantum chip in a low-temperature constant temperature cavity with a temperature less than 2K, and the output optical signal is absorbed by the heterogeneously integrated superconducting nanowire and converted into an electrical signal for output.

[0091] For details, see Figure 7a to Figure 7c , showing a homemade fiber array, in which Figure 7c Display as Figure 7bSchematic diagram of the cross-sectional structure of the optical fiber array along B-B'. The optical fiber array includes an upper cover plate 202, a lower cover plate 203 and two optical fibers 201, wherein the number M of the optical fibers 201 can be adjusted according to the specific number of the silicon waveguides 103 in the silicon-based integrated quantum chip, so that the optical fibers 201 are aligned and coupled with the silicon waveguides 103, wherein the value of M can be an integer of M≥2, such as 4, 8, etc. Further, a packaging box can be prepared to achieve precise alignment of the optical fiber with the silicon-based integrated quantum chip. In this embodiment, since the silicon-based integrated quantum chip includes two silicon waveguides 103, the optical fiber array includes two optical fibers 201, and the distance between the two optical fibers 201 is set to 250μm to match the silicon waveguide 103 and achieve good alignment for input of optical signals. During the test, the silicon-based integrated quantum chip needs to be tested in a low-temperature constant temperature chamber with a temperature less than 2K to ensure the normal operation of the superconducting nanowire 105. The distribution and setting of the test equipment can refer to the existing equipment and will not be introduced here.

[0092] In summary, the silicon-based integrated quantum chip, preparation and testing method of the present invention integrates superconducting nanowires above silicon waveguides, so that superconducting nanowires and silicon waveguides form evanescent wave coupling through a silicon oxide covering layer, and waveguide-coupled on-chip single-photon detection can be realized; a higher evanescent wave absorption rate can be achieved through the silicon oxide covering layer located between the superconducting nanowires and the silicon waveguide, and the silicon oxide covering layer can act as a mask when growing superconducting nanowires to avoid damaging the silicon waveguide, so as to reduce the loss of the silicon waveguide; the silicon oxide covering layer with a smaller surface roughness after CMP can ensure the flatness of the superconducting nanowires, so as to reduce dark counts and improve quantum performance; a multi-channel silicon-based integrated quantum chip can be prepared. The present invention can achieve integration and scale, and reliably maintain the processing capability of high-fidelity single-photon signals.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a silicon-based integrated quantum chip, characterized in that: The following steps are involved: Providing an SOI substrate, wherein the SOI substrate comprises a bottom silicon layer, a silicon oxide insulating layer and a top silicon layer stacked in sequence from bottom to top; Patterning the top silicon layer to form a silicon waveguide, wherein the step of forming the silicon oxide capping layer comprises: forming a silicon oxide covering layer covering the silicon waveguide on a surface of the silicon waveguide; Thinning the silicon oxide covering layer so that the thickness of the silicon oxide covering layer on the silicon waveguide is 20 nm to 50 nm, and the surface roughness of the silicon oxide covering layer is less than 1 nm; forming a silicon oxide capping layer covering the silicon waveguide; A superconducting nanowire is formed on the silicon oxide capping layer, and the superconducting nanowire and the silicon waveguide form evanescent wave coupling through the silicon oxide capping layer.

2. The method for preparing a silicon-based integrated quantum chip according to claim 1, characterized in that: The material of the superconducting nanowire is NbN, Nb, TaN, MoSi, MoGe, NbTiN or WSi.

3. The method for preparing a silicon-based integrated quantum chip according to claim 1, characterized in that: The silicon-based integrated quantum chip includes N silicon waveguides, where N is ≥ 2 and is an integer.

4. A silicon-based integrated quantum chip, characterized in that: The silicon-based integrated quantum chip comprises: bottom silicon layer; a silicon oxide insulating layer, the silicon oxide insulating layer being located on the bottom silicon layer; A silicon waveguide, wherein the silicon waveguide is located on the silicon oxide insulating layer; A silicon oxide covering layer, wherein the silicon oxide covering layer covers the silicon waveguide, the thickness of the silicon oxide covering layer on the silicon waveguide is 20 nm to 50 nm, and the surface roughness of the silicon oxide covering layer is less than 1 nm; A superconducting nanowire is located on the silicon oxide capping layer, and the superconducting nanowire forms evanescent wave coupling with the silicon waveguide through the silicon oxide capping layer.

5. The silicon-based integrated quantum chip according to claim 4, characterized in that: The superconducting nanowire is a NbN superconducting nanowire, a Nb superconducting nanowire, a TaN superconducting nanowire, a MoSi superconducting nanowire, a MoGe superconducting nanowire, a NbTiN superconducting nanowire or a WSi superconducting nanowire; the thickness of the superconducting nanowire is 5nm-10nm, and the morphology of the superconducting nanowire includes a tortuous and sinuous shape.

6. The silicon-based integrated quantum chip according to claim 4, characterized in that: The silicon-based integrated quantum chip includes N silicon waveguides, where N is ≥ 2 and is an integer.

7. A method for testing a silicon-based integrated quantum chip, characterized in that: The following steps are involved: Providing a silicon-based integrated quantum chip as described in any one of claims 4 to 6; Providing an optical fiber array, the optical fiber array comprising an upper cover plate, a lower cover plate and optical fibers, the number of the optical fibers corresponding to the silicon waveguide; The optical fiber is coupled to the corresponding silicon waveguide, and the input optical signal is coupled into the silicon-based integrated quantum chip in a low-temperature constant temperature cavity with a temperature less than 2K, and the output optical signal is absorbed by the heterogeneously integrated superconducting nanowire and converted into an electrical signal for output.

Images