Chip components

Abstract

The present invention provides a chip component, which includes: a substrate having a first surface and a second surface on the opposite side thereof; a plurality of wall portions, which are formed on the first surface side using a portion of the substrate, have one end and the other end, and the wall portion is formed by a plurality of column units; a support portion, which is formed around the wall portion using a portion of the substrate and is connected to at least one of the one end and the other end of the wall portion; and a capacitor portion formed according to the surface of the wall portion, each of the column units including a central portion and three convex portions extending from the central portion in three different directions when viewed from above, and the wall portion is formed by connecting the convex portions of adjacent column units to each other. Thus, the miniaturization of the element and the enlargement of the capacitance portion can be achieved.

Description

Technical Field

[0001] The present invention relates to a chip component having a capacitor portion. Background Art

[0002] Patent document 1 discloses a chip capacitor including: a substrate; a first conductor film and a first pad film formed on the substrate; a dielectric film formed on the first conductor film and the first pad film; and a second conductor film including a second connection region and a second capacitor formation region formed on the dielectric film. The first conductor film includes a first connection region and a first capacitor formation region. A first external electrode is bonded to the first connection region of the first conductor film, and a second external electrode is bonded to the second connection region of the second conductor film.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent document 1: Japanese Patent Application Publication No. 2017-195322. Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] The chip capacitor of patent document 1 has a capacitance region of a specified capacity. The structure forming the capacitance region is a laminated film of a first conductor film, a dielectric film and a second conductor film formed on a substrate. Therefore, the capacity of the capacitance region is limited by the planar size of the substrate. Therefore, it is difficult to simultaneously achieve both miniaturization of the maintenance element and high capacitance of the capacitor.

[0008] An object of the present invention is to provide a chip component capable of achieving both miniaturization of an element and increase in the capacity of a capacitor portion.

[0009] Technical solutions to the problem

[0010] A chip component according to one aspect of the present invention includes: a substrate having a first surface and a second surface on the opposite side thereof; a plurality of wall portions, which are formed on the first surface side using a portion of the substrate, have one end and the other end, and the wall portion is formed by a plurality of column units; a supporting portion, which is formed around the wall portion using a portion of the substrate and is connected to at least one of the one end and the other end of the wall portion; and a capacitor portion formed along the surface of the wall portion, each of the column units including a central portion and three convex portions extending from the central portion in three different directions when viewed from above, and the wall portion is formed by connecting the convex portions of adjacent column units to each other.

[0011] Effects of the Invention

[0012] According to a chip component of one aspect of the present invention, the wall portion formed on the substrate is formed by a plurality of column units. Each column unit includes a central portion and three convex portions extending from the central portion to three different directions when viewed from above. Thus, compared to the situation where the wall portion is composed of a connection of column units such as a quadrangular prism, the surface area of ​​the wall portion can be expanded. In addition, because the capacitor portion is formed according to the surface of the wall portion, the capacity of the capacitor portion is not limited by the planar size of the substrate, and it is possible to achieve large capacity by increasing the height of the wall portion. In other words, even if the planar size of the substrate is relatively small, the capacity of the capacitor portion can be largely ensured, so both the miniaturization of the element and the large capacity of the capacitor portion can be achieved.

[0013] In addition, the wall portion formed by connecting a plurality of column units has better stability than mutually independent column units. Furthermore, at least one of one end portion and the other end portion of the wall portion is connected to a supporting portion around the wall portion. Thus, the wall portion can be supported at least from the side, thereby strengthening the lateral force applied to the wall portion. As a result, the stability of the wall portion can be maintained even if the height of the wall portion is increased, so the reliability of the element can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic perspective view of the chip component according to the first embodiment of the present invention.

[0015] Figure 2 It is a schematic plan view of the chip component according to the first embodiment of the present invention.

[0016] Figure 3 It is a top view showing the internal structure of the above-mentioned chip component.

[0017] Figure 4 yes Figure 3 An enlarged view of the main parts of the chip components.

[0018] Figure 5 This is a schematic cross-sectional view of the chip component according to the first embodiment of the present invention.

[0019] Figure 6A to Figure 6L It is a diagram showing a part of the manufacturing process of the chip component according to the first embodiment of the present invention.

[0020] Figure 7 This is an enlarged view of a main part of a chip component according to a second embodiment of the present invention.

[0021] Figure 8 Is Figure 7 This is an enlarged view of the portion surrounded by the two-dot chain line VIII.

[0022] Figures 9A to 9F It is a diagram showing a part of the manufacturing process of the chip component according to the second embodiment of the present invention.

[0023] Fig.10 It is a schematic cross-sectional view of a chip component according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0024] First, the embodiments of the present invention are listed for explanation. A chip component of one embodiment of the present invention includes: a substrate having a first surface and a second surface on the opposite side thereof; a plurality of wall portions, which are formed on the first surface side using a portion of the substrate, have one end and the other end, and the wall portion is formed by a plurality of column units; a support portion, which is formed around the wall portion using a portion of the substrate and is connected to at least one of the one end and the other end of the wall portion; and a capacitor portion formed according to the surface of the wall portion, each of the column units including a central portion and three convex portions extending from the central portion in three different directions when viewed from above, and the wall portion is formed by connecting the convex portions of adjacent column units to each other.

[0025] According to this structure, the wall portion formed on the substrate is formed by a plurality of column units. Each column unit includes a central portion and three convex portions extending from the central portion to three different directions when viewed from above. Thus, compared to the situation where the wall portion is composed of a connection of column units such as a quadrangular prism, the surface area of ​​the wall portion can be expanded. In addition, because the capacitor portion is formed according to the surface of the wall portion, the capacity of the capacitor portion is not limited by the planar size of the substrate, and it is possible to achieve large capacity by increasing the height of the wall portion. In other words, even if the planar size of the substrate is small, the capacity of the capacitor portion can be ensured to be large, so both the miniaturization of the element and the large capacity of the capacitor portion can be achieved.

[0026] In addition, the wall portion formed by connecting a plurality of column units has better stability than mutually independent column units. Furthermore, at least one of one end portion and the other end portion of the wall portion is connected to a supporting portion around the wall portion. Thus, the wall portion can be supported at least from the side, thereby strengthening the lateral force applied to the wall portion. As a result, the stability of the wall portion can be maintained even if the height of the wall portion is increased, so the reliability of the element can be improved.

[0027] In the chip component according to one embodiment of the present invention, in each of the column units, each of the protrusions forms an angle of 120° with the adjacent protrusions and intersects with the adjacent protrusions at the center portion.

[0028] According to this structure, no matter which direction a force is applied to the wall, at least one of the three protrusions can also play the role of a control wall to prevent the wall from collapsing. As a result, the stability of the wall can be further improved.

[0029] In a chip component of one embodiment of the present invention, the first wall portion among the multiple wall portions includes: a first main portion, which extends in a first direction and is connected to the above-mentioned supporting portion; and a first branch portion, which extends in a second direction intersecting the above-mentioned first direction and is arranged in a comb-tooth shape along the above-mentioned first direction, and each of the above-mentioned first branches is formed by a first protrusion among the above-mentioned protrusions of each of the above-mentioned column units of the above-mentioned first wall portion.

[0030] In a chip component of one embodiment of the present invention, the above-mentioned protrusion of each of the above-mentioned column units of the above-mentioned first wall portion also includes a second protrusion and a third protrusion in addition to the above-mentioned first protrusion, and the above-mentioned first main portion is formed by connecting the above-mentioned second protrusion and the above-mentioned third protrusion of adjacent above-mentioned column units.

[0031] In a chip component of one embodiment of the present invention, the plurality of wall portions include a second wall portion adjacent to the first wall portion, and the second wall portion includes: a second main portion extending along the first direction and connected to the supporting portion; and a comb-tooth-shaped second branch portion extending toward the first main portion and engaging with the comb-tooth-shaped first branch portion, and each of the second branches is formed by a fourth protrusion among the protrusions of each of the column units of the second wall portion.

[0032] In a chip component of one embodiment of the present invention, the above-mentioned protrusions of each of the above-mentioned column units of the above-mentioned second wall portion also include a fifth protrusion and a sixth protrusion in addition to the above-mentioned fourth protrusion, and the above-mentioned second main portion is formed by connecting the above-mentioned fifth protrusion and the above-mentioned sixth protrusion of adjacent above-mentioned column units.

[0033] In the chip component according to one embodiment of the present invention, a ratio (W / H) of a width W of the convex portion of the column unit to a height H of the wall portion is 2 / 50 to 2 / 100.

[0034] According to this structure, since the height of the wall portion is relatively high, the capacitance of the capacitor portion can be further increased. Moreover, even if the height of the wall portion is increased in this way, since the wall portion is supported by the support portion, the stability of the wall portion can be maintained.

[0035] In the chip component according to one embodiment of the present invention, the support portion is formed in a ring shape surrounding the plurality of wall portions, and the wall portion includes one end portion and the other end portion connected to the support portion.

[0036] According to this structure, both one end and the other end of the wall portion are connected to the support portion, so that the wall portion can be supported from both sides. As a result, the stability of the wall portion can be further improved.

[0037] A chip component according to one embodiment of the present invention includes an insulating film formed on the surface of the wall portion, and the capacitor portion includes: a lower electrode formed on the insulating film; a capacitor film formed on the lower electrode; and an upper electrode formed on the capacitor film.

[0038] In the chip component according to one embodiment of the present invention, the upper electrode includes an embedded electrode embedded in a space between the adjacent wall portions.

[0039] In the chip component according to one embodiment of the present invention, the lower electrode and the upper electrode include polysilicon electrodes, and the capacitor film includes an oxide film.

[0040] In a chip component of one embodiment of the present invention, a first electrode film is formed on the above-mentioned substrate and electrically connected to the above-mentioned lower electrode; a second electrode film is formed on the above-mentioned substrate and electrically connected to the above-mentioned upper electrode; a surface insulating film covers the above-mentioned first electrode film and the above-mentioned second electrode film; a first external electrode is formed on the above-mentioned surface insulating film and passes through the above-mentioned surface insulating film and is electrically connected to the above-mentioned first electrode film; and a second external electrode is formed on the above-mentioned surface insulating film and passes through the above-mentioned surface insulating film and is electrically connected to the above-mentioned second electrode film.

[0041] In the chip component according to one embodiment of the present invention, the first electrode film is connected to the lower electrode in a region directly below the first external electrode.

[0042] In the chip component according to one embodiment of the present invention, the second electrode film is connected to the upper electrode in a region directly below the second external electrode.

[0043] In the chip component according to one embodiment of the present invention, the first electrode film and the second electrode film include aluminum electrode films.

[0044] In a chip component according to one embodiment of the present invention, the first external electrode and the second external electrode include a plating layer formed by plating growth.

[0045] In the chip component according to one embodiment of the present invention, the wall portion is formed in a region between the first external electrode and the second external electrode and in a region directly below the first external electrode and the second external electrode.

[0046] In a chip component according to one embodiment of the present invention, the lower electrode has a concavo-convex structure on a surface in contact with the capacitive film.

[0047] According to this structure, since the concavo-convex structure is formed on the lower electrode, the surface area of ​​the lower electrode can be increased. As a result, the lower electrode can be opposed to the upper electrode with a wider area, and the capacitance of the capacitor can be further increased.

[0048] In a chip component according to one embodiment of the present invention, the substrate includes a semiconductor substrate.

[0049] <Detailed description of embodiments of the present invention>

[0050] Next, embodiments of the present invention will be described in detail with reference to the drawings.

[0051] [First embodiment]

[0052] Figure 1 It is a schematic perspective view of the chip component 1 according to the first embodiment of the present invention. Figure 2 It is a schematic plan view of the chip component 1 according to the first embodiment of the present invention. Figure 3 It is a plan view showing the internal structure of the chip component 1. Figure 4 yes Figure 3 An enlarged view of the main parts of chip component 1. Figure 5 It is a schematic cross-sectional view of the chip component 1 according to the first embodiment of the present invention.

[0053] also, Figure 5 The cross-sectional structure of a main part of the chip component 1 is shown in order to facilitate understanding of the structure of the chip component 1 rather than showing the cross-sectional structure of a specific cut plane of the chip component 1 .

[0054] The chip component 1 is a chip capacitor independently equipped with a capacitance structure, and includes a substantially rectangular substrate 2 constituting the chip body. The substrate 2 may be a semiconductor substrate such as a silicon substrate, or an insulating substrate such as a ceramic substrate or a glass substrate. In the case of a semiconductor substrate, the substrate 2 may be a p-type substrate or an n-type substrate.

[0055] The length L of the long side of the substrate 2 along the longitudinal direction is, for example, 0.4 mm to 2 mm. The length D of the short side along the short direction is, for example, 0.2 mm to 2 mm. The thickness T of the substrate 2 is, for example, 0.1 mm to 0.5 mm.

[0056] The substrate 2 has a first surface 3, a second surface 4 located on the opposite side thereof, and a third surface 5 connecting the first surface 3 and the second surface 4. The first surface 3 and the second surface 4 of the substrate 2 are formed into a rectangular shape in a plan view (hereinafter referred to as a "plan view") viewed from the normal direction thereof.

[0057] The first surface 3, the second surface 4, and the third surface 5 of the substrate 2 may also be referred to as the front surface, the back surface, and the side surface of the substrate 2, respectively. In addition, in this embodiment, the third surface 5 is divided into a total of four surfaces, namely, one opposite surface facing each other in the long side direction of the substrate 2 and one opposite surface facing each other in the short side direction of the substrate 2, because the substrate 2 is formed into a rectangular shape when viewed from above. On the other hand, even if the substrate 2 is circular, elliptical, or rectangular when viewed from above, the third surface 5 may be chamfered at each corner (such as Figure 2 As shown, the case of having a rounded corner 6), with Figure 1 Different, may not be explicitly divided into multiple faces.

[0058] A first external electrode 7 and a second external electrode 8 are formed on the first surface 3 of the substrate 2. The first external electrode 7 is arranged at one end portion in the long side direction of the substrate 2. The second external electrode 8 is arranged at the other end portion in the long side direction of the substrate 2. The first external electrode 7 and the second external electrode 8 are both formed in a rectangular shape having a pair of long sides along the short side direction of the substrate 2 when viewed from above.

[0059] like Figure 3 and Figure 5 As shown, in the chip component 1, a portion of the substrate 2 on the first surface 3 side is selectively removed, so that the remaining portion of the substrate 2 forms a plurality of wall portions 9 and support portions 10.

[0060] The plurality of wall portions 9 extend in the short-side direction D1 (first direction) of the substrate 2. In this embodiment, the plurality of wall portions 9 extend from one side of a pair of peripheral edge portions (portions close to the third surface 5) along the long-side direction D2 (second direction) of the substrate 2 to the other side. In addition, the plurality of wall portions 9 are arranged at intervals from each other in the long-side direction D2 of the substrate 2. Thus, as shown in FIG. Figure 3 As shown, the plurality of wall portions 9 are formed in a strip shape in a plan view.

[0061] In addition, in this embodiment, the strip-shaped wall portion 9 is as shown in FIG. Figure 3 As shown in FIG. 1 , the strip-shaped wall portion 9 is formed in the region between the first external electrode 7 and the second external electrode 8, and in the region directly below the first external electrode 7 and the second external electrode 8. Therefore, in the thickness direction of the substrate 2, a part of the strip-shaped wall portion 9 is not opposite to the first external electrode 7 and the second external electrode 8, and the remaining part is opposite to the first external electrode 7 and the second external electrode 8. In addition, the strip-shaped wall portion 9 may be formed only in the region between the first external electrode 7 and the second external electrode 8. In this case, the first surface 3 of the substrate 2 in the region directly below the first external electrode 7 and the second external electrode 8 may also be a flat surface.

[0062] On the other hand, the support portion 10 in this embodiment is the remaining portion of the substrate 2 formed around the plurality of wall portions 9. In this embodiment, the portion formed in an annular (frame-shaped) shape along the third surface 5 of the substrate 2 is referred to as the support portion 10 as a whole, and the support portion 10 is not necessarily annular. For example, only the portion including a pair of third surfaces 5, 5 along the long side direction D2 of the substrate 2 and connected to one end 9A and / or the other end 9B of each wall portion 9 in the long side direction (extension direction) may be referred to as the support portion 10.

[0063] Reference Figure 3 The support portion 10 integrally includes: a first support portion 11 having a relatively narrow width; and a second support portion 12 having a relatively wider width than the first support portion 11. In this embodiment, the first support portion 11 is a pair of portions along the long side direction D2 of the substrate 2, and the second support portion 12 is a pair of portions along the short side direction D1 of the substrate 2, and they may be arranged opposite to each other.

[0064] Next, refer to Figure 4 and Figure 5 The structure of the wall portion 9 will be described specifically.

[0065] Reference Figure 4 , the wall 9 is formed of a plurality of columnar units 13. Here, "the wall 9 is formed of a plurality of columnar units 13" means, for example, that columns (the columnar units 13 in this embodiment) of the same shape are connected to form a linear wall 9 when viewed from above. In other words, the wall 9 itself is not formed in a columnar shape, but is formed in a linear shape. Figure 4 As shown by the dotted lines in the figure, the wall portion 9 can be divided into columnar units 13 of the same shape by imaginary lines. Therefore, the raw material portion (semiconductor portion in this embodiment) of the substrate 2 is continuous at the boundary between the convex portions 15 of the adjacent columnar units 13. Thus, the adjacent convex portions 15 are connected to each other via the raw material portion of the substrate 2 to form a whole.

[0066] Each column unit 13 includes a central portion 14 and three convex portions 15 extending in three different directions from the central portion 14 when viewed from above. The wall portion 9 is formed by connecting the convex portions 15 of adjacent column units 13. More specifically, in each column unit 13, each convex portion 15 forms angles θ1, θ2, and θ3 of 120° with the adjacent convex portions 15, and the adjacent convex portions 15 intersect in the central portion 14.

[0067] In addition, the angles θ1, θ2, and θ3 are 120°, which are equal to each other in this embodiment, but they may be different from each other. For example, the angle θ3 between the second convex portion 21 and the third convex portion 22 described later is 160°, and the angle θ1 between the first convex portion 20 and the second convex portion 21 and the angle θ2 between the first convex portion 20 and the third convex portion 22 are both 100°.

[0068] In this embodiment, a pair of wall portions 9 adjacent to each other among the plurality of wall portions 9 may be referred to as a first wall portion 16 and a second wall portion 17 .

[0069] The first wall portion 16 includes a first main portion 18 extending in the short-side direction D1 of the substrate 2 and connected to the support portion 10 (first support portion 11), and first branch portions 19 extending in the long-side direction D2 of the substrate 2 and arranged in a comb-teeth shape along the short-side direction D1 of the substrate 2. Each first branch portion 19 is formed by a first protrusion 20 in the protrusion 15 of each column unit 13 of the first wall portion 16.

[0070] On the other hand, the convex portion 15 of each column unit 13 of the first wall portion 16 further includes a second convex portion 21 and a third convex portion 22 in addition to the first convex portion 20. The first main portion 18 is formed by connecting the second convex portion 21 and the third convex portion 22 of the adjacent column units 13. That is, in this embodiment, the second convex portion 21 and the third convex portion 22 are alternately arranged along the short side direction D1 of the substrate 2, and as a whole, a first main portion 18 having a wave shape (sawtooth shape) is formed when viewed from above.

[0071] One end portion 9A and the other end portion 9B (at Figure 4 The convex portion 15 (not shown) is connected to the support portion 10 (first support portion 11). More specifically, the raw material portion (semiconductor portion in this embodiment) of the substrate 2 is continuous at the boundary between the support portion 10 and the first main portion 18. Thus, the support portion 10 and the first main portion 18 are connected to each other via the raw material portion of the substrate 2.

[0072] The second wall portion 17 includes: a second main portion 23 extending along the short side direction D1 of the substrate 2 and connected to the support portion 10 (first support portion 11); and comb-tooth-shaped second branch portions 24 extending toward the first main portion 18 and meshing with the comb-tooth-shaped first branch portions 19. Each second branch portion 24 is formed by a fourth protrusion among the protrusions 15 of each column unit 13 of the second wall portion 17.

[0073] On the other hand, the convex portion 15 of each column unit 13 of the second wall portion 17 further includes a fifth convex portion 26 and a sixth convex portion 27 in addition to the fourth convex portion 25. The second main portion 23 is formed by connecting the fifth convex portion 26 and the sixth convex portion 27 of the adjacent column units 13. That is, in this embodiment, the fifth convex portion 26 and the sixth convex portion 27 are alternately arranged along the short side direction D1 of the substrate 2, and as a whole, a second main portion 23 having a wave shape (sawtooth shape) is formed when viewed from above.

[0074] One end portion 9A and the other end portion 9B (at Figure 4The convex portion 15 (not shown) is connected to the support portion 10 (first support portion 11). More specifically, the raw material portion (semiconductor portion in this embodiment) of the substrate 2 is continuous at the boundary between the support portion 10 and the second main portion 23. Thus, the support portion 10 and the second main portion 23 are connected as one body via the raw material portion of the substrate 2.

[0075] Furthermore, in this embodiment, a pair of wall portions 9 consisting of a first wall portion 16 and a second wall portion 17 meshing in a comb-teeth shape are sequentially formed along the long side direction D2 of the substrate 2. That is, along the long side direction D2 of the substrate 2, the first wall portion 16 and the second wall portion 17 are alternately arranged. A gap 28 is formed between the first wall portion 16 and the second wall portion 17. The gap 28 is a portion where the raw material of the substrate 2 is removed and is surrounded by the wall portion 9 and the support portion 10. The width W1 of the gap 28 is, for example, 2μm to 8μm. In addition, in Figure 3 and Figure 4 In the figure, for the sake of clarity, the gap 28 is shaded.

[0076] In this embodiment, the gap 28 may include a first gap 29 and a second gap 30. The first gap 29 is formed between the first wall portion 16 and the second wall portion 17 meshing in a comb-tooth shape, and is formed in a zigzag shape. The second gap 30 is formed between the first wall portion 16 and the second wall portion 17 facing each other across the surface on the opposite side of the comb teeth, and is formed in a wave shape (sawtooth shape).

[0077] In addition, in this embodiment, if Figure 5 As shown in FIG. 1 , the ratio (W2 / H) of the width W2 of the convex portion 15 of the column unit 13 to the height H of the wall portion 9 (the depth of the gap 28) may be 2 / 50 to 2 / 100. Figure 4 As shown, it can be defined as the width in the direction perpendicular to the extending direction of each convex portion 15 from the central portion 14 .

[0078] Specifically, the width W2 of the convex portion 15 of the columnar unit 13 may be, for example, 2 μm to 8 μm. On the other hand, the height H of the wall portion 9 may be 50 μm to 400 μm.

[0079] Reference Figure 3 In the support portion 10, a plurality of convex portions 31 protruding toward the wall portion 9 may be formed in the second support portion 12 formed along the wall portion 9. The plurality of convex portions 31 extend toward the wall portion 9 and may be arranged to be aligned with the comb-shaped first branch portion 19 or the second branch portion 24 (in Figure 3 (not shown) meshing comb-like shape.

[0080] like Figure 1 and Figure 5As shown, an insulating film 32 is formed on the first surface 3 of the substrate 2 in a manner covering the entire area of ​​the first surface 3 of the substrate 2. The insulating film 32 is formed not only on the flat surface of the substrate 2, i.e., the first surface 3, but also on the entire surface (upper surface 34 and side surface 35) of the wall portion 9. The insulating film 32 has an end surface that is consistent with the third surface 5 of the substrate 2. The insulating film 32 may be, for example, a SiO2 film or a SiN film. The thickness of the insulating film 32 may be, for example, (2μm~4μm).

[0081] A capacitor portion 33 is formed on the insulating film 32. The capacitor portion 33 is formed in accordance with the upper surface 34 and the side surface 35 of the wall portion 9. In other words, the capacitor portion 33 has at least a lower electrode 36 having a concave-convex shape consistent with the width direction and the height direction of the wall portion 9. In this embodiment, the lower electrode 36 is formed on the insulating film 32 as an electrode film having a surface in contact with the upper surface 34 and the side surface 35 of the wall portion 9 and another surface located at an equal distance from the upper surface 34 and the side surface 35 of the wall portion 9. In other words, the lower electrode 36 has a certain thickness along the upper surface 34 and the side surface 35 of the wall portion 9. In addition, a capacitor film 37 is formed on the lower electrode 36, and an upper electrode 38 is formed on the capacitor film 37.

[0082] The lower electrode 36 integrally includes a first portion 39 and a second portion 40, wherein the first portion 39 is opposite to the upper surface 34 and the side surface 35 of the wall portion 9 and includes a relative electrode opposite to the upper electrode 38, and the second portion 40 is led out from the first portion 39 to the first surface 3 of the substrate 2 and includes a contact portion opposite to the first external electrode 7. The first portion 39 and the second portion 40 of the lower electrode 36 can be referred to as a capacitance region and a contact region of the lower electrode 36 according to their respective functions. The contact region of the second portion 40 of the lower electrode 36 is led out further outward than the upper electrode 38 and is not opposite to the upper electrode 38 in the thickness direction of the substrate 2.

[0083] In addition, the lower electrode 36 may be a semiconductor material such as polysilicon, or a metal material containing Cu or Al. In the case of a metal material, it may be formed of Cu, Al, AlSi or AlCu. In addition, the thickness of the lower electrode 36 may be, for example, (400nm~600nm).

[0084] The capacitive film 37 is formed in accordance with the shape of the lower electrode 36 and conforms to the concavo-convex shapes of the wall portion 9 in the width direction and the height direction. The capacitive film 37 only needs to cover at least the first portion 39 of the lower electrode 36 .

[0085] In addition, the capacitor film 37 may be, for example, a SiO2 film or a SiN film, or a stacked film thereof. For example, it may be a SiO2 / SiN stacked film or a SiO2 / SiN / SiO2 stacked film. Furthermore, the capacitor film 37 may also be an insulating film formed of a high dielectric material (High-k material). Examples of high dielectric materials include tantalum pentoxide (Ta2O5) and hafnium oxide (HfO2). In addition, examples include strontium titanate (SrTiO3) and barium strontium titanate (BaTiO3). x Sr 1-x )TiO3 and other perovskite compounds. In addition, the thickness of the capacitor film 37 is, for example, (10nm~100nm).

[0086] The upper electrode 38 is embedded in the gap 28 and formed along the first surface 3 of the substrate 2. The upper electrode 38 integrally includes: a first portion 41 embedded in the gap 28; and a second portion 42 connected to the upper end of the first portion 41 and formed flatly along the first surface 3 of the substrate 2. The first portion 41 and the second portion 42 of the upper electrode 38 may also be referred to as the embedded portion and the flat portion of the upper electrode 38 according to their respective forms.

[0087] The entire first portion 41 and the portion of the second portion 42 facing the lower electrode 36 constitute a capacitor region 43 of the upper electrode 38. In addition, the region of the second portion 42 that is drawn out from the formation region of the wall portion 9 to the first surface 3 of the substrate 2 constitutes a contact region 44 with the second external electrode 8. Figure 5 As shown, the contact region 44 of the upper electrode 38 and a portion of the second portion 40 of the lower electrode 36 (a portion other than the contact region) can face each other via the capacitor film 37. Thus, the stacked structure can also be used as a capacitor, and the capacitance of the capacitor 33 can be further increased.

[0088] In addition, the upper electrode 38 may be a semiconductor material such as polycrystalline silicon, or a metal material containing Cu or Al. In the case of a metal material, it may be formed of Cu, Al, AlSi or AlCu. In addition, the thickness of the upper electrode 38 (second portion 42) may be, for example, (500nm~1000nm).

[0089] On the substrate 2, a first insulating film 45 and a second insulating film 46 are further formed. The first insulating film 45 covers the insulating film 32 and the upper electrode 38 and is stacked thereon. The second insulating film 46 is stacked on the first insulating film 45. The first insulating film 45 and the second insulating film 46 have end faces that coincide with the third surface 5 of the substrate 2. Therefore, the insulating film 32, the first insulating film 45, and the second insulating film 46 are Figure 5The cross-sectional view shown has a stacking interface exposed on an extension line of the third surface 5 of the substrate 2 .

[0090] The first insulating film 45 and the second insulating film 46 are formed with a first contact hole 47 for exposing the second portion 40 (contact region) of the lower electrode 36, and a second contact hole 48 for exposing the contact region 44 of the upper electrode 38. The first contact hole 47 and the second contact hole 48 are respectively formed in regions directly below the first external electrode 7 and the second external electrode 8. In addition, the first contact hole 47 and the second contact hole 48 are respectively formed in a line shape along the short side direction D1 of the substrate 2.

[0091] Furthermore, there is no particular limitation on the positions and shapes of the first contact hole 47 and the second contact hole 48 as long as the lower electrode 36 and the upper electrode 38 can be exposed. For example, the first contact hole 47 and the second contact hole 48 are respectively formed in the region between the first external electrode 7 and the second external electrode 8. In addition, the first contact hole 47 and the second contact hole 48 can be respectively formed in a circular shape, a quadrilateral shape, or the like.

[0092] Main reference Figure 2 and Figure 5 , on the second insulating film 46, the first electrode film 49 and the second electrode film 50 are formed to be spaced apart from each other.

[0093] The first electrode film 49 integrally includes a first pad portion 51 and a first lead portion 52. The first pad portion 51 is disposed just below the first external electrode 7 and is opposite to the first external electrode 7. The first lead portion 52 is led out from the first pad portion 51 along the first surface 3 of the substrate 2 toward the second external electrode 8 and is formed between the first external electrode 7 and the second external electrode 8. The first pad portion 51 enters the first contact hole 47 and is connected to the lower electrode 36.

[0094] The second electrode film 50 integrally includes a second pad portion 53 and a second lead portion 54. The second pad portion 53 is disposed directly below the second external electrode 8 and is opposite to the second external electrode 8. The second lead portion 54 is led out from the second pad portion 53 along the first surface 3 of the substrate 2 toward the first external electrode 7 and is formed between the first external electrode 7 and the second external electrode 8. The second pad portion 53 enters the second contact hole 48 and is connected to the upper electrode 38.

[0095] like Figure 2 As shown, the first electrode film 49 and the second electrode film 50 are formed as a whole on substantially the entire first surface 3 of the substrate 2, except for the region of the gap 55 (e.g., about 2 μm) therebetween. Thus, since substantially the entire region of the first surface 3 of the substrate 2 is covered by the electrode films 49 and 50, the external force applied to the first surface 3 can be evenly dispersed, and the impact can be mitigated.

[0096] In addition, a material containing Al can be applied as the electrode material of the first electrode film 49 and the second electrode film 50. Examples of such a material include AlCu and AlSiCu, and AlCu is preferred.

[0097] In addition, Figure 2 In the embodiment, the second electrode film 50 is formed larger than the first electrode film 49 and covers most of the strip-shaped wall portion 9 ( Figure 3 However, the size relationship between the first electrode film 49 and the second electrode film 50 is not particularly limited, and can be changed by appropriately setting the position and shape of the gap 55. For example, the first electrode film 49 may be larger than the second electrode film 50.

[0098] A surface insulating film 56 is further formed on the substrate 2. The surface insulating film 56 covers the first electrode film 49 and the second electrode film 50. The surface insulating film 56 may be, for example, a SiO2 film or a SiN film. The thickness of the surface insulating film 56 may be, for example, (1μm~1.5μm).

[0099] The surface insulating film 56 integrally includes a first portion 57 covering the region on the first surface 3 of the substrate 2 and a second portion 58 covering the third surface 5 of the substrate 2. Thus, the second surface 4 of the substrate 2 is exposed, and the other surfaces are entirely covered by the surface insulating film 56.

[0100] A surface protection film 59 is formed on the first portion 57 of the surface insulating film 56. The surface protection film 59 may be, for example, a resin film such as a polyimide film. The thickness of the surface protection film 59 is, for example, (2μm~10μm).

[0101] The surface protection film 59 is formed between the first external electrode 7 and the second external electrode 8 so as to bulge upward (in a direction away from the first surface 3 of the substrate 2 ) at the center portion in the longitudinal direction D2 of the substrate 2 .

[0102] The surface insulating film 56 and the surface protective film 59 are formed with first pad openings 60 for exposing the first pad portion 51 . The surface insulating film 56 and the surface protective film 59 are formed with second pad openings 61 for exposing the second pad portion 53 .

[0103] The first external electrode 7 is formed in the first pad opening 60. The first external electrode 7 is electrically connected to the first pad portion 51 in the first pad opening 60. Thus, the first external electrode 7 is electrically connected to the lower electrode 36 via the first electrode film 49.

[0104] The second external electrode 8 is formed in the second pad opening 61. The second external electrode 8 is electrically connected to the second pad portion 53 in the second pad opening 61. Thus, the second external electrode 8 is electrically connected to the upper electrode 38 via the second electrode film 50.

[0105] The first external electrode 7 and the second external electrode 8 have a first protrusion 62 and a second protrusion 63 , respectively, which protrude from the surface of the surface protection film 59 .

[0106] The first protrusion 62 has a lead portion extending from the first pad opening 60 along the first surface 3 of the substrate 2 toward the second external electrode 8 and formed between the first external electrode 7 and the second external electrode 8. Similarly, the second protrusion 63 has a lead portion extending from the second pad opening 61 along the first surface 3 of the substrate 2 toward the first external electrode 7 and formed between the first external electrode 7 and the second external electrode 8.

[0107] The first external electrode 7 and the second external electrode 8 may be, for example, a Ni / Pd / Au laminated film including a Ni film, a Pd film, and an Au film laminated in this order from the substrate 2. These laminated films may also be plated layers formed by plating growth.

[0108] Furthermore, according to the chip component 1, the wall portion 9 formed on the substrate 2 is formed by a plurality of column units 13. Each column unit 13 includes a central portion 14 and three convex portions 15 extending in three different directions from the central portion 14 when viewed from above. Thus, the surface area of ​​the wall portion 9 can be increased compared to a case where the wall portion 9 is formed by connecting column units such as quadrangular prisms.

[0109] Furthermore, the lower electrode 36, the capacitor film 37 and the upper electrode 38 are formed according to the upper surface 34 and the side surface 35 of the wall portion 9, so the capacity of the capacitor portion 33 is not limited by the plane size of the substrate 2, and the large capacity can be achieved by increasing the height H of the wall portion 9. In other words, even if the plane size of the substrate 2 is small, the capacity of the capacitor portion 33 can be largely ensured, and both the miniaturization of the element and the large capacity of the capacitor portion 33 can be achieved.

[0110] In addition, if the wall portion 9 is formed by connecting a plurality of column units 13, it has excellent stability compared to mutually independent column units 13. In addition, one end 9A and the other end 9B of the wall portion 9 are connected to the supporting portion 10 around the wall portion 9. Thus, the wall portion 9 can be supported from both sides, and the lateral force applied to the wall portion 9 can be strengthened. As a result, even if the height H of the wall portion 9 is increased, the stability of the wall portion 9 can be maintained, and the reliability of the element can be improved.

[0111] More specifically, the ratio (W2 / H) of the width W2 of the protrusion 15 of the column unit 13 to the height H of the wall 9 (the depth of the gap 28) may be 2 / 50 to 2 / 100. Even if the height H of the wall 9 is increased in this manner, the wall 9 is supported by the support portion 10, so that the stability of the wall 9 can be maintained.

[0112] In addition, in each column unit 13, each convex portion 15 forms an angle θ1, θ2, and θ3 of 120° with the adjacent convex portion 15, and intersects with the adjacent convex portion 15 at the center portion 14. Therefore, even if a force is applied to the wall portion 9 from any direction, at least one of the three convex portions 15 can also play the role of a control wall to prevent the collapse of the wall portion 9. As a result, the stability of the wall portion 9 can be further improved.

[0113] Figure 6A to Figure 6L It is a figure which shows a part of the manufacturing process of the chip component 1 which concerns on 1st Embodiment of this invention.

[0114] When manufacturing the chip component 1, first, Fig. 6A As shown, a wafer 73 serving as a base of the substrate 2 is prepared. Then, a mask 74 (hard mask) made of SiO 2 is formed on the first surface 3 of the wafer 73 by, for example, thermal oxidation. Next, a resist 75 is applied on the mask 74 .

[0115] Then, if Figure 6B As shown, after the resist 75 and the mask 74 form the opening 76, the wafer 73 is selectively etched from the first surface 3 side through the mask 74. Thus, the gap 28 is formed in the removed portion of the wafer 73, and the wall portion 9 and the support portion 10 are formed in the portion other than the gap 28. As an etching method, dry etching is preferably used. By dry etching, the ratio (W2 / H) of the width W2 of the convex portion 15 of the column unit 13 to the height H of the wall portion 9 can be increased (high aspect ratio).

[0116] Then, if Figure 6C As shown, the first surface 3 of the wafer 73, the upper surface 34 of the wall portion 9, and the side surface 35 are formed with an insulating film 32 made of SiO2, for example, by thermal oxidation. Then, for example, by CVD method, a lower electrode 36, a capacitor film 37, and an upper electrode 38 are sequentially formed. In the film forming process of the lower electrode 36, the capacitor film 37, and the upper electrode 38, the raw material gas corresponding thereto is supplied into the chamber of the CVD device.

[0117] Then, if Fig.6D As shown, the upper electrode 38, the capacitor film 37, and the lower electrode 36 are patterned in sequence, thereby selectively removing the upper electrode 38, the capacitor film 37, and the lower electrode 36. The insulating film 32 is exposed in the removed region.

[0118] Then, if Fig. 6E As shown in FIG. 1 , the first insulating film 45 is formed by, for example, a CVD method.

[0119] Then, if Fig. 6F As shown in the figure, the second insulating film 46 is formed by, for example, a CVD method. Next, the second insulating film 46 and the first insulating film 45 are patterned, and the second insulating film 46 and the first insulating film 45 are selectively removed. Thus, the first contact hole 47 and the second contact hole 48 are formed. Next, the material of the first electrode film 49 and the second electrode film 50 is formed into a film by, for example, a sputtering method, and then patterned, thereby forming the first electrode film 49 and the second electrode film 50.

[0120] Then, if Figure 6G As shown, plasma etching is performed through a mask (not shown) to selectively remove the wafer 73. As a result, the material of the wafer 73 is removed in the boundary area between adjacent element areas (areas forming each chip component 1). As a result, a groove 77 of a specified depth can be formed from the first surface 3 of the wafer 73 to the middle of the thickness of the wafer 73. The groove 77 is divided by a pair of side surfaces (the third surface 5 of the chip component 1) opposite to each other, and a bottom surface 78 connecting the lower ends of the pair of third surfaces 5 (the ends on the second surface 4 side of the wafer 73). For example, the depth of the groove 77 based on the first surface 3 of the wafer 73 is approximately 100 μm, and the width of the groove 77 (the spacing between the relative third surfaces 5) is approximately 20 μm, and can be constant over the entire area in the depth direction.

[0121] Then, if Figure 6H As shown, the material of the surface insulating film 56 is formed on the entire area of ​​the first surface 3 of the wafer 73 by, for example, CVD. At this time, the surface insulating film 56 is also formed on the entire area of ​​the inner surface of the groove 77 (the third surface 5 and the bottom surface 78).

[0122] Then, if Fig.6I As shown in the figure, the material of the surface protection film 59 (for example, liquid of a photosensitive resin composed of polyimide) is sprayed on the wafer 73 from the surface insulating film 56 to form the surface protection film 59 of the photosensitive resin. At this time, in order to prevent the liquid from entering the groove 77, the liquid is applied to the wafer 73 through a mask (not shown) having a pattern that covers only the groove 77 when viewed from above. As a result, the liquid photosensitive resin is formed only on the wafer 73, and the surface protection film 59 is formed on the wafer 73.

[0123] In addition, since the liquid does not enter the groove 77, the surface protection film 59 is not formed in the groove 77. In addition, in addition to spraying the liquid of the photosensitive resin, the surface protection film 59 can also be formed by spin coating the liquid or sticking a sheet made of photosensitive resin on the first surface 3 of the chip 73.

[0124] Next, a heat treatment (curing treatment) is performed on the surface protection film 59. As a result, the thickness of the surface protection film 59 is thermally shrunk, and the surface protection film 59 is cured, and the film quality is stabilized.

[0125] Then, if Figure 6J As shown, for example, the surface protection film 59 is selectively removed and patterned by dry etching such as RIE (Reactive Ion Etching) using a photolithography process, etc. Thus, the first pad opening 60 and the second pad opening 61 are formed simultaneously.

[0126] Then, if Figure 6K As shown, for example, by laminating Ni, Pd, and Au by electroless plating, the first external electrode 7 and the second external electrode 8 can be formed simultaneously.

[0127] Then, if Figure 6L As shown, the chip 73 is ground from the second surface 4. Specifically, after the groove 77 is formed, a thin plate-shaped supporting tape (not shown) having an adhesive surface, for example, made of PET (polyethylene terephthalate) is adhered to the first external electrode 7 and the second external electrode 8 side (i.e., the first surface 3). Then, while the chip 73 is supported by the supporting tape, the chip 73 is ground from the second surface 4 side. By grinding, when the chip 73 becomes thinner until it reaches the bottom surface 78 of the groove 77, the portion connecting the adjacent chip components 1 disappears, so that the chip 73 can be divided with the groove 77 as a boundary to become a finished chip component 1. That is, the chip 73 is divided (cut) in the groove 77 (in other words, in the boundary area), thereby cutting out independent chip components 1. In addition, the chip component 1 can also be cut out by etching the chip 73 from the second surface 4 side to the bottom surface 78 of the groove 77.

[0128] Furthermore, by polishing or etching the second surface 4 of the substrate 2 of the completed chip component 1 to make it mirror-finished, the second surface 4 can be made more attractive.

[0129] [Second embodiment]

[0130] Figure 7 FIG. 1 is an enlarged view of a main part of a chip component 101 according to a second embodiment of the present invention. In the second embodiment, the same parts as those in the first embodiment are marked with the same reference numerals as those in the first embodiment. Figure 1 to Figure 5 The same reference numerals are used for the cases and the description is omitted.

[0131] Chip component 101 such as Figure 7As shown, the lower electrode 102 and the capacitance film 103 are provided instead of the lower electrode 36 and the capacitance film 37. The lower electrode 102 is formed on the insulating film 32, and the capacitance film 103 is formed on the lower electrode 102. On the capacitance film 103, the upper electrode 38 described above is formed.

[0132] The lower electrode 102 has a concavo-convex structure 104 on the contact surface with the capacitor film 103. The concavo-convex structure 104 is as follows: Figure 7 As shown, it is formed on the entire surface of the contact surface with the capacitance film 103. The concavo-convex structure 104 is formed by alternately repeating concave portions 105 and convex portions 106 along the upper surface 34 and the side surface 35 of the wall portion 9.

[0133] In addition, the lower electrode 102 may include a first layer 107 in contact with the insulating film 32, and a second layer 108 formed on the first layer 107 and in contact with the capacitor film 103. Figure 7 As shown, it can be formed to the middle of the thickness direction of the second layer 108. That is, one surface and the other surface of the first layer 107 are both flat films, one surface of the second layer 108 (the surface in contact with the first layer 107) is flat, and the other surface (the surface in contact with the capacitor film 103) can be a film with a concave-convex structure 104.

[0134] The first layer 107 may be a semiconductor material such as polysilicon, or a metal material including Cu or Al. In the case of a metal material, it may be composed of Cu, Al, AlSi or AlCu. In addition, the thickness of the first layer 107 may be, for example, (100nm~1000nm).

[0135] The second layer 108 may be a semiconductor material such as polysilicon, or a metal material including Cu or Al. In the case of a metal material, for example, it may be composed of Cu, Al, AlSi or AlCu. Figure 8 In the case of the structure shown in FIG. 1 , the second layer 108 is preferably amorphous polysilicon. In addition, the thickness of the second layer 108 can be, for example, (1nm~100nm).

[0136] Figure 8 yes Figure 7 Next, refer to Figure 8 A specific example of the concavo-convex structure 104 will be described. Figure 8 The structure shown.

[0137] Reference Figure 8The lower electrode 102 (the second layer 108 in this embodiment) includes: a plurality of mountain-shaped protrusions 109 formed at intervals from each other; and a spherical portion 110 formed by recesses 111 between adjacent protrusions 109 .

[0138] The convex portion 109 may have a top portion 112 located midway in the height direction of the spherical portion 110 (in the thickness direction of the lower electrode 102). Figure 8 As shown, it can be a flat surface or a pointed surface. By connecting the tops 112 of the protrusions 109 to each other continuously, as shown in FIG. Figure 8 In the figure, the dot-dash line indicates the base surface 113 constituting the lower electrode 102 .

[0139] One spherical portion 110 is disposed in each concave portion 111 between adjacent convex portions 109, and is formed integrally at the bottom of the concave portion 111. Figure 8 The spherical portion 110 is shown as a perfect circular shape in cross-section, and may be formed into a mushroom shape extending from the bottom of each recess 111, for example, depending on the formation conditions of the spherical portion 110. In this case, instead of the spherical portion 110, it is also referred to as an extension portion extending from the recess 111. In addition, the spherical portion 110 is formed with a size protruding to the outside from each recess 111. In this embodiment, the hemispherical portion of about half of the upper side of the spherical portion 110 protrudes beyond the base surface 113.

[0140] Thus, a concavo-convex structure 104 including a hemispherical convex portion 106 protruding from a base surface 113 and a concave portion 105 surrounded by the top 112 of the adjacent convex portion 106 and the convex portion 109 is formed on the contact surface of the lower electrode 102 (the second layer 108) with the capacitor film 103. The lower electrode 102 (the second layer 108) having the concavo-convex structure 104 is also formed as a hemispherical grained silicon layer (Hemi-Spherical-Grained Silicon).

[0141] In this embodiment, the capacitive film 103 has the convex portion 114 that enters the concave portion 105 of the concavo-convex structure 104. The convex portion 114 enters the concave portion 105 and may also enter the gap portion 115 between the spherical portion 110 and the concave portion 111.

[0142] As described above, according to the chip component 101 of the second embodiment, the concavo-convex structure 104 is formed on the lower electrode 102, so that the surface area of ​​the lower electrode 102 can be increased. As a result, the lower electrode 102 can be opposed to the upper electrode 38 with a wider area, and the capacitance of the capacitor 33 can be further increased.

[0143] Figures 9A to 9F It is a diagram showing a part of the manufacturing process of the chip component 101 according to the second embodiment of the present invention.

[0144] When manufacturing the chip component 101, as described above, Figure 6A to Figure 6B As shown, the gap 28 is formed in the wafer 73 , and the wall portion 9 and the support portion 10 (not shown) are formed in the portion other than the gap 28 .

[0145] Then, if Fig.9A As shown, the first surface 3 of the wafer 73 and the upper surface 34 and the side surface 35 of the wall portion 9 are formed into an insulating film 32 made of SiO 2 by, for example, thermal oxidation.

[0146] Then, if Fig. 9B As shown in FIG. 1 , the first layer 107 of the lower electrode 102 is formed by, for example, a CVD method.

[0147] Then, if Fig. 9C and Fig.9D As shown in FIG. 1 , the second layer 108 of the lower electrode 102 having the concavo-convex structure 104 is formed. The second layer 108 can be formed, for example, by the following steps. First, as shown in FIG. Fig. 9C As shown in FIG. 1 , the amorphous silicon layer 116 is formed by the LPCVD method using Si 2 H 6 gas. The amorphous silicon layer 116 has, for example, Next, the surface of the amorphous silicon layer 116 is treated with a hydrofluoric acid (HF) aqueous solution to remove the natural oxide film formed on the surface of the amorphous silicon layer 116. After that, an annealing treatment is performed so that Si atoms grow on the surface of the amorphous silicon layer 116 to form Fig.9D and Figure 8 The concavo-convex structure 104 is shown.

[0148] Then, if Fig.9E and Fig.9F As shown, the capacitance film 103 and the upper electrode 38 are sequentially formed by, for example, the CVD method.

[0149] Afterwards, after Figure 6D to Figure 6L By performing the steps shown, the chip component 101 can be obtained.

[0150] As mentioned above, although embodiment of this invention is described, this invention can also be implemented in other forms.

[0151] For example, in the above-mentioned embodiment, the capacitor portion 33 has a structure consisting of a lower electrode 36 and an upper electrode 38 sandwiching a capacitor film 37 of one layer, but it can also be a structure including more than two layers of capacitor films and electrodes sandwiching each capacitor film. The size of the wall portion 9 and the gap 28 can be appropriately adjusted according to the number of capacitor films and electrodes.

[0152] In addition, the lower electrode 36 does not need to be a conductive film, but may be a part of the substrate 2. For example, Fig.10 As shown, in the surface portion of the substrate 2, a high-concentration impurity region (for example, p + type region), thereby being used as the lower electrode 79. In this case, the insulating film 32 can be omitted.

[0153] In the above-described embodiment, the chip component 1 is a chip capacitor having a capacitance structure mounted alone, but by providing a region for other elements such as a diode and a fuse on the substrate 2, it can also be a composite element.

[0154] In addition, various design changes can be made within the scope of the items described in the claims.

Claims

1. A chip component, characterized in that: include: A substrate having a first surface and a second surface opposite thereto, the substrate being formed into a rectangular shape when viewed from above; a plurality of wall portions formed on the first surface side using a portion of the substrate, having one end and the other end, and the wall portions are formed by a plurality of pillar units; a first supporting portion and a second supporting portion, which are formed by using a portion of the substrate along two sides extending in the long side direction of the substrate and opposite to each other in the short side direction of the substrate, and are respectively connected to the one end portion and the other end portion of the wall portion; and According to the capacitor portion formed on the surface of the wall portion, The plurality of wall portions include a first wall portion and a second wall portion that form a pair, Each of the column units includes, in a plan view, a central portion and three convex portions, namely, a first convex portion, a second convex portion, and a third convex portion extending from the central portion in three directions. The first wall portion includes: a first main portion, which is formed by connecting the first protrusions and the second protrusions of the adjacent column units in a manner of crossing at a predetermined angle, and extends in a zigzag shape in the short-side direction of the substrate when viewed from above, and the first protrusion at one end of the first main portion is connected to the first supporting portion, and the second protrusion at the other end is connected to the second supporting portion; and a comb-tooth-shaped first branch portion, which is formed by the third protrusion of each of the column units and protrudes from the first main portion in a direction orthogonal to the longitudinal direction of the first main portion when viewed from above, The second wall portion includes: a second main portion, which is formed by connecting the first protrusions and the second protrusions of the adjacent column units in a manner of crossing at a predetermined angle, and extends in a zigzag shape in the short side direction of the substrate when viewed from above, and the second protrusion at one end of the second main portion is connected to the first supporting portion, and the first protrusion at the other end is connected to the second supporting portion; and a comb-tooth-shaped second branch portion, which is formed by the third protrusion of each of the column units and protrudes from the second main portion in a direction orthogonal to the longitudinal direction of the second main portion when viewed from above, The first wall portion and the second wall portion are opposed to each other in a manner that the first branch portion in a comb-like shape and the second branch portion in a comb-like shape are meshed with each other with a gap therebetween. In each of the column units, each of the protrusions forms an angle of 120° with the adjacent protrusions and intersects with the adjacent protrusions at the central portion. The mutually adjacent convex portions of the first wall portion and the second wall portion are provided so as to face in opposite directions in a plan view.

2. The chip component according to claim 1, characterized in that: A ratio (W / H) of a width W of the convex portion of the column unit to a height H of the wall portion is 2 / 50 to 2 / 100.

3. The chip component according to claim 1 or 2, characterized in that: The first support portion and the second support portion are connected to each other and formed in a ring shape surrounding the plurality of wall portions.

4. The chip component according to claim 1 or 2, characterized in that: including an insulating film formed on a surface of the wall portion, The capacitor section includes: a lower electrode formed on the insulating film; a capacitor film formed on the lower electrode; and an upper electrode formed on the capacitor film.

5. The chip component according to claim 4, characterized in that: The upper electrode includes an embedded electrode embedded in a space between adjacent wall portions.

6. The chip component according to claim 4, characterized in that: The lower electrode and the upper electrode include polysilicon electrodes, The capacitor film includes an oxide film.

7. The chip component according to claim 4, characterized in that: include: a first electrode film formed on the substrate and electrically connected to the lower electrode; a second electrode film formed on the substrate and electrically connected to the upper electrode; a surface insulating film covering the first electrode film and the second electrode film; a first external electrode formed on the surface insulating film, penetrating the surface insulating film and electrically connected to the first electrode film; and A second external electrode is formed on the surface insulating film, penetrates the surface insulating film, and is electrically connected to the second electrode film.

8. The chip component according to claim 7, characterized in that: The first electrode film is connected to the lower electrode in a region directly below the first external electrode.

9. The chip component according to claim 7 or 8, characterized in that: The second electrode film is connected to the upper electrode in a region directly below the second external electrode.

10. The chip component according to claim 7 or 8, characterized in that: The first electrode film and the second electrode film include aluminum electrode films.

11. The chip component according to claim 7 or 8, characterized in that: The first external electrode and the second external electrode include a plated layer formed by plated growth.

12. The chip component according to claim 7 or 8, characterized in that: The wall portion is formed in a region between the first external electrode and the second external electrode and in a region directly below the first external electrode and the second external electrode.

13. The chip component according to claim 4, characterized in that: The lower electrode has a concavo-convex structure on a contact surface with the capacitive film.

14. The chip component according to claim 1 or 2, characterized in that: The substrate includes a semiconductor substrate.

15. The chip component according to claim 1, characterized in that: A pair of wall portions consisting of the first wall portion and the second wall portion meshing in a comb-teeth shape are sequentially formed along the longitudinal direction of the substrate.

16. The chip component according to claim 15, characterized in that: The gap between the first wall portion and the second wall portion includes a first gap and a second gap, The first gap is formed between the first wall portion and the second wall portion meshing in a comb-teeth shape, and is formed in a zigzag shape. The second gap is formed between the first wall portion and the second wall portion that face each other across the surface on the opposite side to the comb teeth, and is formed in a corrugated shape.

Images