A packaging structure of stacked wafers and packaging method thereof
By forming step-like sidewalls and covering metal seed layers at the edges of the wafer stack, the problems of debonding failure and edge morphology changes in stacked wafer packages are solved, and efficient electrical interconnection and cost control are achieved.
Patent Information
- Application Number
- CN202011619443.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-12-31
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2040-12-31
AI Technical Summary
In the packaging process of stacked wafers, the higher metal bump density areas have the risk of debonding failure, resulting in yield loss, and the edge morphology of multi-layer stacked wafers has a greater change, making manufacturing difficult and cost high.
By performing specific morphological constraints on the edges of the wafer stack, a stepped sidewall is formed and a metal seed layer and metal bumps are covered on the dielectric layer, ensuring that the edge length difference to the total thickness ratio is between 2:1 and 2.5 mm. Within the scope, ensure the effectiveness of electrical interconnection.
Effectively reduce the risk of understanding bond failure, ensure yield output, and reduce production costs and manufacturing difficulty through edge trimming and dielectric layer processing.
Smart Images
Figure CN112466869B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a packaging structure of stacked wafers and a packaging method thereof, belonging to the technical field of semiconductor chip packaging. Background Art
[0002] With the development of the semiconductor industry, the performance of electronic products needs to be continuously improved. As the cost of chip manufacturing rises sharply, the way to improve product performance begins to shift from the miniaturization of chip circuit nodes to the packaging field.
[0003] In order to reduce the area and power consumption of the package, and meet the development trend of low cost and full integration of integrated circuits, packaging requires more chips to be stacked rather than traditionally laid flat, that is, to make the chips "stand up" rather than "spread out". The stacking of chips can integrate various types of chips such as logic chips, memory chips, RF chips, etc. to form heterogeneous chiplets, thereby significantly reducing power consumption, saving space, and shortening signal exchange time, which is in line with the development trend of future packaging. A typical example is the Fiji GPU display core chip of Advanced Micro Devices (AMD), which is packaged in the form of high-bandwidth memory (HBM) stacked with logic chips, and then packaged with GPU chips in 2.5D. However, the industry already has a clear roadmap to stack all these chips to form a true 3D package.
[0004] Wafer-level packaging (WLP) is a typical low-cost and high-efficiency packaging method. WLP is a method of arranging dielectric layer I110 and metal layer on a complete wafer using standard tools and processes before wafer cutting. After the chips are stacked, the top chip or the bottom chip must extend the pins to electrically interconnect with the substrate or printed circuit board; in the existing public method, the stacked wafers are pre-grown with bump pins on the top wafer where the pins need to extend, and the subsequent stacking process is completed after temporary bonding. However, for the layout area of higher metal bumps 360 or higher density metal bumps 360, there is a higher risk of debonding failure, and the number of heterogeneous integration layers is large, and once a failure occurs, it may cause a large yield loss.
[0005] Therefore, it is a low-cost and high-yield method to grow the stacked wafer pins using the traditional wafer-level bump production line. However, the edge of the multi-layer stacked wafer has a large morphology change, which makes the traditional WLP production line difficult to manufacture and insufficient in feasibility. Summary of the invention
[0006] Based on this, it is necessary to provide a packaging structure of stacked wafers and a packaging method thereof. During the manufacturing process, the edges and thickness of the stacked wafers are constrained to form a specific morphology to ensure that the edge morphology will not affect the bump manufacturing process during the bump manufacturing process.
[0007] The objective of the present invention is achieved as follows: The present invention provides a packaging structure of stacked wafers, which includes a wafer stack C2, a carrier wafer A1, and an electrical connection layer. The wafer stack C2 is arranged above the carrier wafer A1 and is connected through the electrical connection layer. The wafer stack C1 includes several layers of functional wafers, and the wafers include a silicon base, a silicon through-hole, a dielectric layer I, and a metal interconnection layer. The silicon through-hole penetrates the silicon base from top to bottom. The dielectric layer I is arranged above the silicon base and exposes the metal interconnection layer through the opening of the dielectric layer I. From bottom to top, the size of the wafers decreases layer by layer, and stepped side walls are formed around them. Above the carrier wafer A1, the front side of the wafer stack C2 is coated with a dielectric layer III and an opening of the dielectric layer III is formed. The dielectric layer III coats the stepped side walls of the wafer stack C2 downwardly, and a metal seed layer and a metal bump are arranged inside the opening of the dielectric layer III. The metal bump is connected to the metal interconnection layer of an adjacent wafer through the metal seed layer.
[0008] Furthermore, a ratio of a length difference △5 between an edge of the wafer stack C1 and an edge of the wafer A1 to a total thickness T1 is not less than 2:1.
[0009] Furthermore, the length difference Δ5 between the edge of the wafer stack C1 and the edge of the wafer A1 is not greater than 2.5 mm and is the minimum required to ensure effective electrical interconnection of the metal contacts of the electroplating fixture.
[0010] Furthermore, the material of the metal bump includes at least one of gold, tin, silver, copper and nickel.
[0011] Furthermore, the dielectric layer I includes at least one of polyimide and phenolic resin organic materials.
[0012] The present invention discloses a packaging method for a packaging structure of stacked wafers, and the process steps are as follows: step 1, providing wafer A1 and wafer B1, wafer B2, wafer B3, and wafer B4, completing silicon vias, dielectric layer I, and metal interconnection layer on the silicon base of wafers B1, wafer B2, wafer B3, and wafer B4, depositing metal inside the silicon vias and connecting with the metal interconnection layer, and exposing dielectric layer I on the top layer of the metal interconnection layer, wherein wafer B1 is the bottom wafer of the package, and will be interconnected with other wafers in the future, and wafer B4 is the wafer on which metal bumps are finally grown;
[0013] Step 3: Provide a carrier plate, and bond the upper surface of the wafer B1 to the carrier plate by an adhesive;
[0014] Step 4: Thinning the silicon substrate of the wafer B1 by a thinning process such as mechanical grinding or chemical etching to expose the upper surface of the silicon via;
[0015] Step 5: a dielectric layer is formed on the wafer B1 on the TSV by coating or chemical deposition process and a dielectric layer opening is formed, wherein the dielectric layer opening exposes the upper surface of the TSV;
[0016] Step 6: forming a conductive layer in the dielectric layer opening by one or a combination of evaporation, electroplating or chemical plating, wherein the conductive layer is connected to the silicon via;
[0017] Step 7, wafer B1 is interconnected with wafer B2, and the top layer of the metal interconnection layer of wafer B2 is connected to the conductive layer of wafer B1. Repeat the above steps, wafer B3 is stacked with wafer B2, and wafer B4 is stacked with wafer B3, completing layer-by-layer interconnection to form a wafer stack C1. Wafer B2, wafer B3, and wafer B4 are subjected to the same thinning process, and then their respective dielectric layers are formed by coating or chemical deposition process, and finally their respective conductive layers are formed.
[0018] Step 8: After the required number of stacked layers is met, debond and remove the carrier;
[0019] Step 9: The wafer B1 of the wafer stack C1 is then bonded face to face with the bottom wafer A1, that is, the top layer of the protruding metal interconnection layer of the wafer B1 is interconnected with the pad of the bottom wafer A1 to form a wafer stack C2; the back side of the wafer A1 is also ground and thinned to meet the thickness limit of the machine operation;
[0020] Step 10: trim the edge of the wafer stack C2 so that the total thickness T1 = wafer B1 + wafer B2 + wafer B3 + wafer B4, and the total thickness T1 does not exceed 50% of the thickness T of the photoresist layer. After trimming, the ratio of the length difference △5 between the edge of the wafer stack C1 and the edge of the wafer A1 to the total thickness T1 is not less than 2:1, and the length difference △5 between the edge of the wafer stack C1 and the edge of the wafer A1 is not greater than 2.5 mm and the minimum should ensure effective electrical interconnection of the metal contacts 401 of the electroplating fixture;
[0021] Step 11: Coat the front surface of the wafer stack C2 and the sidewalls around it with a dielectric layer III, and cover the front surface of the wafer B4 and the sidewalls of the wafer stack C2 with an opening in the dielectric layer exposing the top layer of the metal interconnect layer of the wafer B4;
[0022] Step 12: Using magnetron sputtering or evaporation, a metal seed layer is formed on the front side of the wafer stack C2, and the metal seed layer also covers the top layer of the metal interconnect layer of B4;
[0023] Step 13: Continue to apply photoresist on the metal seed layer, and expose a photoresist layer opening on the photoresist layer on the front side of the wafer B4;
[0024] Step 14: Form metal bumps by electroplating, remove useless photoresist, and etch away useless metal seed layers to complete the production of metal bumps;
[0025] Furthermore, in step two, the edges of wafer B1, wafer B2, wafer B3, and wafer B4 are trimmed, and the silicon base is cut from top to bottom until it is flush with the bottom of the silicon via; in step four, the remaining silicon base of wafer B1 is thinned by thinning processes such as mechanical grinding or chemical etching until the upper surface of the silicon via is exposed, thereby completing the trimming of the edges of wafer B1, wafer B2, wafer B3, and wafer B4.
[0026] Further, in step seven, wafer B1, wafer B2, wafer B3, and wafer B4 are stacked in sequence and connected to each other, and the gaps between the top layers of the metal interconnection layers are filled with organic resin, and the thickness of the organic resin is equal to the thickness of the top layer of the metal interconnection layer.
[0027] Furthermore, the organic resin includes epoxy resin or phenolic resin.
[0028] Furthermore, the processing method of the edge of the photoresist layer includes: first completing an anti-seepage ring on the edge of the wafer B4 by shading or exposing, and then developing the photoresist on the edge by exposing or shading.
[0029] Beneficial Effects
[0030] 1. During the manufacturing process, define the position difference between the upper and lower wafers and the ratio of the thickness of the single-layer wafer to the thickness of the photoresist to ensure the coverage of the photoresist;
[0031] 2. Define the diameter difference between the upper and lower wafers under the premise that the center of the second wafer coincides with the bottom wafer, forming the position difference of the edge to ensure the sealing and effectiveness of the electrical interconnection of the electroplating fixture contacts. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 A cross-sectional schematic diagram of a packaging structure of stacked wafers according to the present invention;
[0033] Figure 2 for Figure 1 A partially enlarged cross-sectional schematic diagram of ;
[0034] Figures 3A to 3P A cross-sectional schematic diagram of a packaging method for a packaging structure of stacked wafers according to the present invention;
[0035] In the figure:
[0036] TSV 101
[0037] Dielectric layer Ⅰ110
[0038] Metal interconnect layer 120
[0039] Electrical connection layer 150
[0040] Pad 151
[0041] Carrier 200
[0042] Bonding layer 201
[0043] Wafer A1
[0044] Wafer B1
[0045] Wafer B2
[0046] Wafer B3
[0047] Wafer B4
[0048] Dielectric layer Ⅲ300
[0049] Dielectric layer III opening 301
[0050] Metal seed layer 310
[0051] Photoresist layer 320
[0052] Photoresist layer opening 323
[0053] Anti-seepage ring 304
[0054] Metal Bump 360
[0055] Electroplating fixture metal contacts 401
[0056] The fixture sealing layer 402 is electroplated. DETAILED DESCRIPTION
[0057] The specific implementation modes of the present invention are described in detail below with reference to the accompanying drawings.
[0058] The present invention provides a packaging structure of stacked wafers, such as Figure 1 and Figure 2 As shown, Figure 1 A cross-sectional schematic diagram of a stacked wafer structure of the present invention; Figure 2 for Figure 1 The partially enlarged cross-sectional schematic diagram includes a wafer stack C2, a wafer A1, and an electrical connection layer 150, wherein a pad 151 is provided in the electrical connection layer 150. The wafer A1 carries the wafer stack C2.
[0059] The wafer stack C2 is disposed above the carrier wafer A1 and connected via an electrical connection layer 150. The wafer stack C1 includes several layers of functional wafers, such as Figure 1 As shown, wafer B1, wafer B2, wafer B3, and wafer B4 are used as an example.
[0060] Each functional wafer includes a silicon substrate 100, a silicon through-hole 101, a dielectric layer I 110 and a metal interconnection layer 120. The silicon through-hole 101 penetrates the silicon substrate 100 from top to bottom. The dielectric layer I 110 is arranged above the silicon substrate 100 and the top layer 121 of the metal interconnection layer 120 is exposed through the opening of the dielectric layer I 110. Above the carrier wafer A1, the front side of the wafer stack C2 is coated with a dielectric layer III 300 and a dielectric layer III opening 301 is formed. The dielectric layer III 300 is coated downward on the side wall of the wafer stack C2, as shown in FIG. Figure 1 A metal seed layer 310 and a metal bump 360 are disposed on the dielectric layer III opening 301 , and the metal bump 360 is connected to the metal interconnect layer 120 of the adjacent wafer through the metal seed layer 310 .
[0061] Specifically, the edge of the wafer stack C2 is trimmed, and its total thickness T1 = wafer B1 + wafer B2 + wafer B3 + wafer B4, and the total thickness T1 does not exceed 50% of the thickness T of the photoresist layer 320, which has a great constraint on the total thickness of wafers B1, B2, B3, and B4. After trimming, the ratio of the length difference △5 between the edge of the wafer stack C1 and the edge of the wafer A1 to the total thickness T1 is not less than 2:1, see Figure 3J The length difference △5 between the edge of wafer stack C1 and the edge of wafer A1 is not greater than 2.5 mm and should be at least sufficient to ensure effective electrical interconnection of the electroplating fixture metal contact 401. The electroplating fixture metal contact 401 is pressed on the metal seed layer for conductivity, and the electroplating fixture sealing layer 402 is against the sealing ring to prevent the electroplating solution from penetrating.
[0062] The present invention provides a packaging method for a packaging structure of stacked wafers. Figures 3A to 3P The schematic diagram of the chip packaging method is shown in Figure 1, which shows five layers of wafer A1, wafer B1, wafer B2, wafer B3, and wafer B4. The process steps are as follows: Step 1: Figure 3A , providing wafer A1 and wafer B1, wafer B2, wafer B3, and wafer B4, silicon substrate 100 of wafer B1, wafer B2, wafer B3, and wafer B4 is completed with silicon via 101, dielectric layer I 110, and metal interconnection layer 120, metal is deposited inside the silicon via 101 and connected to the metal interconnection layer 120, and the top layer 121 of the metal interconnection layer 120 exposes the dielectric layer I 110, wherein wafer B1 is the most basic wafer of the package, which will be interconnected with other wafers in the future, and wafer B4 is the wafer on which the metal bump 360 is finally grown.
[0063] Step 3: See Figure 3B, provide a carrier 200, and bond the upper surface of the wafer B1 to the carrier 200 through an adhesive 201; step 4, see Figure 3C The silicon base 100 of the wafer B1 is thinned by a thinning process such as mechanical grinding or chemical etching to expose the upper surface of the silicon via 101.
[0064] Step 5: See Figure 3D , a dielectric layer 130 is formed on the wafer B1 on the TSV 101 by coating or chemical deposition process and a dielectric layer opening 131 is formed, and the dielectric layer opening 131 exposes the upper surface of the TSV 101. The dielectric layer I 110 includes organic materials such as polyimide and phenolic resin, but inorganic materials such as silicon oxide and silicon nitride may also be used.
[0065] Step 6: See Figure 3E A conductive layer is formed in the dielectric layer opening 131 by one or a combination of evaporation, electroplating or chemical plating, and the conductive layer is connected to the silicon through-hole 101. The conductive layer includes common aluminum, copper, tin, nickel or precious metal, so as to facilitate subsequent interconnection with the wafer B2;
[0066] Step 7: See Figure 3F , wafer B1 is interconnected with wafer B2, and the top layer of the metal interconnect layer of wafer B2 is connected to the conductive layer of wafer B1; see Figure 3G , repeat the steps, stack wafer B3 and wafer B2, stack wafer B4 and wafer B3, complete layer-by-layer interconnection, and form a wafer stack C1, wafer B2, wafer B3, and wafer B4 undergo the same thinning process, and then form their own dielectric layers through coating or chemical deposition processes, and finally form their own conductive layers;
[0067] Step 8: See Figure 3H , after the required number of stacked layers is met, debonding is performed and the carrier 200 is removed;
[0068] Step 9: See Fig. 3I , then the wafer B1 of the wafer stack C1 is bonded face to face with the bottom wafer A1, that is, the top layer 121 of the protruding metal interconnect layer 120 of the wafer B1 is interconnected with the pad 151 (pad) of the bottom wafer A1, to form a wafer stack C2; because the thickness of the wafer stack C2 may exceed the actual production capacity of the wafer packaging production line, the back of the wafer A1 will also be ground and thinned to meet the thickness limit of the machine operation;
[0069] Step 10: See Figure 3J, trim the edge of the wafer stack C2 so that the total thickness T1 = wafer B1 + wafer B2 + wafer B3 + wafer B4, and the total thickness T1 does not exceed 50% of the thickness T of the photoresist layer 320, which has a great constraint on the total thickness of wafers B1, B2, B3, and B4. After trimming, the ratio of the length difference △5 between the edge of the wafer stack C1 and the edge of the wafer A1 to the total thickness T1 is not less than 2:1, see Figure 3J The length difference Δ5 between the edge of the wafer stack C1 and the edge of the wafer A1 is not greater than 2.5 mm and should be at least sufficient to ensure effective electrical interconnection of the metal contacts 401 of the electroplating fixture.
[0070] Step 11: See Figure 3K The dielectric layer III 300 is coated on the front surface of the wafer stack C2 and the side walls around it. The dielectric layer III 300 covers the front surface of the wafer B4 and the side walls of the wafer stack C2, and the dielectric layer III opening 301 exposes the top layer of the metal interconnect layer of the wafer B4. Because the glue layer of the dielectric layer III 300 is very thin, it is difficult to completely cover the stepped side walls in actual operation.
[0071] Step 12: See Figure 3L , by magnetron sputtering or evaporation, a metal seed layer 310 is formed on the front side of the wafer stack C2, and the metal seed layer 310 also covers the top layer of the metal interconnect layer of B4; step 13, see Figure 3M , and then continue to apply photoresist on the metal seed layer 310. The setting of the thickness T of the photoresist layer 320 is a key factor.
[0072] See also Figure 3M In this process, a photoresist layer opening 323 is exposed on the photoresist layer 320 on the front side of the wafer B4. The edge processing method includes: first completing an anti-seepage ring 321 on the edge of the wafer B4 by shading or exposing, and then developing the photoresist on the edge by exposing or shading. The processing method of shading or exposing depends on whether the photoresist material is a positive or negative adhesive material. If the photoresist material is a positive adhesive material, a shading method is used; if the photoresist material is a negative adhesive material, an exposure method is used. However, for laminated photoresists, this method can also be implemented by laser ablation and other methods;
[0073] Step 14: See Figure 3N The metal bump 360 is formed by electroplating, the useless photoresist is removed, and the useless metal seed layer 310 is etched away to complete the production of the metal bump 360. The material forming the metal bump 360 includes but is not limited to conductive materials that can be realized by electroplating, such as gold, tin, silver, copper, and nickel.
[0074] After completing the above steps, the subsequent packaging steps are continued. It should be further explained that the number of stacked wafer layers is not limited to the five layers shown in this embodiment, and multiple layers of wafers can be stacked within the allowable range.
[0075] In step 2, the edges of wafers B1, B2, B3, and B4 are trimmed and the silicon substrate 100 is cut from top to bottom until it is flush with the bottom of the silicon via 101, so as to save cutting time, reduce the loss of cutting tools, and reduce production costs. Fig.3O In the subsequent steps three and four, the silicon base 100 of the remaining wafer B1 is thinned by a thinning process such as mechanical grinding or chemical etching to expose the upper surface of the silicon through-hole 101, and the edges of the wafers B1, B2, B3, and B4 are trimmed. Figure 3P In step 2, trimming the edges in advance can also prevent the formation of sharp corners on the wafer after grinding.
[0076] In step seven, wafer B1, wafer B2, wafer B3, and wafer B4 are stacked in sequence. When they are connected to each other, there are still gaps between the top layers of the metal interconnection layers, which require filling with organic resins such as epoxy resin and phenolic resin (not shown in the figure). The thickness of the organic resin is equal to the thickness of the top layer of the metal interconnection layer. The presence of the organic resin is beneficial to dispersing stress between the wafers and strengthening the entire packaging structure.
[0077] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A packaging structure of stacked wafers, characterized in that: It comprises a wafer stack C2, a wafer A1, and an electrical connection layer (150); the wafer stack C2 is arranged above a carrier wafer A1 and connected via the electrical connection layer (150); the wafer stack C1 comprises a plurality of layers of functional wafers, the plurality of layers of functional wafers being wafer B1, wafer B2, wafer B3, and wafer B4; the wafer stack C1 is bonded face-to-face with the carrier wafer A1 to form the wafer stack C2; The functional wafer comprises a silicon base (100), a silicon through-hole (101), a dielectric layer I (110) and a metal interconnection layer (120), wherein the silicon through-hole (101) penetrates the silicon base (100) from top to bottom, and the dielectric layer I (110) is arranged above the silicon base (100) and exposes the metal interconnection layer (120) through an opening in the dielectric layer I (110); From bottom to top, the size of the wafer decreases layer by layer, and a stepped sidewall is formed around it. Above the supporting wafer A1, the front side of the wafer stack C2 is coated with a dielectric layer III (300) and a dielectric layer III opening (301) is formed. The dielectric layer III (300) is coated downwardly on the stepped sidewall of the wafer stack C2. A metal seed layer (310) and a metal bump (360) are arranged on the dielectric layer III opening (301). The metal bump (360) is connected to the metal interconnect layer (120) of the adjacent wafer through the metal seed layer (310); The ratio of the length difference △5 between the edge of the wafer stack C1 and the edge of the supporting wafer A1 to the total thickness T1 of the wafer stack C1 is not less than 2:1, wherein the total thickness T1 is the sum of the thicknesses of wafers B1, B2, B3 and B4.
2. The packaging structure according to claim 1, characterized in that: The length difference Δ5 between the edge of the wafer stack C1 and the edge of the wafer A1 is no more than 2.5 mm and is the minimum required to ensure effective electrical interconnection of the metal contacts (401) of the electroplating fixture.
3. The packaging structure according to claim 1, characterized in that: The material of the metal bump (360) includes at least one of gold, tin, silver, copper and nickel.
4. The packaging structure according to claim 1, characterized in that: The dielectric layer I (110) includes at least one of polyimide and phenolic resin organic materials.
5. A packaging method for a packaging structure of stacked wafers as claimed in any one of claims 1 to 4, wherein the process steps are as follows: Step 1: providing wafer A1 and wafers B1, B2, B3 and B4, completing silicon vias (101), dielectric layer I (110) and metal interconnection layer (120) on the silicon substrate (100) of wafers B1, B2, B3 and B4, depositing metal inside the silicon via (101) and connecting it to the metal interconnection layer (120), and exposing the dielectric layer I (110) on the top layer (121) of the metal interconnection layer (120), wherein wafer B1 is the bottom wafer of the package and will be interconnected with other wafers in the future, and wafer B4 is the wafer on which the metal bumps (360) are finally grown; Step 3: providing a carrier plate (200), and bonding the upper surface of the wafer B1 to the carrier plate (200) via an adhesive (201); Step 4: Thinning the silicon substrate (100) of the wafer B1 by mechanical grinding or chemical etching to expose the upper surface of the silicon through-hole (101); Step 5: Forming a dielectric layer (130) and a dielectric layer opening (131) on the wafer B1 through coating or chemical deposition process on the through silicon via (101), wherein the dielectric layer opening (131) exposes the upper surface of the through silicon via (101); Step 6: forming a conductive layer in the dielectric layer opening (131) by one process or a combination of several processes selected from evaporation, electroplating or chemical plating, wherein the conductive layer is connected to the silicon through-hole (101); Step 7, wafer B1 is interconnected with wafer B2, and the top layer of the metal interconnection layer of wafer B2 is connected to the conductive layer of wafer B1. Repeat the above steps, wafer B3 is stacked with wafer B2, and wafer B4 is stacked with wafer B3, completing layer-by-layer interconnection to form a wafer stack C1. Wafer B2, wafer B3, and wafer B4 are subjected to the same thinning process, and then their respective dielectric layers are formed by coating or chemical deposition process, and finally their respective conductive layers are formed. Step 8: After the required number of stacked layers is met, debonding is performed and the carrier is removed (200); Step nine, bonding the wafer B1 of the wafer stack C1 to the bottom wafer A1 face to face, that is, interconnecting the top layer (121) of the protruding metal interconnect layer (120) of the wafer B1 with the pad (151) of the bottom wafer A1, to form a wafer stack C2; The back side of wafer A1 will also be ground and thinned to meet the thickness limit of the machine operation; Step 10, trimming the edge of the wafer stack C2 so that the total thickness T1 = wafer B1 + wafer B2 + wafer B3 + wafer B4, the total thickness T1 does not exceed 50% of the thickness T of the photoresist layer (320), after trimming, the ratio of the length difference △5 between the edge of the wafer stack C1 and the edge of the wafer A1 to the total thickness T1 is not less than 2:1, the length difference △5 between the edge of the wafer stack C1 and the edge of the wafer A1 is not greater than 2.5 mm and the minimum should ensure effective electrical interconnection of the metal contacts (401) of the electroplating fixture; Step 11: Coating a dielectric layer III (300) on the front surface of the wafer stack C2 and the side walls thereof. The dielectric layer III (300) covers the front surface of the wafer B4 and the side walls of the wafer stack C2, and the dielectric layer III opening (301) exposes the top layer of the metal interconnect layer of the wafer B4. Step 12: Using magnetron sputtering or evaporation, a metal seed layer (310) is formed on the front side of the wafer stack C2, and the metal seed layer (310) also covers the top layer of the metal interconnect layer of B4; Step 13: Continue to apply photoresist on the metal seed layer (310), and expose a photoresist layer opening (323) on the photoresist layer (320) on the front side of the wafer B4; Step 14: Use an electroplating process to form a metal bump (360), remove useless photoresist, and etch away the useless metal seed layer (310), thereby completing the production of the metal bump (360).
6. The packaging method according to claim 5, characterized in that: In step 2, the edges of wafers B1, B2, B3 and B4 are trimmed, and the silicon substrate (100) is cut from top to bottom until it is flush with the bottom of the silicon through-hole (101); In step 4, the silicon substrate (100) of the remaining wafer B1 is thinned by mechanical grinding or chemical etching until the upper surface of the silicon via (101) is exposed, thereby completing the trimming of the edges of wafer B1, wafer B2, wafer B3, and wafer B4.
7. The packaging method according to claim 6, characterized in that: In step seven, wafer B1, wafer B2, wafer B3, and wafer B4 are stacked in sequence and connected to each other, and the gaps between the top layers of the metal interconnection layers are filled with organic resin, and the thickness of the organic resin is equal to the thickness of the top layer of the metal interconnection layer.
8. The packaging method according to claim 7, characterized in that: The organic resin includes epoxy resin or phenolic resin.
9. The packaging method according to claim 8, characterized in that: The method for processing the edge of the photoresist layer (320) includes: first completing an anti-seepage ring (321) on the edge of the wafer B4 by means of shading or exposure, and then developing the photoresist on the edge by means of exposure or shading.