Instruction processing method and device

Abstract

The present invention discloses an instruction processing device, comprising: an instruction fetch unit, an instruction execution unit and a counting buffer, wherein the counting buffer is coupled to the instruction fetch unit and the instruction execution unit respectively, and the instruction fetch unit is adapted to store address-related information of the jump instruction into the counting buffer when a jump instruction is read, and transmit an information identifier corresponding to the address-related information to the instruction execution unit, wherein the address-related information includes address information of the jump instruction in a storage device; the instruction execution unit is adapted to obtain address-related information of the jump instruction from the counting buffer according to the information identifier, and execute the jump instruction according to the address-related information. The present invention also discloses a corresponding instruction processing method, a system on chip and an intelligent device.

Description

Technical Field

[0001] The present invention relates to the field of processor technology, and in particular to an instruction processing method and device capable of reducing resources occupied by address information of instructions stored and transmitted in a processor pipeline. Background Art

[0002] Modern processors usually use pipeline technology to improve the processor's computing speed. The pipeline is composed of multiple processing units with different functions in the processor (such as instruction fetch unit, instruction decoding unit, instruction execution unit, instruction retirement unit, etc.). The processing process of an instruction is decomposed into multiple steps, and each step is executed by a corresponding processing unit. When a certain step of an instruction is completed by a certain processing unit, the instruction will enter the next processing unit in the pipeline for the next step, and the processing unit will continue to process the next instruction.

[0003] The program counter (PC) is used to store the address information of the instruction in the memory. The processor reads the instruction from the memory according to the address information stored in the program counter. After the processor obtains the instruction according to the address information in the program counter, the address information of the instruction will be stored and transferred in each processing unit of the pipeline along with the instruction until the instruction is retired, and is used to maintain the retired instructions. The transfer of the address information of the instruction on the pipeline and the storage of the address information of the instruction in each processing unit of the pipeline will occupy a large amount of hardware resources, increasing the hardware cost of the processor. Summary of the invention

[0004] To this end, the present invention provides an instruction processing method and device to try to solve or at least alleviate the above problems.

[0005] According to a first aspect of the present invention, there is provided an instruction processing device, comprising: an instruction fetch unit, an instruction execution unit and a counting buffer, wherein the counting buffer is coupled to the instruction fetch unit and the instruction execution unit respectively, and the instruction fetch unit is adapted to store address-related information of the jump instruction into the counting buffer when a jump instruction is read, and to transmit an information identifier corresponding to the address-related information to the instruction execution unit, wherein the address-related information includes address information of the jump instruction in a storage device; the instruction execution unit is adapted to obtain address-related information of the jump instruction from the counting buffer according to the information identifier, and to execute the jump instruction according to the address-related information.

[0006] Optionally, the instruction processing device according to the present invention also includes: an instruction retirement unit, which is coupled to the instruction execution unit and the counting buffer respectively, and is suitable for receiving an information identifier sent by the instruction execution unit, and obtaining address-related information of the jump instruction from the counting buffer according to the information identifier, so as to retire the jump instruction.

[0007] Optionally, in the instruction processing device according to the present invention, the instruction fetching unit is adapted to: pre-decode the read instruction to determine the operation code of the instruction; and determine whether the instruction is a jump instruction according to the operation code.

[0008] Optionally, in the instruction processing device according to the present invention, the jump instruction includes a conditional jump instruction and an unconditional jump instruction.

[0009] Optionally, in the instruction processing device according to the present invention, the instruction fetch unit is also suitable for: when a conditional jump instruction is read, predicting whether the conditional jump instruction will jump, and storing the prediction result and the address information of the conditional jump instruction as address-related information of the conditional jump instruction in a counting buffer.

[0010] Optionally, in the instruction processing device according to the present invention, the instruction fetching unit is further adapted to: determine address information of a next instruction to be read according to the prediction result.

[0011] Optionally, in the instruction processing device according to the present invention, the instruction execution unit is suitable for: executing a conditional jump instruction to obtain an execution result of whether a jump occurs; obtaining a predicted result of the conditional jump instruction from a counting buffer according to an information identifier; judging whether the predicted result is consistent with the execution result of the conditional jump instruction, and sending the judgment result and the information identifier to the instruction retirement unit, so that the instruction retirement unit determines the address information of the next instruction to be retired according to the judgment result and the information identifier.

[0012] Optionally, in the instruction processing device according to the present invention, the instruction retirement unit is suitable for: receiving the judgment result and information identifier sent by the instruction execution unit; obtaining the address-related information of the conditional jump instruction from the counting buffer according to the information identifier, and deleting the address-related information of the conditional jump instruction from the counting buffer; and determining the address information of the next instruction to be retired according to the judgment result and the address information and prediction result of the conditional jump instruction.

[0013] Optionally, in the instruction processing device according to the present invention, the instruction retirement unit is further adapted to: when the judgment result is inconsistent, re-determine the address information of the next instruction to be read according to the judgment result and the address information of the conditional jump instruction.

[0014] Optionally, in the instruction processing device according to the present invention, the instruction fetching unit is further adapted to: when an unconditional jump instruction is read, determine the jump target address of the unconditional jump instruction, and use the jump target address as address information of the next instruction to be read.

[0015] Optionally, in the instruction processing device according to the present invention, the instruction execution unit is further adapted to: execute an unconditional jump instruction to obtain an execution result of a determined jump, and send the execution result and an information identifier to the instruction retirement unit.

[0016] Optionally, in the instruction processing device according to the present invention, the instruction retirement unit is further suitable for: receiving the execution result and information identifier of the unconditional jump instruction sent by the instruction execution unit; obtaining the address-related information of the unconditional jump instruction from the counting buffer according to the information identifier, and deleting the address-related information of the unconditional jump instruction from the counting buffer; and determining the jump target address of the unconditional jump instruction according to the address information and execution result of the unconditional jump instruction, and using the jump target address as the address information of the next instruction to be retired.

[0017] Optionally, in the instruction processing device according to the present invention, the information identifier is determined according to the storage position of the address related information of the jump instruction in the counting buffer.

[0018] Optionally, in the instruction processing device according to the present invention, the counting buffer adopts a queue data structure.

[0019] According to a second aspect of the present invention, there is provided an instruction processing method, which is executed in an instruction processing device, the instruction processing device comprising an instruction fetch unit, an instruction execution unit and a counting buffer, the method comprising the steps of: when the instruction fetch unit reads a jump instruction, storing address-related information of the jump instruction into the counting buffer, and transmitting an information identifier corresponding to the address-related information to the instruction execution unit, wherein the address-related information includes address information of the jump instruction in a storage device; the instruction execution unit obtains address-related information of the jump instruction from the counting buffer according to the information identifier, and executes the jump instruction according to the address-related information.

[0020] According to a third aspect of the present invention, there is provided a system on chip, comprising an instruction processing device as described in any one of the above items.

[0021] According to a fourth aspect of the present invention, there is provided an intelligent device, comprising a system on chip as described above. According to the technical solution of the present invention, a counting buffer is used to centrally store address-related information of jump instructions. When the instruction fetching unit reads the jump instruction, the address-related information of the jump instruction is stored in the counting buffer, and the information identifier corresponding to the address-related information is determined. The address-related information includes, but is not limited to, the address information of the jump instruction in the storage device. In the subsequent processing of the jump instruction by the pipeline, the address-related information of the instruction is no longer transmitted between the various processing units, but only the information identifier is transmitted. If a processing unit on the pipeline needs to use the address-related information of the jump instruction when performing instruction processing, it is obtained from the counting buffer according to the information identifier.

[0022] According to the technical solution of the present invention, a counting buffer is used to centrally store address-related information of jump instructions, thereby avoiding storing the address information of instructions in each processing unit on the pipeline and avoiding the address information of instructions from being transmitted between processing units, thereby saving the hardware cost of each processing unit.

[0023] In addition, the counting buffer of the present invention only stores address-related information of jump instructions, and does not store address-related information of sequential instructions. Usually, only a small number of instructions in the pipeline are jump instructions, so the total number of entries in the counting buffer is usually less than the total number of instructions on the pipeline, and the resources occupied by the counting buffer itself are less than the sum of the address information of instructions transmitted in the pipeline, thereby reducing the hardware cost of the entire instruction processing device.

[0024] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To achieve the above and related purposes, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings, which indicate various ways in which the principles disclosed herein can be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. The above and other purposes, features and advantages of the present disclosure will become more apparent by reading the following detailed description in conjunction with the accompanying drawings. Throughout the present disclosure, the same reference numerals generally refer to the same parts or elements.

[0026] Figure 1 A schematic diagram of an instruction processing device 100 according to an embodiment of the present invention is shown;

[0027] Figure 2 A schematic diagram showing an instruction fragment including a sequential instruction and a jump instruction according to an embodiment of the present invention is shown;

[0028] Figure 3 A flowchart of an instruction processing method 300 according to an embodiment of the present invention is shown;

[0029] Figure 4 A schematic diagram of a processor 400 according to an embodiment of the present invention is shown;

[0030] Figure 5 FIG. 5 is a schematic diagram of a system on chip 500 according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0032] Figure 1 FIG. 1 is a schematic diagram of an instruction processing device 100 according to an embodiment of the present invention. In some embodiments, the instruction processing device 100 may be a single-core processor, a processor core in a multi-core processor, or a processing element in an electronic system, but is not limited thereto.

[0033] In addition, it should be noted that Figure 1 The division of the various components in is functional and may be rearranged and combined for physical implementation without departing from the scope of protection of the present invention.

[0034] like Figure 1 As shown, the instruction processing device 100 includes an instruction fetch unit 110, an instruction decoding unit 120, an instruction execution unit 130 and an instruction retirement unit 140 coupled in sequence. These four processing units are components of the pipeline and are respectively used to read (Fetch), decode (Decode), execute (Execute) and write back the operation results (Write-back) of instructions.

[0035] The register set 170 includes a plurality of registers. Registers are high-speed storage components with limited storage capacity, which can be used to temporarily store information such as instructions, data, and addresses. The register set 170 includes a variety of registers, such as general purpose registers (GPS), special function registers (SFR), control registers, etc., but not limited thereto. The register set 170 includes a program counter (PC), which can also be called an instruction pointer register (IP), which is a special register used to store the address information of the next instruction to be executed.

[0036] According to one embodiment, Figure 1As shown, the program counter in the register group 170 includes an instruction fetch counter 172 and a retirement counter 174. The instruction fetch counter 172 stores the address information of the next instruction to be read, and the retirement counter 174 stores the address information of the next instruction to be retired. In some other embodiments, the instruction fetch counter 172 and the retirement counter 174 may be circuit modules inside certain processing units. For example, the instruction fetch counter 172 may be a circuit module inside the instruction fetch unit 110, and the retirement counter 174 may be a circuit module inside the instruction retirement unit 140.

[0037] The storage device 180 is coupled to the instruction processing apparatus 100 and is used to store instructions and data. The storage device 180 may be, for example, a read-only memory (ROM), a random access memory (RAM), etc., but is not limited thereto.

[0038] The instruction fetch unit 110 obtains the instruction to be processed from the cache 160, the storage device 180 or other sources according to the address information stored in the instruction fetch counter 172, and updates the value of the instruction fetch counter 172 to the address of the next instruction to be executed.

[0039] The instructions fetched by the instruction fetch unit 110 may include sequential instructions and jump instructions. Sequential instructions are instructions that are executed sequentially, that is, for an instruction, if after the execution of the instruction is completed, the next instruction to be executed is the instruction immediately following the instruction in the storage device 180, then the instruction is a sequential instruction. Jump instructions are instructions that are executed by jumping, that is, for an instruction, if after the execution of the instruction is completed, the next instruction to be executed is not the instruction immediately following the instruction in the storage device 180, but an instruction located at another location in the storage device 180, then the instruction is a jump instruction.

[0040] Jump instructions further include conditional jump instructions and unconditional jump instructions. Conditional jump instructions are also called branch instructions, which contain judgment conditions. Whether the judgment conditions are met will cause the program to execute different branches. In other words, the judgment results of the judgment conditions are different, and the address of the next instruction to be executed is different. Unconditional jump instructions do not contain judgment conditions. When the unconditional jump instruction is executed, a specific instruction is always executed unconditionally.

[0041] Figure 2 FIG. 1 is a schematic diagram showing an instruction fragment including a sequential instruction and a jump instruction according to an embodiment of the present invention. Figure 2As shown, a certain area of ​​the storage device 180 continuously stores six instructions, instruction 1 to instruction 6. Instructions 1, 3, 5, and 6 are sequential instructions. After these instructions are executed, the next instruction after these instructions is executed sequentially. Instruction 2 is a conditional jump instruction. When the condition is met, branch 1 is executed, that is, jump to instruction 5 and execute instruction 5; when the condition is not met, branch 2 is executed, that is, instruction 3 is executed sequentially. Instruction 4 is an unconditional jump instruction. After instruction 4 is executed, it always jumps to instruction 6 and executes instruction 6.

[0042] The instruction decoding unit 120 receives the instructions passed in from the instruction fetch unit 110, and decodes these instructions to generate low-level micro-operations, microcode entry points, microinstructions or other low-level instructions or control signals, which reflect the received instructions or are derived from the received instructions. The low-level instructions or control signals can implement the operation of high-level instructions through low-level (e.g., circuit level or hardware level) operations. Various different mechanisms can be used to implement the instruction decoding unit 120. Examples of suitable mechanisms include, but are not limited to, microcode, lookup tables, hardware implementations, and programmable logic arrays (PLA). The present invention is not limited to the various mechanisms for implementing the instruction decoding unit 120, and any mechanism that can implement the instruction decoding unit 120 is within the scope of protection of the present invention.

[0043] Subsequently, the instruction decoding unit 120 sends the decoded instructions to the instruction execution unit 130, and the instruction execution unit 130 executes the instructions. The instruction execution unit 130 includes circuits operable to execute instructions. When executing these instructions, the instruction execution unit 130 may receive data inputs from the register set 170, the cache 160, and / or the storage device 180 and generate data outputs to them.

[0044] Subsequently, the instruction execution unit 130 sends the execution result of the instruction to the instruction retirement unit 140. In the instruction retirement stage, the instruction retirement unit 140 writes back the execution result of the instruction to the corresponding storage components (such as general registers, control registers, and storage devices 180, etc.), updates the value of the retirement counter 174 to the address of the next instruction to be executed, thereby updating the state of the instruction processing device 100.

[0045] In order to facilitate the instruction retirement unit 140 to retire instructions, the instruction retirement unit 140 needs to know the address information of the instruction to be retired. In the prior art, after the instruction fetch unit 110 obtains the instruction according to the address information in the instruction fetch counter 172, the address information of the instruction will be temporarily stored and transferred along with the instruction in each processing unit of the pipeline, and finally arrive at the instruction retirement unit 140. For the instruction processing device 100 that executes instructions out of order, it is necessary to store and transfer the address information of the instruction in the instruction fetch unit 110, the instruction decoding unit 120 and the reorder buffer (ROB). Transmitting the address information of the instruction on the pipeline and storing it in each processing unit of the pipeline will occupy a large amount of hardware resources, increasing the hardware cost of the processor. In order to solve this problem, the present invention sets a counting buffer 150 in the instruction processing device 100, and the counting buffer 150 is respectively coupled to the instruction fetch unit 110, the instruction execution unit 130, the instruction retirement unit 140 and other processing units on the pipeline, and is used to centrally store address-related information of jump instructions to avoid storing the address information of instructions in each processing unit on the pipeline, and avoid the address information of instructions from being transmitted between the processing units, thereby saving the hardware cost of each processing unit.

[0046] When the instruction currently read by the instruction fetch unit 110 is a jump instruction, the instruction fetch unit 110 stores the address-related information of the jump instruction into the counting buffer 150, and determines the information identifier of the address-related information, and the address-related information includes but is not limited to the address information of the jump instruction in the storage device 180. Subsequently, the instruction fetch unit 110 transmits the information identifier corresponding to the address-related information to the instruction execution unit 130, the instruction retirement unit 140 and other subsequent processing units via the instruction decoding unit 120. The instruction execution unit 130, the instruction retirement unit 140 and other subsequent processing units obtain the address-related information of the jump instruction from the counting buffer 150 according to the information identifier, and execute and retire the jump instruction according to the address-related information. Based on the counting buffer 150 of the present invention, in the process of processing the jump instruction in the pipeline, it is not necessary to transmit the address-related information of the jump instruction between the various processing units in the pipeline, but only the information identifier is transmitted. If a processing unit needs to use address-related information of an instruction when processing the instruction, the processing unit can obtain the address-related information from the counting buffer 150 according to the information identifier, thereby avoiding the transmission and storage of the address information of the instruction between the processing units, saving the hardware cost of each processing unit.

[0047] The counting buffer 150 of the present invention is used to centrally store address-related information of jump instructions, and only the information identifier corresponding to the stored address-related information is transmitted on the pipeline. The relevant processing units on the pipeline (such as the instruction execution unit 130, the instruction retirement unit 140, etc.) can obtain the address-related information of the jump instruction from the counting buffer 150 according to the information identifier. As for the sequential instruction, since the next instruction to be executed is the instruction located after the sequential instruction, the address information of the next instruction can be calculated according to the length of the sequential instruction, and there is no need to store and transmit the address information of the sequential instruction. Therefore, the address-related information of the sequential instruction is not stored in the counting buffer 150, and the various processing units on the pipeline will not store or transmit the address-related information of the sequential instruction. Usually only a small number of instructions in the pipeline are jump instructions, therefore, the total number of table entries cached in the counting buffer 150 is usually less than the total number of instructions on the pipeline, and the resources occupied by the counting buffer 150 itself are less than the sum of the instruction address information transmitted in the pipeline, thereby reducing the hardware cost of the entire instruction processing device.

[0048] It should be noted that Figure 1 Only one count buffer 150 is exemplarily shown in the instruction processing device 100. In other embodiments, multiple count buffers 150 may be provided in the instruction processing device 100, and the present invention does not limit the number of count buffers 150 included in the instruction processing device 100. Those skilled in the art can understand that providing multiple count buffers 150 in the instruction processing device 100 can achieve technical effects such as increasing storage capacity and improving information fault tolerance, but it will also increase the hardware cost of the instruction processing device 100. Those skilled in the art can comprehensively consider various factors and set the number of count buffers 150 according to actual conditions.

[0049] When multiple count buffers 150 are provided in the instruction processing device 100, these multiple count buffers 150 can store the same address-related information, that is, the address-related information is redundantly stored, thereby improving the fault tolerance of the information. Even if a certain count buffer 150 fails, the information stored in other count buffers 150 can also ensure the normal progress of the instruction processing process. Alternatively, these multiple count buffers 150 can store different address-related information, thereby achieving the expansion of the storage space, so that it can store more address-related information of jump instructions. Alternatively, these multiple count buffers 150 can be divided into multiple groups, and the count buffers 150 in different groups store different address-related information, and the count buffers 150 in the same group store the same address-related information, so that the capacity can be expanded while improving the information fault tolerance.

[0050] In addition, it should be noted that Figure 1The division of the various components in is only functional. In the specific physical implementation of the instruction processing device, Figure 1 The various components shown may be rearranged and combined without departing from the scope of protection of the present invention.

[0051] For example, despite Figure 1 In the instruction processing device 100, the count buffer 150 is shown as a separate component, but those skilled in the art can understand that in other embodiments, the count buffer 150 can also be integrated into certain components (for example, integrated into the instruction fetch counter 172). The present invention does not limit the specific implementation method of the count buffer 150 in the instruction processing device 100.

[0052] For example, Figure 1 The instruction retirement unit 140 shown may also be a circuit module integrated into the instruction execution unit 130; the cache 160 may further include one or more intermediate-level caches, such as the second level (L2), third level (L3), fourth level (L4) or other levels of cache, a last-level cache (LLC); and the like.

[0053] The above briefly describes the function and processing logic of the count buffer 150. The following will describe in detail the interaction between the count buffer 150 and the instruction fetch unit 110, the instruction execution unit 130, and the instruction retirement unit 140 during the instruction processing process.

[0054] The instruction fetch unit 110 reads instructions from the cache 160, the storage device 180 or other sources according to the address information in the instruction fetch counter 172. The instruction fetch unit 110 is adapted to pre-decode the read instruction to determine the operation code of the instruction, and then determine the operation type of the instruction according to the operation code, that is, determine whether the instruction is a jump instruction.

[0055] An opcode is a short code used to indicate the type of operation of an instruction. Opcodes include, for example, move (mov), add (add), subtract (sub), halt (hlt), conditional transfer (jz), etc., but are not limited thereto. Each opcode corresponds to a specific type of operation. Therefore, after identifying the opcode of an instruction, it is possible to determine whether the instruction corresponds to a jump operation, that is, whether the instruction is a jump instruction, and to determine which type of jump instruction the jump instruction is (determine whether it is a conditional jump instruction or an unconditional jump instruction). Common opcodes for jump instructions include j, jz, jnz, je, jmp, etc., but are not limited thereto.

[0056] When the instruction fetched by instruction fetch unit 110 is a jump instruction, instruction fetch unit 110 stores address related information of the jump instruction in count buffer 150 and determines the information identifier of the address related information. The address related information includes address information of the jump instruction in storage device 180, but is not limited thereto.

[0057] According to an embodiment, the information identifier of the address-related information of the jump instruction can be determined according to the storage location of the address information in the counting buffer 150. For example, the counting buffer 150 includes N table entries, each of which is used to store the address-related information of a jump instruction. Then, the counting buffer 150 can store the address-related information of N jump instructions at most. If the address-related information of a jump instruction is stored in the 5th table entry of the counting buffer 150, the information identifier of the address-related information of the jump instruction can be set to 5 accordingly.

[0058] The above method of determining the information identifier based on the storage location is only an example. Those skilled in the art will appreciate that, in addition to the above method, other methods may be used to determine the information identifier of the address-related information. The present invention does not limit the method for determining the information identifier, as long as the information identifier and the address-related information of the jump instruction have a unique corresponding relationship.

[0059] The address-related information of the jump instruction includes, but is not limited to, the address information of the jump instruction in the storage device. According to one embodiment, the address-related information may include, in addition to the address information of the jump instruction, information such as the type of the jump instruction (conditional jump instruction, unconditional jump instruction, or a type classified according to other classification criteria), the prediction result of the branch instruction, etc. The specific information items included in the address-related information may differ according to the different types of jump instructions.

[0060] According to one embodiment, when the instruction fetch unit 110 reads a conditional jump instruction, it predicts whether the conditional jump instruction will jump (i.e., performs branch prediction), and stores the prediction result and the address information of the conditional jump instruction as address-related information of the conditional jump instruction in the counting buffer 150. In addition, the type of the jump instruction (i.e., the conditional jump instruction) can also be stored in the counting buffer 150, that is, the address-related information of the conditional jump instruction can also include the type identifier of the jump instruction.

[0061] Furthermore, when the instruction fetch unit 110 reads a conditional jump instruction, the instruction fetch unit 110 also determines the address information of the next instruction to be executed (the next instruction to be executed is the next instruction to be read) according to the prediction result, and updates the address information of the next instruction to be executed to the instruction fetch counter 172. It should be noted that the instruction fetch unit 110 can, for example, adopt a static branch prediction method to always predict the first branch or the second branch in the conditional jump instruction; or adopt a dynamic branch prediction method to predict whether the current conditional jump instruction will jump according to the historical branch hit situation; and so on. The present invention does not limit the specific branch prediction strategy adopted by the instruction fetch unit 110, and any branch prediction strategy is within the protection scope of the present invention.

[0062] When the instruction fetch unit 110 reads an unconditional jump instruction, since the jump target address (i.e., the address of the next instruction to be executed) is specified in the unconditional jump instruction, the instruction fetch unit 110 can determine the jump target address of the unconditional jump instruction by pre-decoding, and use the jump target address as the address information of the next instruction to be read, and update the instruction fetch counter 172. In some embodiments, the address-related information of the unconditional jump instruction may only include the address information of the unconditional jump instruction. In other embodiments, the address-related information of the unconditional jump instruction may include, in addition to the address information of the unconditional jump instruction, information such as the type identification and jump target address of the unconditional jump instruction.

[0063] After storing the address-related information of the jump instruction in the counting buffer 150 and determining the information identifier corresponding to the address-related information, the instruction fetch unit 110 sends the jump instruction and the information identifier to the instruction decoding unit 120. The instruction decoding unit 120 decodes the instruction to generate low-level micro-operations, microcode entry points, micro-instructions or other low-level instructions or control signals, which reflect the received instructions or are derived from the received instructions. Specifically, the instruction decoding unit 120 decodes the information required for the execution of the instruction, such as the operation type of the instruction (such as addition, subtraction, multiplication, division, etc.), the operand address (source operand address, target register address, etc.), the instruction length (such as 32 bits), etc., but not limited to this. Subsequently, the instruction decoding unit 120 sends the decoded instruction information and the information identifier corresponding to the instruction to the instruction execution unit 130.

[0064] The instruction execution unit 130 executes the jump instruction according to the instruction information sent by the instruction decoding unit 120, and sends the execution result and information identifier of the jump instruction to the instruction retirement unit 140. The instruction retirement unit 140 receives the information identifier sent by the instruction execution unit 130, and obtains the address-related information of the jump instruction from the counting buffer 150 according to the information identifier, so as to retire the jump instruction. Depending on the type of jump instruction, the processing steps performed by the instruction execution unit 130 and the instruction retirement unit 140 are different.

[0065] When the jump instruction is a conditional jump instruction, the instruction execution unit 130 executes the conditional jump instruction to determine whether the jump condition is established to obtain an execution result of whether the jump occurs. In addition, the instruction execution unit 130 obtains the predicted result of the conditional jump instruction from the counting buffer 150 according to the received information identifier. The instruction execution unit 130 determines whether the obtained predicted result is consistent with the actual execution result of the conditional jump instruction, and sends the judgment result and the information identifier to the instruction retirement unit 140, so that the instruction retirement unit 140 determines the address information of the next instruction to be retired according to the judgment result and the information identifier, and updates the address information of the next instruction to be retired to the retirement counter 174.

[0066] The instruction retirement unit 140 receives the judgment result and information identifier sent by the instruction execution unit 130, obtains the address-related information of the conditional jump instruction from the count buffer 150 according to the information identifier, and then deletes the address-related information of the conditional jump instruction stored in the count buffer 150. Subsequently, the instruction retirement unit 140 determines the address information of the next instruction to be retired according to the judgment result sent by the instruction execution unit 130, and the address information and prediction result of the conditional jump instruction obtained from the count buffer 150, and updates the address information of the next instruction to be retired to the retirement counter 174.

[0067] Specifically, when the judgment result sent by the instruction execution unit 130 indicates that the predicted result of the conditional jump instruction is consistent with the actual execution result, it indicates that the prediction is correct. The instruction retirement unit 140 can determine the address information of the next instruction to be executed based on the address information and the predicted result (i.e., the actual execution result) of the conditional jump instruction. The next instruction to be executed is the next instruction to be retired, and the address information of the next instruction to be executed is updated to the retirement counter 174. In addition, since the prediction is correct, the address information of the next instruction stored in the current instruction fetch counter 172 is also correct and does not need to be corrected.

[0068] When the judgment result sent by the instruction execution unit 130 indicates that the predicted result of the conditional jump instruction is inconsistent with the actual execution result, it indicates a prediction error. In this case, the instruction retirement unit 140 determines the address information of the next instruction to be executed based on the address information of the conditional jump instruction and the actual execution result (the actual execution result is opposite to the predicted result), and updates the address information of the next instruction to be executed to the retirement counter 174.

[0069] In addition, the address information of the next instruction currently stored in the instruction fetch counter 172 is determined based on the prediction result. Due to the prediction error, the address information stored in the instruction fetch counter 172 is also wrong and needs to be corrected. Therefore, according to one embodiment, when the judgment result indicates that the prediction result of the conditional jump instruction is inconsistent with the actual execution result, the instruction retirement unit 140 re-determines the address information of the next instruction to be read based on the received judgment result and the address information of the conditional jump instruction, and updates the address information of the next instruction to be executed to the instruction fetch counter 172.

[0070] When the jump instruction is an unconditional jump instruction, the instruction execution unit 130 executes the unconditional jump instruction to obtain the execution result of the determined jump. In addition, the instruction execution unit 130 can obtain address-related information from the counting buffer 150 according to the information identifier to further determine the execution result of the jump. Subsequently, the instruction execution unit 130 sends the execution result of the determined jump and the information identifier to the instruction retirement unit 140, so that the instruction retirement unit 140 determines the address information of the next instruction to be executed, and updates the address information of the next instruction to be executed to the retirement counter 174.

[0071] The instruction retirement unit 140 receives the execution result and information identifier of the determined jump sent by the instruction execution unit 130, obtains the address-related information of the unconditional jump instruction from the counting buffer 150 according to the information identifier, and then deletes the address-related information of the unconditional jump instruction stored in the counting buffer 150. Subsequently, the instruction retirement unit 140 determines the jump target address of the unconditional jump instruction according to the address information of the unconditional jump instruction and the execution result of the determined jump sent by the instruction execution unit 130 (the jump target address is the address of the next instruction to be executed and to be retired), and updates the retirement counter 174 with the jump target address as the address information of the next instruction to be retired.

[0072] In the embodiment of the present invention, the count buffer 150 includes a plurality of entries, each of which corresponds to address-related information of a jump instruction. Each entry of the count buffer 150 is identified and distinguished by an information identifier.

[0073] According to one embodiment, the counting buffer 150 is implemented using a queue data structure, and each entry in the counting buffer 150 follows a First In First Out (FIFO) storage principle, that is, the order of creation (storage) and popping (deletion) of the entries is the same, and the entries created first will be popped out before the entries created later.

[0074] When the instruction fetch unit 110 pre-decodes a jump instruction, the instruction fetch unit 110 stores the address-related information of the jump instruction as a table entry in the count buffer 150 and determines the information identifier of the table entry. Subsequently, the instruction fetch unit 110 sequentially transmits the information identifier of the table entry along with the jump instruction to the subsequent pipelines such as the instruction decoding unit 120, the instruction execution unit 130, and the instruction retirement unit 140. The creation of each table entry in the count buffer 150 is performed according to the execution order of the instructions.

[0075] The count buffer 150 includes at least two pointers, a create pointer and a retire pointer, wherein the create pointer points to an empty table entry to be created in the count buffer 150, and the identifier of the table entry pointed to by the create pointer is the information identifier of the next jump instruction. The retire pointer points to the oldest table entry in the count buffer 150, that is, the table entry corresponding to the next jump instruction to be retired. The count buffer 150 determines the empty and full status by the create pointer and the retire pointer. When the count buffer 150 is full, the instruction fetch unit 110 cannot create a new jump instruction table entry in the count buffer 150, so the instruction fetch unit 110 will suspend execution to wait for an entry to be popped out of the count buffer 150.

[0076] According to one embodiment, when the instruction execution unit 130 executes the jump instruction out of order, the address-related information of the jump instruction can be obtained from the count buffer 150 according to the information identifier of the jump instruction. After the jump instruction is executed, the instruction execution unit 130 can store part of the execution result in the corresponding table entry of the count buffer 150. In the instruction retirement stage, the instruction retirement unit 140 obtains the address-related information (including part of the execution result) of the jump instruction from the count buffer 150 according to the information identifier, and updates and maintains the retirement counter 174 according to the obtained address-related information. After the jump instruction is retired, the table entry corresponding to the instruction is popped out from the count buffer 150.

[0077] Since instructions are retired in the order of execution, the entries in the count buffer 150 are also popped out in the order of execution of the instructions.

[0078] The instruction processing scheme of the present invention is described below with a specific embodiment.

[0079]

[0080] Referring to the above table, the storage area 0x4 to 0x18 of the storage device 180 stores an instruction fragment, which includes six instructions, instruction 1 to instruction 6. The function implemented by the instruction fragment is to find the absolute value of the variable x, that is,

[0081]

[0082] Before the instruction fragments in the above table are executed, the addresses stored in the instruction fetch counter 172 and the retirement counter 174 are both 0x4, indicating that the next instruction to be read and retired is instruction 1.

[0083] The execution process of instruction 1 is as follows:

[0084] The instruction fetch unit 110 reads instruction 1 according to the address 0x4 in the instruction fetch counter 172. The instruction fetch unit 110 pre-decodes instruction 1 and determines that instruction 1 is a sequential instruction, not a jump instruction. Therefore, the next instruction to be read is instruction 2 located after instruction 1, and the value of the instruction fetch counter 172 is updated to the address of instruction 2, that is, 0x8. Subsequently, instruction 1 is sent to the instruction decoding unit 120.

[0085] The instruction decoding unit 120 decodes instruction 1, determines that the operation type of instruction 1 is a memory load operation 1w (load word), the address of the operand is the content stored in register x7 (corresponding to the indirect addressing mode), the target register is register x5, and the length of the instruction is 32 bits and other instruction information, and sends this instruction information to the instruction execution unit 130.

[0086] The instruction execution unit 130 receives the instruction information sent by the instruction decoding unit 120, takes out the value of the variable x from the memory according to the address 0 (x7) of the operand, and then sends the execution result of the instruction (the value of x taken out) and the target register x5, the instruction length of 32 bits and other information to the instruction retirement unit 140.

[0087] The instruction retirement unit 140 writes the value of x into register x5 and updates the value of the retirement counter 174 to 0x8 (i.e., the original value 0x4 plus the instruction length of 32 bits).

[0088] The execution process of instruction 2 is as follows:

[0089] The instruction fetch unit 110 reads instruction 2 according to the address 0x8 in the instruction fetch counter 172. The instruction fetch unit 110 pre-decodes instruction 2 and determines that instruction 2 is a branch instruction (i.e., a conditional jump instruction) based on the operation code bltz (branch less than zero) of instruction 2. Subsequently, the instruction fetch unit 110 predicts the branch instruction and creates the prediction result (e.g., "no jump"), the address 0x8 of instruction 2, and other relevant information as address-related information of instruction 2 to the counting buffer 150, and determines the information identifier corresponding to the address-related information according to the storage location of the address-related information in the counting buffer 150. For example, if the address-related information of instruction 2 is created in the table entry 5 of the counting buffer 150, then the information identifier of instruction 2 is 5.

[0090] Since no jump is predicted, the next instruction to be executed should be instruction 3 located at 0xc. Therefore, the instruction fetch unit 110 updates the value of the instruction fetch counter 172 to 0xc.

[0091] Subsequently, the instruction fetch unit 110 sends instruction 2 and the information identifier of instruction 2 to the instruction decoding unit 120 .

[0092] The instruction decoding unit 120 decodes instruction 2, determines instruction information such as the operation type of instruction 2 is bltz, the operand address is register x5, and the instruction length is 32 bits, and sends these instruction information and the information identifier of instruction 2 to the instruction execution unit 130.

[0093] The instruction execution unit 130 obtains the predicted result of instruction 2, "no jump", from the count buffer 150 according to the information identifier. In addition, the instruction execution unit 130 executes instruction 2, obtains the value of x from register x5, and determines whether the value of x is less than 0. If x<0, instruction 2 should jump, and the actual execution result of instruction 2 is inconsistent with the predicted result of the instruction fetch unit 110, that is, the prediction is wrong; otherwise (i.e. x≥0), instruction 2 does not jump, and the actual execution result of instruction 2 is consistent with the predicted result of the instruction fetch unit 110, that is, the prediction is correct.

[0094] The instruction execution unit 130 sends the judgment result of whether the prediction is correct and the information identification of instruction 2 to the instruction retirement unit 140.

[0095] Assuming that the prediction is correct, the instruction execution unit 130 will send the correct prediction result and the information identifier of instruction 2 to the instruction retirement unit 140. The instruction retirement unit 140 obtains the address information 0x8 of instruction 2 and the prediction result "no jump" from the count buffer 150 according to the information identifier of instruction 2, and then pops up the table entry corresponding to instruction 2 from the count buffer 150, that is, deletes the address-related information of instruction 2 cached in the count buffer 150. The instruction retirement unit 140 calculates that the address of the next instruction to be executed when no jump is 0xc based on the address information 0x8 of instruction 2 and the correct prediction result "no jump", and then updates the value of the retirement counter 174 to 0xc. Next, instruction 3 is executed.

[0096] Assuming that the prediction is wrong, the instruction execution unit 130 will send the prediction error result and the information identifier of instruction 2 to the instruction retirement unit 140. According to the information identifier of instruction 2, the instruction retirement unit 140 obtains the address information 0x8 of instruction 2 and the prediction result "no jump" from the count buffer 150, and then pops the table entry corresponding to instruction 2 from the count buffer 150, that is, deletes the address related information of instruction 2 cached in the count buffer 150. According to the address information 0x8 of instruction 2 and the prediction error prediction result "no jump", the instruction retirement unit 140 calculates that the address of the next instruction to be executed when jumping is 0x14, and then updates the value of the retirement counter 174 to 0x14. In addition, since the address in the current instruction fetch counter 172 is obtained by the instruction fetch unit 110 based on the wrong prediction result, the address information stored in the current instruction fetch counter 172 is also wrong and needs to be corrected. The instruction retirement unit updates the correct address information 0x14 of the next instruction to be executed to the instruction fetch counter 172. Next, instruction 5 is executed.

[0097] The execution process of instruction 3 is as follows:

[0098] The instruction fetch unit 110 reads instruction 3 according to the address 0xc in the instruction fetch counter 172. The instruction fetch unit 110 pre-decodes instruction 3 and determines that instruction 3 is a sequential instruction, not a jump instruction. Therefore, the next instruction to be read is instruction 4 after instruction 3, and updates the value of the instruction fetch counter 172 to the address of instruction 4, that is, 0x10. Subsequently, instruction 3 is sent to the instruction decoding unit 120.

[0099] The instruction decoding unit 120 decodes instruction 3, determines that the operation type of instruction 3 is a data transfer operation mv (move), the source address of the data transfer operation is register x5, the target address is register x6, and the instruction length is 32 bits, and sends this instruction information to the instruction execution unit 130.

[0100] The instruction execution unit 130 receives the instruction information sent by the instruction decoding unit 120, takes out the value of x from the source address (register x5), and then sends the execution result of the instruction (the value of x taken out) and the target address register x6, as well as the information that the instruction length is 32 bits to the instruction retirement unit 140.

[0101] The instruction retirement unit 140 writes the value of x into register x6 and updates the value of the retirement counter 174 to the address 0x10 of instruction 4 (i.e., the original value 0xc plus the instruction length 32 bits).

[0102] The execution process of instruction 4:

[0103] The instruction fetch unit 110 reads instruction 4 according to the address 0x10 in the instruction fetch counter 172. The instruction fetch unit 110 pre-decodes instruction 4 and determines that instruction 4 is an unconditional jump instruction based on the operation code j (jump) of instruction 4. Subsequently, the instruction fetch unit 110 creates the address 0x10 of instruction 4 and other related information as address related information of instruction 4 to the counting buffer 150, and determines the information identifier corresponding to the address related information according to the storage position of the address related information in the counting buffer 150. For example, if the address related information of instruction 4 is created to the table entry 6 of the counting buffer 150, then the information identifier of instruction 4 is 6.

[0104] Since instruction 4 is an unconditional jump instruction, instruction 4 will jump unconditionally to the target address 0x18 after execution. Therefore, the instruction fetch unit 110 updates the value of the instruction fetch counter 172 to 0x18.

[0105] Subsequently, the instruction fetch unit 110 sends instruction 4 and the information identifier of instruction 4 to the instruction decoding unit 120. The instruction decoding unit 120 decodes instruction 4, determines instruction information such as the operation type of instruction 4 being j and the instruction length being 32 bits, and sends the instruction information and the information identifier of instruction 4 to the instruction execution unit 130.

[0106] The instruction execution unit 130 obtains the address information 0x10 of instruction 4 from the counting buffer 150 according to the information identifier of instruction 4, determines that the execution result of instruction 4 is “jump”, and sends the execution result “jump” and the information identifier of instruction 4 to the instruction retirement unit 140 .

[0107] The instruction retirement unit 140 obtains the address information 0x10 of instruction 4 from the count buffer 150 according to the information identifier, and then pops the table entry corresponding to instruction 4 from the count buffer 150, that is, deletes the address information of instruction 4 cached in the count buffer 150. The instruction retirement unit calculates the address of the next instruction as 0x18 based on the execution result (jump) of instruction 4 and the address information 0x10, and updates the value of the retirement counter 174 to 0x18.

[0108] The execution process of instruction 5:

[0109] If the instruction fetch unit 110 predicts an error when executing instruction 2, the instruction retirement unit 140 will update the values ​​of the instruction fetch counter 172 and the retirement counter 174 to 0x14.

[0110] The instruction fetch unit 110 reads instruction 5 according to the address 0x14 in the instruction fetch counter 172. The instruction fetch unit 110 pre-decodes instruction 5 and determines that instruction 5 is a sequential instruction, not a jump instruction. Therefore, the next instruction to be read is instruction 6 after instruction 5, and the value of the instruction fetch counter 172 is updated to the address of instruction 6, that is, 0x18. Subsequently, instruction 5 is sent to the instruction decoding unit 120.

[0111] The instruction decoding unit 120 decodes instruction 5, determines that the operation type of instruction 5 is the negated data transfer operation neg (negative), the source address of the data transfer operation is register x5, the target address is register x6, and the instruction length is 32 bits and other instruction information, and sends this instruction information to the instruction execution unit 130.

[0112] The instruction execution unit 130 receives the instruction information sent by the instruction decoding unit 120, takes out the value of x from the source address (register x5), then inverts x, and sends the execution result of the instruction (-value of x) and the target address register x6, as well as the instruction length of 32 bits to the instruction retirement unit 140.

[0113] The instruction retirement unit 140 writes the value of -x into register x6 and updates the value of the retirement counter 174 to the address 0x18 of instruction 6 (i.e., the original value 0x14 plus the instruction length of 32 bits).

[0114] The execution process of instruction 6:

[0115] The instruction fetch unit 110 reads instruction 6 according to the address 0x18 in the instruction fetch counter 172. The instruction fetch unit 110 pre-decodes instruction 6 and determines that instruction 6 is a sequential instruction, not a jump instruction, and that instruction 6 is the last instruction in the instruction fragment. At this time, the value of the instruction fetch counter 172 is no longer updated. Subsequently, instruction 6 is sent to the instruction decoding unit 120.

[0116] The instruction decoding unit 120 decodes instruction 6, determines that the operation type of instruction 6 is a memory write operation sw (save word), the source address of the write operation is register x6, the target memory address is the content stored in register x8, and the length of the instruction is 32 bits and other instruction information, and sends this instruction information to the instruction execution unit 130.

[0117] The instruction execution unit 130 receives the instruction information sent by the instruction decoding unit 120, takes out the value of y from the source address (register x6), and then sends the execution result of the instruction (the taken out value of y) and the target memory address 0 (x8), as well as the instruction length of 32 bits to the instruction retirement unit 140.

[0118] The instruction retirement unit 140 writes the value of y into the address indicated by register x8. The entire instruction fragment is executed.

[0119] It should be noted that, although the processing process of each instruction is described separately in the above embodiments, those skilled in the art can understand that, based on the pipeline technology, the processing process of each instruction may overlap in time. In other words, multiple instructions may be processed on the pipeline at a certain moment (for example, at a certain moment, the instruction fetch unit reads instruction 2, and the instruction decoding unit is decoding instruction 1 at the same time), rather than waiting for the previous instruction to exit the pipeline before executing the next instruction.

[0120] Figure 3 FIG. 3 is a flow chart of an instruction processing method 300 according to an embodiment of the present invention. The instruction processing method 300 is executed in the instruction processing device 100 of the present invention to avoid the address information of the instruction being stored and transmitted on the pipeline. Figure 3 As shown, the method 300 starts at step S310 .

[0121] In step S310, when the instruction fetch unit reads a jump instruction, the address-related information of the jump instruction is stored in a counting buffer, and an information identifier corresponding to the address-related information is passed to the instruction execution unit, wherein the address-related information includes the address information of the jump instruction in the storage device.

[0122] According to one embodiment, before step S310, the instruction fetching unit determines whether the read instruction is a jump instruction according to the following steps: the instruction fetching unit pre-decodes the read instruction to determine the operation code of the instruction, and determines whether the instruction is a jump instruction according to the operation code. Further, the jump instruction includes a conditional jump instruction and an unconditional jump instruction, and the instruction fetching unit determines whether the instruction is a conditional jump instruction or an unconditional jump instruction according to the operation code of the instruction.

[0123] In step S310, the address-related information of the jump instruction includes, but is not limited to, the address information of the jump instruction in the storage device. According to one embodiment, the address-related information may include, in addition to the address information of the jump instruction, information such as the type of the jump instruction (conditional jump instruction, unconditional jump instruction, or a type classified according to other classification criteria), the prediction result of the branch instruction, and the like. The specific information items included in the address-related information may differ according to the different types of jump instructions.

[0124] According to one embodiment, when the instruction fetch unit reads a conditional jump instruction, it predicts whether the conditional jump instruction will jump, and uses the prediction result and the address information of the conditional jump instruction as address-related information of the conditional jump instruction, and stores them in a counting buffer. In addition, the instruction fetch unit also determines the address information of the next instruction to be read based on the prediction result, and updates the address information of the next instruction to be read to the instruction fetch counter.

[0125] According to one embodiment, when the instruction fetch unit reads an unconditional jump instruction, it determines the jump target address of the unconditional jump instruction, uses the jump target address as address information of the next instruction to be read, and updates the instruction fetch counter.

[0126] According to one embodiment, the information identifier of the address-related information of the jump instruction is determined according to the storage position of the address-related information of the jump instruction in the counting buffer. For example, the counting buffer includes N table entries, each of which is used to store the address-related information of a jump instruction, then the counting buffer can store at most N address-related information of jump instructions. If the address-related information of a jump instruction is stored in the 5th table entry of the counting buffer, then the information identifier of the address-related information of the jump instruction can be set to 5 accordingly.

[0127] After storing the address-related information of the jump instruction in the counting buffer and determining the information identifier corresponding to the address-related information, the instruction fetch unit sends the jump instruction and the information identifier to the instruction decoding unit. The instruction decoding unit decodes the jump instruction and sends the decoding result together with the information identifier to the instruction execution unit.

[0128] Subsequently, in step S320, the instruction execution unit obtains address-related information of the jump instruction from the counting buffer according to the information identifier, and executes the jump instruction according to the address-related information.

[0129] According to one embodiment, the method 300 further includes step S330 (step S330 is Figure 3 (not shown), step S330 is performed after step S320.

[0130] In step S330, the instruction retirement unit receives the information identifier sent by the instruction execution unit, obtains the address-related information of the jump instruction from the counting buffer according to the information identifier, and retires the jump instruction according to the address-related information. For example, the instruction retirement unit updates the address information in the retirement counter 174 according to the address-related information, and writes back the execution result of the instruction to the register or storage device, etc.

[0131] The specific process of executing the jump instruction in step S320 and retiring the jump instruction in step S330 varies according to the type of the jump instruction.

[0132] When the jump instruction is a conditional jump instruction, in step S320, the instruction execution unit executes the conditional jump instruction and determines whether the jump condition is established to obtain the execution result of whether the jump occurs. And, according to the information identifier, the prediction result of the conditional jump instruction is obtained from the counting buffer. The instruction execution unit determines whether the obtained prediction result is consistent with the actual execution result of the conditional jump instruction, and sends the judgment result and the information identifier to the instruction retirement unit so that the instruction retirement unit executes the subsequent step S330 to retire the conditional jump instruction.

[0133] In step S330, the instruction retirement unit receives the judgment result and information identifier sent by the instruction execution unit, obtains the address-related information of the conditional jump instruction from the counting buffer according to the information identifier, and then deletes the address-related information of the conditional jump instruction stored in the counting buffer. Subsequently, the instruction retirement unit determines the address information of the next instruction to be retired (i.e., the next instruction to be executed) according to the judgment result sent by the instruction execution unit, and the address information and prediction result of the conditional jump instruction obtained from the counting buffer, and updates the address information of the next instruction to be retired to the retirement counter.

[0134] Specifically, when the judgment result sent by the instruction execution unit indicates that the predicted result of the conditional jump instruction is consistent with the actual execution result, it indicates that the prediction is correct. The instruction retirement unit can determine the address information of the next instruction to be executed based on the address information and the predicted result (i.e., the actual execution result) of the conditional jump instruction. The next instruction to be executed is the next instruction to be retired, and the address information of the next instruction to be executed is updated to the retirement counter. In addition, since the prediction is correct, the address information of the next instruction stored in the current instruction fetch counter is also correct and does not need to be corrected.

[0135] When the judgment result sent by the instruction execution unit indicates that the predicted result of the conditional jump instruction is inconsistent with the actual execution result, it indicates a prediction error. In this case, the instruction retirement unit determines the address information of the next instruction to be executed based on the address information of the conditional jump instruction and the actual execution result (the actual execution result is opposite to the predicted result), and updates the address information of the next instruction to be executed to the retirement counter. In addition, the address information of the next instruction currently stored in the instruction fetch counter is determined based on the prediction result. Due to the prediction error, the address information stored in the instruction fetch counter is also wrong and needs to be corrected. Therefore, according to one embodiment, when the judgment result indicates that the predicted result of the conditional jump instruction is inconsistent with the actual execution result, the instruction retirement unit re-determines the address information of the next instruction to be read (i.e., to be executed) based on the judgment result and the address information of the conditional jump instruction, and updates the address information of the next instruction to be read to the instruction fetch counter.

[0136] When the jump instruction is an unconditional jump instruction, in step S320, the instruction execution unit executes the unconditional jump instruction to obtain the execution result of the determined jump. In addition, the instruction execution unit can obtain address-related information from the counting buffer according to the information identifier to further determine the execution result of the jump. Subsequently, the instruction execution unit sends the execution result of the determined jump and the information identifier to the instruction retirement unit so that the instruction retirement unit executes the subsequent step S330 to retire the jump instruction, that is, determine the address information of the next instruction to be retired (i.e., to be executed) according to the execution result and the information identifier, and update the address information of the next instruction to be retired to the retirement counter.

[0137] In step S330, the instruction retirement unit receives the execution result and information identifier of the determined jump sent by the instruction execution unit, obtains the address-related information of the unconditional jump instruction from the counting buffer according to the information identifier, and then deletes the address-related information of the unconditional jump instruction stored in the counting buffer. Subsequently, the instruction retirement unit determines the jump target address of the unconditional jump instruction (the jump target address is the address of the next instruction to be executed and retired) according to the address information of the unconditional jump instruction and the execution result of the determined jump sent by the instruction execution unit, and updates the retirement counter with the jump target address as the address information of the next instruction to be retired.

[0138] As described above, the instruction processing device according to the present invention can be implemented as a processor core, and the instruction processing method can be executed in the processor core. The processor core can be implemented in different processors in different ways. For example, the processor core can be implemented as a general-purpose in-order core for general-purpose computing, a high-performance general-purpose out-of-order core for general-purpose computing, and a dedicated core for graphics and / or scientific (throughput) computing. The processor can be implemented as a CPU (central processing unit) and / or a coprocessor, wherein the CPU may include one or more general-purpose in-order cores and / or one or more general-purpose out-of-order cores, and the coprocessor may include one or more dedicated cores. Such a combination of different processors can lead to different computer system architectures. In one computer system architecture, the coprocessor is on a chip separate from the CPU. In another computer system architecture, the coprocessor is in the same package as the CPU but on a separate die. In another computer system architecture, the coprocessor is on the same die as the CPU (in this case, such a coprocessor is sometimes referred to as a dedicated logic such as integrated graphics and / or scientific (throughput) logic, or is referred to as a dedicated core). In a computer system architecture also known as a system on a chip, the described CPU (sometimes called an application core or application processor), the coprocessors described above, and additional functionality may be included on the same die.

[0139] Figure 4 FIG. 4 is a schematic diagram of a processor 400 according to an embodiment of the present invention. Figure 4 As shown in the solid line box in FIG. 1 , according to one embodiment, the processor 40 includes a single core 410-1, a system agent unit 420, and a bus controller unit 430. Figure 4 As shown in the dashed box in , according to another embodiment of the present invention, the processor 400 may further include multiple cores 410 -N, an integrated memory controller unit 422 in the system agent unit 420 , and a dedicated logic 440 .

[0140] According to one embodiment, the processor 400 may be implemented as a central processing unit (CPU), wherein the dedicated logic 440 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and the cores 410-1 to 410-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of the two). According to another embodiment, the processor 400 may be implemented as a coprocessor, wherein the cores 410-1 to 410-N are multiple dedicated cores for graphics and / or science (throughput). According to yet another embodiment, the processor 400 may be implemented as a coprocessor, wherein the cores 410-1 to 410-N are multiple general-purpose in-order cores. Therefore, the processor 400 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), or an embedded processor, etc. The processor may be implemented on one or more chips. Processor 400 may be part of and / or implemented on one or more substrates using any of a number of processing technologies such as, for example, BiCMOS, CMOS, or NMOS.

[0141] The memory hierarchy includes one or more levels of cache within each core, one or more shared cache units 450, and external memory (not shown) coupled to the integrated memory controller unit 422. The shared cache unit 450 may include one or more intermediate level caches, such as a second level (L2), third level (L3), fourth level (L4), or other level of cache, a last level cache (LLC), and / or combinations thereof. Although in one embodiment, a ring-based interconnect unit 452 interconnects the integrated graphics logic 440, the shared cache unit 450, and the system agent unit 420 / integrated memory controller unit 422, the present invention is not limited thereto, and any number of well-known techniques may be used to interconnect these units.

[0142] The system agent unit 420 includes those components that coordinate and operate the cores 410-1 to 410-N. The system agent unit 420 may include, for example, a power control unit (PCU) and a display unit. The PCU may include logic and components required to adjust the power state of the cores 410-1 to 410-N and the integrated graphics logic 440. The display unit is used to drive one or more externally connected displays.

[0143] The cores 410-1 to 410-N may have the above reference Figure 1The core architectures described herein may be homogeneous or heterogeneous in terms of the architecture instruction set. That is, two or more of the cores 410-1 to 410-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set.

[0144] Figure 5 FIG. 5 is a schematic diagram of a system on chip (SoC) 500 according to an embodiment of the present invention. Figure 5 The system-on-chip shown contains Figure 4 The processor 400 shown is therefore Figure 4 Similar parts in the drawings have the same reference numerals. Figure 5 As shown, the interconnect unit 520 is coupled to the application processor 510, the system agent unit 420, the bus controller unit 430, the integrated memory controller unit 422, one or more coprocessors 530, a static random access memory (SRAM) unit 540, a direct memory access (DMA) unit 550, and a display unit 560 for coupling to one or more external displays. The application processor 510 includes a set of one or more cores 410-1 to 410-N and a shared cache unit 450. The coprocessor 530 includes integrated graphics logic, an image processor, an audio processor, and a video processor. In one embodiment, the coprocessor 530 includes a special-purpose processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, or an embedded processor, etc.

[0145] In addition, the system on chip described above can be included in a smart device to implement corresponding functions in the smart device, including but not limited to executing relevant control programs, performing data analysis, calculation and processing, network communication, and controlling peripherals in the smart device.

[0146] Such intelligent devices include specialized intelligent devices, such as mobile terminals and personal digital terminals, etc. These devices include one or more systems on a chip according to the present invention to process data or control peripherals in the devices.

[0147] Such smart devices also include specialized devices constructed to achieve specific functions, such as smart speakers and smart display devices, etc. These devices include a system on a chip according to the present invention to control the speakers and display devices, thereby giving the speakers and display devices additional communication, perception, and data processing functions.

[0148] Such smart devices also include various IoT and AIoT devices. These devices include a system-on-chip according to the present invention for data processing, such as AI computing, data communication and transmission, etc., thereby achieving a denser and more intelligent device distribution.

[0149] Such smart devices can also be used in vehicles, for example, they can be implemented as vehicle-mounted devices, or can be embedded in vehicles, thereby providing data processing capabilities for the vehicle's intelligent driving.

[0150] Such smart devices can also be used in the field of home and entertainment, for example, they can be implemented as smart speakers, smart air conditioners, smart refrigerators, smart display devices, etc. These devices include the system on chip according to the present invention to perform data processing and peripheral control, thereby realizing the intelligence of home and entertainment devices.

[0151] In addition, such intelligent devices can also be used in the industrial field, for example, they can be implemented as industrial control equipment, sensing equipment, IoT equipment, AIoT equipment and braking equipment, etc. These devices include the system on chip according to the present invention to perform data processing and peripheral control, thereby realizing the intelligence of industrial equipment.

[0152] The above description of the smart device is merely illustrative, and the smart device according to the present invention is not limited thereto. All smart devices that can use the system on chip according to the present invention to perform data processing are within the protection scope of the present invention.

[0153] The various embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of the present invention may be implemented as a computer program or program code executed on a programmable system, the programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0154] It should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than those explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0155] Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in the devices described in the embodiment, or alternatively may be located in one or more devices different from the devices in the examples. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.

[0156] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0157] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0158] In addition, some of the embodiments are described herein as methods or combinations of method elements that can be implemented by a processor of a computer system or by other devices that perform the functions. Therefore, a processor with necessary instructions for implementing the method or method elements forms a device for implementing the method or method elements. In addition, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements for the purpose of implementing the invention.

[0159] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved, and is not intended to imply that the objects so described must have a given order in time, space, order, or in any other manner.

[0160] Although the present invention has been described according to a limited number of embodiments, it will be apparent to those skilled in the art, with the benefit of the above description, that other embodiments may be envisioned within the scope of the invention thus described. In addition, it should be noted that the language used in this specification is selected primarily for readability and teaching purposes, rather than for explaining or defining the subject matter of the present invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is illustrative, not restrictive, with respect to the scope of the present invention, which is defined by the appended claims.

Claims

1. An instruction processing device, comprising: An instruction fetch unit, an instruction execution unit and a counting buffer, wherein the counting buffer is coupled to the instruction fetch unit and the instruction execution unit respectively, wherein: Each table entry included in the counting buffer is used as a storage location to store address related information of a jump instruction; The instruction fetch unit is adapted to store address-related information of the jump instruction in a table entry included in the count buffer when reading the jump instruction, and transmit an information identifier corresponding to the address-related information to the instruction execution unit, wherein the information identifier is determined according to a storage position of the address-related information of the jump instruction in the count buffer, and the address-related information includes address information of the jump instruction in a storage device; The instruction execution unit is adapted to obtain address-related information of the jump instruction from the counting buffer according to the information identifier, and execute the jump instruction according to the address-related information.

2. The apparatus of claim 1, further comprising: An instruction retirement unit is coupled to the instruction execution unit and the counting buffer respectively, and is adapted to receive the information identifier sent by the instruction execution unit, and obtain address-related information of the jump instruction from the counting buffer according to the information identifier, so as to retire the jump instruction.

3. The device according to claim 1 or 2, wherein: The instruction fetch unit is adapted to: Pre-decoding the read instruction to determine the operation code of the instruction; It is determined whether the instruction is a jump instruction according to the operation code.

4. The device according to any one of claims 1 to 2, wherein: The jump instructions include conditional jump instructions and unconditional jump instructions.

5. The device according to claim 4, wherein: The instruction fetch unit is further adapted to: When a conditional jump instruction is read, it is predicted whether the conditional jump instruction will jump, and the prediction result and the address information of the conditional jump instruction are used as address related information of the conditional jump instruction and stored in the counting buffer.

6. The apparatus of claim 5, wherein the instruction fetch unit is further adapted to: The address information of the next instruction to be read is determined according to the prediction result.

7. The apparatus according to claim 5 or 6, wherein the instruction execution unit is adapted to: Executing the conditional jump instruction to obtain an execution result of whether a jump occurs; Acquire a prediction result of the conditional jump instruction from the counting buffer according to the information identifier; Determine whether the prediction result is consistent with the execution result of the conditional jump instruction, and send the judgment result and the information identifier to the instruction retirement unit so that the instruction retirement unit can determine the address information of the next instruction to be retired based on the judgment result and the information identifier.

8. The device according to claim 7, wherein: The instruction retirement unit is suitable for: receiving the determination result and the information identifier sent by the instruction execution unit; Acquire address-related information of the conditional jump instruction from the counting buffer according to the information identifier, and delete the address-related information of the conditional jump instruction from the counting buffer; as well as The address information of the next instruction to be retired is determined according to the judgment result and the address information and prediction result of the conditional jump instruction.

9. The device of claim 8, wherein: The instruction retirement unit is also adapted to: When the judgment result is inconsistent, the address information of the next instruction to be read is re-determined according to the judgment result and the address information of the conditional jump instruction.

10. The device of claim 4, wherein: The instruction fetch unit is further adapted to: When an unconditional jump instruction is read, a jump target address of the unconditional jump instruction is determined, and the jump target address is used as address information of the next instruction to be read.

11. The device of claim 10, wherein: The instruction execution unit is also adapted to: Execute the unconditional jump instruction to obtain an execution result of determining the jump, and send the execution result and the information identifier to the instruction retirement unit.

12. The device of claim 11, wherein: The instruction retirement unit is also adapted to: Receiving the execution result and information identification of the unconditional jump instruction sent by the instruction execution unit; Acquire address-related information of the unconditional jump instruction from the counting buffer according to the information identifier, and delete the address-related information of the unconditional jump instruction from the counting buffer; as well as The jump target address of the unconditional jump instruction is determined according to the address information of the unconditional jump instruction and the execution result, and the jump target address is used as the address information of the next instruction to be retired.

13. The device of claim 1, wherein: The counting buffer adopts a queue data structure.

14. An instruction processing method, executed in an instruction processing device, the instruction processing device comprising an instruction fetch unit, an instruction execution unit and a counting buffer, each entry contained in the counting buffer being used as a storage location for storing address related information of a jump instruction, the method comprising the steps of: When the instruction fetch unit reads a jump instruction, the address related information of the jump instruction is stored in a table entry included in the counting buffer, and the information identifier corresponding to the address related information is transmitted to the instruction execution unit, wherein, The information identifier is determined according to the storage location of the address related information of the jump instruction in the counting buffer, and the address related information includes the address information of the jump instruction in the storage device; The instruction execution unit obtains address-related information of the jump instruction from the counting buffer according to the information identifier, and executes the jump instruction according to the address-related information.

15. The method of claim 14, wherein: The instruction processing device further includes an instruction retirement unit, and the method further includes the steps of: The instruction retirement unit receives the information identifier sent by the instruction execution unit, obtains address-related information of the jump instruction from the counting buffer according to the information identifier, and retires the jump instruction according to the address-related information.

16. The method according to claim 14 or 15, before the step of storing the address related information of the jump instruction into the counting buffer, further comprising the step of: Pre-decoding the read instruction to determine the operation code of the instruction; It is determined whether the instruction is a jump instruction according to the operation code.

17. The method according to any one of claims 14 to 15, wherein: The jump instructions include conditional jump instructions and unconditional jump instructions.

18. The method of claim 17, further comprising the steps of: When a conditional jump instruction is read, predict whether the conditional jump instruction will jump; The prediction result and the address information of the conditional jump instruction are used as address related information of the conditional jump instruction and stored in the counting buffer.

19. The method according to claim 18, further comprising the step of: The address information of the next instruction to be read is determined according to the prediction result.

20. The method of claim 18 or 19, wherein: The step of executing the jump instruction according to the address related information comprises: Executing the conditional jump instruction to obtain an execution result of whether a jump occurs; Acquire a prediction result of the conditional jump instruction from the counting buffer according to the information identifier; It is determined whether the prediction result is consistent with the execution result of the conditional jump instruction, so as to determine the address information of the next instruction to be retired according to the determination result and the information identifier.

21. The method of claim 20, wherein: The step of determining the address information of the next instruction to be retired according to the judgment result and the information identifier comprises: Acquire address-related information of the conditional jump instruction from the counting buffer according to the information identifier, and delete the address-related information of the conditional jump instruction from the counting buffer; and The address information of the next instruction to be retired is determined according to the judgment result and the address information and prediction result of the conditional jump instruction.

22. The method of claim 21, further comprising the steps of: When the judgment result is inconsistent, the address information of the next instruction to be read is re-determined according to the judgment result and the address information of the conditional jump instruction.

23. The method of claim 17, further comprising the steps of: When an unconditional jump instruction is read, a jump target address of the unconditional jump instruction is determined, and the jump target address is used as address information of the next instruction to be read.

24. The method of claim 23, wherein: The step of executing the jump instruction according to the address related information comprises: The unconditional jump instruction is executed to obtain an execution result of determining the jump, so as to determine the address information of the next instruction to be retired according to the execution result and the information identifier.

25. The method of claim 24, wherein: The step of determining the address information of the next instruction to be retired according to the execution result and the information identifier comprises: Acquire address-related information of the unconditional jump instruction from the counting buffer according to the information identifier, and delete address-related information of the unconditional jump instruction from the counting buffer; and The jump target address of the unconditional jump instruction is determined according to the address information of the unconditional jump instruction and the execution result, and the jump target address is used as the address information of the next instruction to be retired.

26. A system on chip, comprising the instruction processing device according to any one of claims 1 to 13.

27. An intelligent device comprising the system on chip according to claim 26.

Images