Semiconductor device processing method and semiconductor device

Abstract

The present application provides a method for processing a semiconductor device and a semiconductor device. The method for processing a semiconductor device includes: providing a semiconductor preform; wherein the semiconductor preform includes a substrate, a first dielectric layer disposed on a surface of the substrate, and at least one metal lead embedded in the first dielectric layer; a groove is formed on the surface of the first dielectric layer away from the substrate, and the groove exposes the metal lead; a connection pad is formed in the groove, the connection pad is connected to the metal lead, and the upper surface of the connection pad is lower than the surface of the first dielectric layer away from the substrate; a needle test is performed on the semiconductor preform; wherein a convex portion is formed on the surface of the connection pad after the needle test is performed on the semiconductor preform; a second dielectric layer is formed on the surface of the first dielectric layer away from the substrate, and the second dielectric layer covers the convex portion. This method can greatly reduce the thickness of the resulting product, which is conducive to the development of the product in the direction of lightness and thinness.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a processing method of a semiconductor device and a semiconductor device. Background Art

[0002] With the continuous development of semiconductor technology, 3D-IC (three-dimensional integrated circuit) technology has been widely used, which has made great contributions to the realization of high-performance interconnection integration of overall circuits.

[0003] At present, the processing method of semiconductor devices generally forms connection pads on the surface of semiconductor preforms after forming semiconductor preforms, and connects the connection pads with the metal layer in the semiconductor preforms, and then uses a probe to apply a certain force to contact the connection pads on the surface of the semiconductor preforms and conduct tests. However, after the connection pads are pierced with needles, they usually leave obvious protrusions or needle marks, which affects the flatness of the semiconductor device and the performance of the device; in order to solve this problem, a sufficiently thick dielectric layer is generally deposited on the surface of the semiconductor preform so that the dielectric layer completely covers the protrusions or needle marks on the connection pads, and the dielectric layer is mechanically polished multiple times to ensure the flatness of the surface of the semiconductor device.

[0004] However, the above method requires a thicker dielectric layer to be deposited, which not only greatly increases the thickness of the semiconductor device, but is also not conducive to the development of the product towards lighter and thinner dimensions, and requires more mechanical polishing. Summary of the invention

[0005] The semiconductor device processing method and semiconductor device provided in the present application can solve the problem that the existing method requires a thick dielectric layer to be deposited, which not only greatly increases the thickness of the semiconductor device and is not conducive to the development of the product in the direction of thinness and lightness, but also requires a large number of mechanical polishing times.

[0006] In order to solve the above technical problems, a technical solution adopted by the present application is: to provide a method for processing a semiconductor device. The method includes: providing a semiconductor preform; wherein the semiconductor preform includes a substrate, a first dielectric layer arranged on a surface of the substrate, and at least one metal lead end embedded in the first dielectric layer; a groove is formed on the surface of the first dielectric layer away from the substrate, and the groove exposes the metal lead end; a connection pad is formed in the groove, the connection pad is connected to the metal lead end, and the upper surface of the connection pad is lower than the surface of the first dielectric layer away from the substrate; a needle test is performed on the semiconductor preform; wherein a convex portion is formed on the surface of the connection pad after the needle test is performed on the semiconductor preform; a second dielectric layer is formed on the surface of the first dielectric layer away from the substrate, and the second dielectric layer covers the convex portion.

[0007] After forming a second dielectric layer on the surface of the first dielectric layer away from the substrate and covering the protrusion with the second dielectric layer, the method further includes: planarizing the second dielectric layer and processing the surface of the second dielectric layer away from the first dielectric layer to expose the connection pad for subsequent bonding.

[0008] The metal lead-out terminal is formed at a position of the first dielectric layer closest to the substrate and is located below the bottom of the trench.

[0009] The semiconductor preform further includes a plurality of metal layers embedded in the first dielectric layer, the plurality of metal layers are interconnected and are led out through metal lead-out terminals to be electrically connected to the connection pads.

[0010] The metal lead-out terminal is offset from the multi-layer metal layer, and the groove and the multi-layer metal layer are spaced apart from each other in a direction parallel to the first dielectric layer.

[0011] The step of forming a connection pad in the groove specifically includes: depositing a conductive layer at least in the groove; processing the conductive layer so that the upper surface of the conductive layer is lower than the surface of the first dielectric layer away from the substrate.

[0012] Among them, the step of depositing a conductive layer at least in the groove specifically includes: depositing a conductive layer on the surface of the first dielectric layer away from the substrate and in the groove; the step of processing the conductive layer specifically includes: removing the conductive layer located on the surface of the first dielectric layer away from the substrate, and removing part of the conductive layer located at the edge of the groove; and thinning the conductive layer located in the groove.

[0013] After the step of forming the second dielectric layer on the surface of the first dielectric layer away from the substrate, the method further includes: polishing the surface of the second dielectric layer away from the first dielectric layer.

[0014] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a semiconductor device. The semiconductor device includes a substrate, a first dielectric layer, at least one metal lead, a connection pad and a second dielectric layer; wherein the first dielectric layer is arranged on a surface of the substrate, and a groove is provided on the surface of the first dielectric layer away from the substrate; at least one metal layer is embedded in the first dielectric layer; wherein the substrate, the first dielectric layer and the at least one metal lead form a semiconductor preform; the connection pad includes a protrusion, the connection pad is accommodated in the groove and is connected to the at least one metal lead for needle testing; wherein the upper surface of the connection pad is lower than the surface of the first dielectric layer away from the substrate; the second dielectric layer is stacked on the surface of the first dielectric layer away from the substrate and covers the protrusion.

[0015] The metal lead-out terminal is located at a position of the first dielectric layer closest to the substrate and below the bottom of the trench.

[0016] The present application provides a method for processing a semiconductor device and a semiconductor device. The method for processing a semiconductor device comprises providing a semiconductor preform; wherein the semiconductor preform comprises a substrate and a first dielectric layer arranged on a surface of the substrate, wherein at least one metal lead end is embedded in the first dielectric layer; then a groove is opened on a surface of the first dielectric layer away from the substrate, the groove exposes the metal lead end, a connection pad connected to the metal lead end is formed in the groove, and the upper surface of the connection pad is lower than the surface of the first dielectric layer away from the substrate; then, a needle test is performed on the semiconductor preform, and a convex portion is formed on the surface of the connection pad after the needle test, and finally, a protrusion is formed on the surface of the first dielectric layer away from the substrate. A second dielectric layer is formed on the surface of the semiconductor device, and the second dielectric layer covers the protruding portion to ensure the flatness of the surface of the semiconductor device; wherein, since the connection pad is located inside the groove of the first dielectric layer, compared with the prior art in which the connection pad is arranged on the surface of the first dielectric layer away from the substrate, the thickness of the product itself is smaller; and since the upper surface of the connection pad is lower than the surface of the first dielectric layer away from the substrate, after the needle test, even if a protruding portion is formed on the connection pad, only a thinner second dielectric layer needs to be deposited on the surface of the first dielectric layer away from the substrate to completely cover the protruding portion on the connection pad, thereby greatly reducing the thickness of the product, which is conducive to the development of the product in the direction of being lighter and thinner. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A flowchart of a method for processing a semiconductor device provided in one embodiment of the present application;

[0018] Figure 2 A schematic diagram of the structure of a semiconductor preform provided in one embodiment of the present application;

[0019] Figure 3 An embodiment of the present application provides Figure 1 A schematic diagram of the product structure after being processed in step S12;

[0020] Figure 4 An embodiment of the present application provides Figure 1 A schematic diagram of the product structure after being processed in step S13;

[0021] Figure 5 An embodiment of the present application provides Figure 1 A schematic diagram of the product structure after being processed in step S14;

[0022] Figure 6a An embodiment of the present application provides Figure 1 A schematic diagram of the product structure after being processed in step S15;

[0023] Figure 6b It is a schematic diagram of the product structure in which a second dielectric layer is formed after a semiconductor preform is subjected to a pin penetration test in the prior art. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0025] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0026] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0027] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0028] See also Figure 1 , Figure 1 A flow chart of a method for processing a semiconductor device provided in one embodiment of the present application; in this embodiment, a method for processing a semiconductor device is provided, which can not only ensure the flatness of the surface of the resulting semiconductor device, but also greatly reduce the thickness of the dielectric layer that needs to be deposited, which is conducive to the development of products in the direction of lighter and thinner.

[0029] Specifically, the method includes:

[0030] Step S11: providing a semiconductor preform.

[0031] Among them, see Figure 2 , Figure 2 A schematic diagram of the structure of a semiconductor preform provided in an embodiment of the present application; the semiconductor preform comprises a substrate 11 and a first dielectric layer 12 disposed on a surface of the substrate 11, and at least one metal layer 13 and at least one metal lead-out terminal 131 are embedded in the first dielectric layer 12. Specifically, the substrate 11 may be a semiconductor substrate 11, such as a silicon substrate, a germanium substrate, etc.; the material of the metal layer 13 may be at least one of an aluminum-copper alloy, aluminum, germanium, and copper, and preferably, the material of the metal layer 13 is copper.

[0032] In a specific implementation process, step S11 specifically includes providing a substrate 11, and then forming a first dielectric layer 12 and a multi-layer metal layer 13 embedded in the first dielectric layer 12 and a metal lead-out terminal 131 on a surface of the substrate 11; specifically, the multi-layer metal layers 13 are interconnected, and one of the metal layers 13 is electrically connected to the metal lead-out terminal 131; in a specific implementation, the metal lead-out terminal 131 is formed at a position of the first dielectric layer 12 closest to the substrate 11, that is, the metal lead-out terminal 131 is formed on the first metal layer 13a and extends to a position where a groove is to be opened in the first dielectric layer 12, wherein the first metal layer 13a specifically refers to the metal layer 13 closest to the substrate 11 among the multi-layer metal layers 13; specifically, the metal lead-out terminal 131 is offset from the multi-layer metal layer 13; that is, the projection of the metal lead-out terminal 131 on the substrate 11 only partially overlaps with the projection of other metal layers 13 on the substrate 11.

[0033] Step S12: a groove is formed on the surface of the first dielectric layer away from the substrate, wherein the groove exposes the metal lead-out terminal.

[0034] Specifically, the product structure after processing in step S12 can be found in Figure 3 , Figure 3 An embodiment of the present application provides Figure 1 Schematic diagram of the product structure after the step S12 is processed; specifically, the groove 121 can be opened on the surface of the first dielectric layer 12 away from the substrate 11 by photolithography and / or etching, and the groove 121 is extended from the surface of the first dielectric layer 12 away from the substrate 11 to a position close to the substrate 11 to increase the depth of the groove 121; specifically, the depth of the groove 121 can be determined according to the protrusion 141 formed by the subsequent needle test (see below) Figure 5); for example, if the height of the protrusion 141 is generally 1-3 microns, the depth of the groove 121 can be at least greater than the total height of the connection pad 14 and the protrusion 141, or only the protrusion 141 not exceeding 0.5 microns is extended out of the opening of the groove 121. Specifically, the diameter of the groove 121 gradually decreases along the direction shown by A.

[0035] In a specific embodiment, a groove 121 is formed at a position of the first dielectric layer 12 away from the surface of the substrate 11 and corresponding to the metal lead-out terminal 131. At this time, the metal lead-out terminal 131 may be located below the bottom of the groove 121, that is, the groove 121 and the metal lead-out terminal 131 are arranged relative to each other in the direction shown by direction A; specifically, the groove 121 and the multi-layer metal layer 13 are arranged at intervals in a direction parallel to the first dielectric layer 12.

[0036] Step S13: forming a connection pad in the groove, the connection pad being connected to the metal lead-out terminal, and the upper surface of the connection pad being lower than the surface of the first dielectric layer away from the substrate.

[0037] Specifically, the product structure after processing in step S13 can be found in Figure 4 , Figure 4 An embodiment of the present application provides Figure 1 Schematic diagram of the product structure after step S13. Specifically, the connection pad 14 is arranged in the groove 121 of the first dielectric layer 12. Compared with the arrangement on the surface of the first dielectric layer 12 away from the substrate 11, the thickness of the product is greatly reduced, which is conducive to the development of the product in the direction of lightness and thinness. Specifically, the connection pad 14 is rectangular and there is a gap between it and the side wall of the groove 121.

[0038] In a specific embodiment, step S13 specifically includes depositing a conductive layer at least in the groove 121, and then processing the conductive layer so that the upper surface of the conductive layer is lower than the surface of the first dielectric layer 12 away from the substrate 11, so as to form a connection pad 14 located in the groove 121. Specifically, the conductive layer can be deposited on the surface of the first dielectric layer 12 away from the substrate 11 and in the groove 121, and then the conductive layer located on the surface of the first dielectric layer 12 away from the substrate 11 is removed by photolithography or etching, and a portion of the conductive layer located on the side wall of the groove 121 is removed, and then the conductive layer located in the groove 121 is thinned to remove a portion of the conductive layer in the groove 121, so that the upper surface of the conductive layer in the groove 121 is lower than the surface of the first dielectric layer 12 away from the substrate 11, so as to form the connection pad 14. The material of the conductive layer can be aluminum, and the formed connection pad 14 is specifically an aluminum pad.

[0039] Specifically, the connection pad 14 is connected to the metal lead-out terminal 131 on the first metal layer 13 a , and the multi-layer metal layer 13 is electrically connected to the connection pad 14 through the metal lead-out terminal 131 .

[0040] Step S14: performing a needle piercing test on the semiconductor preform; wherein, after the needle piercing test on the semiconductor preform, a protrusion is formed on the surface of the connection pad.

[0041] Specifically, the product structure after step S14 can be seen in Figure 5 , Figure 5 An embodiment of the present application provides Figure 1 Schematic diagram of the product structure after step S14; specifically, a probe can be used to act on the connection pad 14 and perform wafer acceptance test (WAT), wafer probe test CP (CP) and other needle tests to test the wafer process and functional verification. The specific test process can be referred to the prior art and will not be repeated here. Figure 5 After the product obtained by this method is subjected to a needle piercing test, only a small portion of the protrusion 141 on the connection pad 14 extends out of the opening of the groove 121, that is, only a portion of the protrusion 141 protrudes from the side surface of the first dielectric layer 12 away from the substrate 11. Compared with the prior art, the height of the protrusion 141 protruding from the side surface of the first dielectric layer 12 away from the substrate 11 is greatly reduced.

[0042] Step S15: forming a second dielectric layer on a surface of the first dielectric layer away from the substrate, wherein the second dielectric layer covers the protrusion.

[0043] Specifically, the product structure after step S15 can be found in Figure 6a , Figure 6a An embodiment of the present application provides Figure 1 Schematic diagram of the product structure after the step S15. In the specific implementation process, since the connection pad 14 is located in the groove 121, the surface of the protrusion 141 on the connection pad 14 away from the substrate 11 may be lower than or slightly higher than the surface of the first dielectric layer 12 away from the substrate 11. Therefore, during the planarization process, only a thin layer of the second dielectric layer 15 needs to be deposited in the groove 121 and / or on the surface of the first dielectric layer 12 away from the substrate 11 to completely cover the protrusion 141 on the connection pad 14; specifically, the thickness of the second dielectric layer 15 can range from 0.3 to 0.5 microns, preferably, 0.5 microns; compared with the thickness of the second dielectric layer 15 formed by the prior art, see Figure 6b , Figure 6bThis is a schematic diagram of the product structure in which the second dielectric layer is formed after the semiconductor preform is subjected to a needle puncture test in the prior art. The solution that the second dielectric layer 15 of 2 microns or even more than 3 microns is required to completely cover the raised portion 141 greatly reduces the thickness of the second dielectric layer 15, which is conducive to the development of the product in the direction of being lighter and thinner. It can be understood that compared with the solution of setting a connection pad 14 on the surface of the semiconductor preform in the prior art, the present application sets a connection pad 14 that is flush with the surface of the first dielectric layer 12 away from the substrate 11 or a connection pad 14 that is lower than the surface of the first dielectric layer 12 away from the substrate 11. After the needle puncture test, the raised portion 141 generated on the connection pad 14 is more easily wrapped by the deposited second dielectric layer 15, which is conducive to the flattening of the product surface. Specifically, in the specific implementation process, in view of the maximum height of the raised portion 141 actually generated, the depth of the groove 121 can be adjusted so that the height extending out of the opening of the groove 121 does not exceed 0.5 microns

[0044] Furthermore, in a specific implementation process, after step S15, the second dielectric layer is planarized, and the surface of the second dielectric layer away from the first dielectric layer is processed to expose the connection pad for subsequent bonding; specifically, in order to ensure the flatness of the surface of the second dielectric layer 15 away from the first dielectric layer 12, the surface of the second dielectric layer 15 away from the first dielectric layer 12 is further polished to improve the flatness of the product; wherein, since the thickness of the second dielectric layer 15 is relatively small, the protrusion 141 on the connection pad 14 does not extend out of the opening of the groove 121 or slightly extends out of the opening of the groove 121, and therefore, the number of polishing times is greatly reduced compared with the prior art.

[0045] Specifically, the step of processing the surface of the second dielectric layer away from the first dielectric layer to expose the connection pad may include forming an opening on the second dielectric layer 15 after the surface is flattened to expose the connection pad 14. It can be understood here that the exposed connection pad 14 may be a protrusion 141 on the connection pad 14 or other positions different from the protrusion 141; specifically, a mask layer may be provided on the second dielectric layer 15 after the surface is flattened, and a window may be formed on the surface of the mask layer as required. In a specific embodiment, the mask layer is a photoresist. Specifically, after the surface of the photoresist away from the second dielectric layer 15 is covered with a mask plate, a light treatment is performed, and the photoresist of the un-illuminated part is washed away to form a through hole, so that the illuminated part forms a mask layer, and part of the surface of the second dielectric layer 15 is exposed through the through hole. Then, the second dielectric layer 15 exposed through the through hole is removed by dry etching, and an opening is formed on the second dielectric layer 15, and part of the connection pad 14 is exposed through the opening. Then, the mask layer on the second dielectric layer 15 is removed to expose the surface of the second dielectric layer 15 away from the connection pad 14. Alternatively, openings may be provided on the second dielectric layer 15 in other ways to expose part of the connection pad 14. It is understood that in other embodiments, the mask layer may not be removed first, and after metal is filled in the opening, the mask layer may be removed during the planarization process.

[0046] It can be understood that the openings may also be other through holes for realizing the function of metal external connection, which is merely an example and not a limitation.

[0047] After the opening is formed, metal is filled in the opening to form a conductive plug; specifically, metal is first deposited in the opening to form a seed layer on the inner wall of the opening, and then the metal is filled into the opening by electroplating to form a conductive plug in the opening. One end of the conductive plug is connected to the connection pad that exposes the second dielectric layer 15. The deposited and plated metal on the second dielectric layer 15 is ground to expose the surface of the second dielectric layer 15 away from the connection pad 14, and at the same time, one end of the conductive plug in the opening is exposed and flush with the surface of the second dielectric layer 15 away from the connection pad 14. In a specific embodiment, a mechanical grinding process can be used to remove excess deposited and plated metal material.

[0048] It can be understood that this method can solve the problem in the prior art that a thicker second dielectric layer needs to be deposited to make the product surface smooth without adding any mask process, and only changes the aluminum pad structure and the metal layer 13 wiring and the depth of the groove 121. The method provided in this application is conducive to achieving the flattening of the product surface after the connection pad 14 is warped after the needle test.

[0049] The processing method of the semiconductor device provided in this embodiment can make the formed connection pad 14 completely located in the groove 121 due to the large depth of the groove 121, so that after the subsequent needle test, the protrusion 141 formed on the connection pad 14 is located in the groove 121 or slightly extends out of the opening of the groove 121, which is not only conducive to the subsequent planarization process, but also can greatly reduce the thickness of the second dielectric layer 15 to be deposited subsequently, and can reduce the number of polishing times, which is conducive to the development of products in the direction of lightness and thinness.

[0050] The processing method of the semiconductor device provided in the present embodiment comprises providing a semiconductor preform; wherein the semiconductor preform comprises a substrate 11 and a first dielectric layer 12 arranged on a surface of the substrate 11, wherein at least one metal lead-out terminal 131 is embedded in the first dielectric layer 12; then a groove 121 is opened on a surface of the first dielectric layer 12 away from the substrate 11, wherein the groove 121 exposes the metal lead-out terminal 131, and a connection pad 14 connected to the metal lead-out terminal 131 is formed in the groove 121, and the upper surface of the connection pad 14 is lower than the surface of the first dielectric layer 12 away from the substrate 11; then, a needle test is performed on the semiconductor preform, and after the needle test, a protrusion 141 is formed on the surface of the connection pad 14, and finally, a first dielectric layer 12 is formed on the surface of the first dielectric layer 12 away from the substrate 11. The second dielectric layer 15 is formed on the first dielectric layer 12, and the second dielectric layer 15 covers the protruding portion 141 to ensure the flatness of the surface of the semiconductor device; wherein, since the connection pad 14 is located inside the groove 121 of the first dielectric layer 12, compared with the prior art in which the connection pad 14 is arranged on the surface of the first dielectric layer 12 away from the substrate 11, the thickness of the product itself is smaller; and since the upper surface of the connection pad 14 is lower than the surface of the first dielectric layer 12 away from the substrate 11, after the needle test, even if the protruding portion 141 is formed on the connection pad 14, it is only necessary to deposit a thinner second dielectric layer 15 on the surface of the first dielectric layer 12 away from the substrate 11 to completely cover the protruding portion 141 on the connection pad 14, thereby greatly reducing the thickness of the product, which is conducive to the development of the product in the direction of lightness and thinness.

[0051] Please continue reading Figures 2 to 6a In this embodiment, a semiconductor device is provided. The semiconductor device has a low thickness and a high flatness. The structure thereof can be specifically referred to in Figure 6a Specifically, the semiconductor device may include a substrate 11, a first dielectric layer 12, at least one metal layer 13, at least one metal lead 131, a connection pad 14 and a second dielectric layer 15. The substrate 11, the first dielectric layer 12, the at least one metal layer 13 and the at least one metal lead 131 form a semiconductor preform.

[0052] The substrate 11 may specifically be a semiconductor substrate, such as a silicon substrate, a germanium substrate, etc.

[0053] Among them, the first dielectric layer 12 is arranged on a surface of the substrate 11, and a groove 121 is opened on the surface of the first dielectric layer 12 away from the substrate 11; specifically, the groove 121 extends from the surface of the first dielectric layer 12 away from the substrate 11 to a position close to the substrate 11 to increase the depth of the groove 121; and the diameter of the groove 121 gradually decreases along the direction shown by the A direction; in a specific embodiment, the metal lead-out terminal 131 is located below the bottom of the groove 121, that is, the groove 121 and the metal lead-out terminal 131 are arranged relative to each other in the direction shown by the A direction.

[0054] Among them, at least one metal layer 13 is embedded in the first dielectric layer 12 and stacked on a surface of the substrate 11; in a specific embodiment, the semiconductor device includes multiple metal layers 13 that are interconnected, the multiple metal layers 13 and the groove 121 are spaced apart in a direction parallel to the first dielectric layer 12, and at least one metal layer 13 in the multiple metal layers 13 is electrically connected to the metal lead-out terminal 131. In a specific implementation, the metal lead-out terminal 131 is formed at the position of the first dielectric layer 12 closest to the substrate 11, that is, the metal lead-out terminal 131 is formed on the first metal layer 13a and extends to the position below the bottom of the groove 121 to be opened in the first dielectric layer 12, wherein the first metal layer 13a specifically refers to the metal layer 13 closest to the substrate 11 among the multiple metal layers 13. Specifically, the metal lead-out terminal 131 is offset from the multiple metal layers 13; that is, the projection of the metal lead-out terminal 131 on the substrate 11 only partially overlaps with the projection of other metal layers 13 on the substrate 11.

[0055] Specifically, the material of the metal layer 13 may be at least one of aluminum-copper alloy, aluminum, germanium, and copper. Preferably, the material of the metal layer 13 is copper.

[0056] Among them, the connection pad 14 includes a protrusion 141, and the connection pad 14 is specifically connected to the multi-layer metal layer 13 through the metal lead-out terminal 131; in a specific embodiment, the connection pad 14 is specifically accommodated in the groove 121, and the upper surface of the connection pad 14 is lower than the surface of the first dielectric layer 12 away from the substrate 11, so that the connection pad 14 is completely accommodated in the groove 121. Compared with the prior art in which the connection pad 14 is set on the surface of the first dielectric layer 12 away from the substrate 11, the thickness of the product is greatly reduced, which is conducive to the development of the product in a light and thin direction; and because the connection pad 14 is completely located in the groove 121, after the needle test, the protrusion 141 formed on the connection pad 14 is located in the groove 121 or slightly extends out of the opening of the groove 121, which is not only conducive to the flattening of the product surface, but also can greatly reduce the thickness of the second dielectric layer 15.

[0057] In a specific embodiment, the depth of the groove 121 can be set according to the height of the protrusion 141 formed by the subsequent needle test; for example, if the height of the protrusion 141 is generally 1-3 microns, the depth of the groove 121 can be at least greater than the total height of the connection pad 14 and the protrusion 141, or only the protrusion 141 not exceeding 0.5 microns can extend out of the opening of the groove 121 to facilitate the subsequent flattening process.

[0058] Specifically, the connection pad 14 may be an aluminum pad, which may be rectangular in shape and have a gap between it and the side wall of the groove 121 .

[0059] Among them, the second dielectric layer 15 is stacked on the surface of the first dielectric layer 12 away from the substrate 11 and covers the protrusion 141, which can effectively ensure the flatness of the product surface; specifically, the thickness of the second dielectric layer 15 can range from 0.3 to 0.5 microns, preferably, it can be 0.5 microns; compared with the prior art, it is necessary to form a second dielectric layer 15 of 2 microns or even more than 3 microns to completely cover the protrusion 141, which greatly reduces the deposition thickness of the second dielectric layer 15.

[0060] The semiconductor device provided in this embodiment can not only perform a needle piercing test by disposing the connection pad 14 in the groove 121 of the first dielectric layer 12, but also can greatly reduce the overall thickness of the product, which is conducive to the development of the product in the direction of being lighter and thinner.

[0061] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for processing a semiconductor device, characterized in that: include: A semiconductor preform is provided; wherein the semiconductor preform comprises a substrate, a first dielectric layer disposed on a surface of the substrate, and at least one metal lead-out terminal embedded in the first dielectric layer; A groove is formed on a surface of the first dielectric layer away from the substrate, wherein the groove exposes the metal lead-out terminal; A connection pad is formed in the groove, the connection pad is connected to the metal lead-out terminal, and the upper surface of the connection pad is lower than the surface of the first dielectric layer away from the substrate; wherein a plurality of metal layers are embedded in the first dielectric layer, the plurality of metal layers are connected to each other and are led out through the metal lead-out terminal to be electrically connected to the connection pad; the metal lead-out terminal is formed on the metal layer closest to the substrate among the plurality of metal layers, and the metal lead-out terminal is offset from the plurality of metal layers; Performing a needle piercing test on the semiconductor preform; wherein, after the needle piercing test on the semiconductor preform, a convex portion is formed on the surface of the connection pad; A second dielectric layer is formed on a surface of the first dielectric layer away from the substrate, and the second dielectric layer covers the protrusion.

2. The method for processing a semiconductor device according to claim 1, wherein: After the step of forming a second dielectric layer on a surface of the first dielectric layer away from the substrate, wherein the second dielectric layer covers the protruding portion, the method further includes: The second dielectric layer is planarized, and a surface of the second dielectric layer on a side away from the first dielectric layer is processed to expose the connection pad for subsequent bonding.

3. The method for processing a semiconductor device according to claim 1, wherein: The metal lead-out terminal is formed at a position of the first dielectric layer closest to the substrate and is located below the bottom of the trench.

4. The method for processing a semiconductor device according to claim 1, wherein: The grooves and the multi-layer metal layers are spaced apart from each other along a direction parallel to the first dielectric layer.

5. The method for processing a semiconductor device according to claim 4, characterized in that: The step of forming a connection pad in the groove specifically includes: depositing a conductive layer within at least the trench; The conductive layer is processed so that an upper surface of the conductive layer is lower than a surface of the first dielectric layer away from the substrate.

6. The method for processing a semiconductor device according to claim 5, characterized in that: The step of depositing a conductive layer at least in the groove specifically comprises: Depositing a conductive layer on a surface of the first dielectric layer away from the substrate and in the groove; The step of processing the conductive layer specifically includes: removing the conductive layer located on the surface of the first dielectric layer away from the substrate, and removing a portion of the conductive layer located at the edge of the trench; and The conductive layer in the trench is thinned.

7. The method for processing a semiconductor device according to claim 1, wherein: After the step of forming a second dielectric layer on a surface of the first dielectric layer away from the substrate, the method further includes: The surface of the second dielectric layer away from the first dielectric layer is polished.

8. A semiconductor device, characterized in that: include: substrate; A first dielectric layer is disposed on a surface of the substrate, and a groove is formed on a surface of the first dielectric layer away from the substrate; At least one metal lead-out terminal is embedded in the first dielectric layer; wherein the substrate, the first dielectric layer and the at least one metal lead-out terminal form a semiconductor preform; A connection pad, comprising a protrusion, the connection pad being accommodated in the groove and connected to the at least one metal lead-out terminal; A second dielectric layer is stacked on a surface of the first dielectric layer away from the substrate and covers the protruding portion; Among them, a plurality of metal layers are also embedded in the first dielectric layer, the plurality of metal layers are interconnected and are led out through the metal lead-out terminals to be electrically connected to the connection pads; the metal lead-out terminals are formed on the metal layer closest to the substrate among the plurality of metal layers, and the metal lead-out terminals are offset from the plurality of metal layers.

9. The semiconductor device according to claim 8, characterized in that The metal lead-out terminal is located at a position of the first dielectric layer closest to the substrate and below the bottom of the trench.

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