Frequency division circuit, phase-locked loop circuit, and control method of frequency division circuit

Abstract

The present application relates to a frequency division circuit, a phase-locked loop circuit and a control method for the frequency division circuit, wherein the first input end of the pre-frequency divider is used to receive the output frequency signal of a voltage-controlled oscillator. The automatic correction counter is connected to the output end of the pre-frequency divider. The programmable counter is connected to the output end of the pre-frequency divider. The input end of the pulse throughput counter is connected to the output end of the pre-frequency divider and the output end of the programmable counter. The first input end of the gate circuit is connected to the output end of the pulse throughput counter, and the output end of the gate circuit is connected to the second input end of the pre-frequency divider. The second input end of the gate circuit is used to input an automatic frequency correction enable signal. The signals output by the pre-frequency divider are respectively sent to the automatic correction counter, the programmable counter and the pulse throughput counter. Therefore, the operating frequency of the automatic correction counter and the programmable counter can be reduced, and the power consumption of the chip can be reduced.

Description

Technical Field

[0001] The present application relates to the field of frequency source generating circuits, and in particular to a frequency dividing circuit, a phase-locked loop circuit, and a control method for the frequency dividing circuit. Background Art

[0002] In the field of frequency source generation circuits, such as phase-locked loops, VCO frequency sub-band automatic correction dividers and feedback dividers are commonly used circuits in modern phase-locked loop circuits. The feedback divider divides the high-frequency VCO (voltage-controlled oscillator) signal to near the reference frequency, and through the loop, the VCO output is the desired frequency signal. The VCO frequency sub-band automatic correction divider also needs to divide the high-frequency signal output by the VCO and then perform subsequent operations. Therefore, the VCO frequency sub-band automatic correction divider and feedback divider increase the area and power consumption of the circuit chip, and increase the manufacturing cost. Summary of the invention

[0003] Based on this, it is necessary to provide a frequency division circuit, a phase-locked loop circuit and a control method for the frequency division circuit to address the above problems.

[0004] The embodiment of the present application provides a frequency division circuit, including:

[0005] A pre-divider, wherein a first input terminal of the pre-divider is used to receive an output frequency signal of a voltage-controlled oscillator;

[0006] An automatic correction counter connected to the output end of the pre-divider;

[0007] A programmable counter connected to the output end of the prescaler;

[0008] a pulse throughput counter, wherein an input end of the pulse throughput counter is connected to an output end of the prescaler and an output end of the programmable counter; and

[0009] A gate circuit, wherein the first input end of the gate circuit is connected to the output end of the pulse throughput counter, the output end of the gate circuit is connected to the second input end of the pre-divider, and the second input end of the gate circuit is used to input an automatic frequency correction enable signal.

[0010] In one embodiment, the prescaler is a divide-by-N / (N+1) dual modulus prescaler.

[0011] In one embodiment, the gate circuit is a two-input AND gate circuit.

[0012] In one embodiment, the gate circuit is a two-input OR gate circuit.

[0013] The embodiment of the present application also provides a phase-locked loop circuit, including the frequency division circuit.

[0014] The embodiment of the present application further provides a control method of a frequency division circuit, which is applied to the frequency division circuit described in the above embodiment, comprising:

[0015] In the voltage-controlled oscillator frequency sub-band automatic correction stage, the automatic frequency correction enable signal inputted from the second input terminal of the gate circuit controls the divide-by-N / (N+1) dual-mode prescaler to operate in the divide-by-N frequency division mode through the gate circuit, and the output frequency signal of the voltage-controlled oscillator inputted from the input terminal of the divide-by-N / (N+1) dual-mode prescaler is down-converted by the N / (N+1) dual-mode prescaler and then inputted into the automatic correction counter for counting;

[0016] In the phase-locked loop locking stage, the automatic frequency correction enable signal input from the second input terminal of the gate circuit and the control signal output from the pulse throughput counter control the pre-divider through the gate circuit to realize the dual-mode pre-divider function.

[0017] In one embodiment, in the phase-locked loop locking stage, the automatic frequency correction enable signal inputted from the second input terminal of the gate circuit and the control signal outputted from the pulse throughput counter control the pre-divider through the gate circuit to realize the dual-mode pre-divider function, including:

[0018] The pulse throughput counter counts the signal output from the output end of the prescaler according to a preset count value;

[0019] The pulse throughput counter outputs a control signal to the gate circuit when counting is completed;

[0020] The gate circuit enables the pre-frequency divider to realize a dual-mode pre-frequency division function under the control of the control signal and the automatic frequency correction enable signal.

[0021] In one embodiment, in the phase-locked loop locking stage, the automatic frequency correction enable signal inputted from the second input terminal of the gate circuit and the control signal outputted from the pulse throughput counter control the pre-divider through the gate circuit to realize the dual-mode pre-divider function, further comprising:

[0022] The programmable counter counts the signal output from the output end of the prescaler according to a preset count value;

[0023] The programmable counter outputs a frequency-divided clock signal to the pulse throughput counter when counting is completed;

[0024] The divided-frequency clock signal is used as a loading signal for loading the pre-designed value of the pulse throughput counter, so that the pulse throughput counter starts counting and dividing according to the new divided-frequency preset value after receiving the loading signal.

[0025] In one embodiment, the gate circuit is a two-input AND gate circuit.

[0026] In one embodiment, the gate circuit is a two-input OR gate circuit.

[0027] The frequency division circuit provided in the embodiment of the present application includes a pre-divider, an automatic correction counter, a programmable counter, a pulse throughput counter and a gate circuit. The first input end of the pre-divider is used to receive the output frequency signal of the voltage-controlled oscillator. The automatic correction counter is connected to the output end of the pre-divider. The programmable counter is connected to the output end of the pre-divider. The input end of the pulse throughput counter is connected to the output end of the pre-divider and the output end of the programmable counter. The first input end of the gate circuit is connected to the output end of the pulse throughput counter, and the output end of the gate circuit is connected to the second input end of the pre-divider. The second input end of the gate circuit is used to input an automatic frequency correction enable signal. The signals output by the pre-divider are respectively sent to the automatic correction counter, the programmable counter and the pulse throughput counter. After the first input end of the pre-divider receives the output frequency signal of the voltage-controlled oscillator, the pre-divider pre-divides the output frequency signal of the voltage-controlled oscillator. Therefore, the operating frequency of the automatic correction counter and the programmable counter can be reduced, and the power consumption of the chip can be reduced.

[0028] The control method of the frequency division circuit is as follows: in the automatic correction stage of the frequency sub-band of the voltage-controlled oscillator, the automatic correction counter counts the signal output by the pre-divider, and outputs the count value of n bits to the digital baseband for judgment, so as to select a suitable VCO frequency sub-band. In the phase-locked loop locking stage, the programmable counter counts the signal output by the pre-divider according to the preset count value. When the counting is finished, the final frequency division clock is output. At the same time, the programmable counter can use the signal sent to the pulse throughput counter as a loading signal for loading the pre-designed value of the pulse throughput counter. The pulse throughput counter counts the signal output by the pre-divider according to the preset count value. After the counting is finished, the pulse throughput counter stops counting and outputs a control signal. The pulse throughput counter can count and divide the frequency according to the new preset frequency division value under the triggering of the loading signal. The automatic frequency correction enable signal input at the second input end of the gate circuit and the control signal output by the pulse throughput counter control the pre-divider through the gate circuit to realize the dual-mode pre-divider function. Therefore, the frequency division circuit can realize that the pre-divider works only in one frequency division mode in the VCO frequency sub-band automatic correction frequency division stage, while the programmable counter and the pulse throughput counter do not work. In the phase-locked loop locking stage, the pre-divider, the programmable counter and the pulse throughput counter in the frequency division circuit constitute the function of the phase-locked loop feedback frequency divider as a whole, thereby reducing the use of devices, saving chip space and energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A structural diagram of a pre-divider provided in an embodiment of the present application;

[0030] Figure 2 A structural diagram of a pre-divider provided in another embodiment of the present application;

[0031] Figure 3 A structural diagram of a pre-divider provided in another embodiment of the present application;

[0032] Figure 4 A structural diagram of a pre-divider provided in another embodiment of the present application.

[0033] Description of reference numerals:

[0034] Frequency division circuit 10 , pre-frequency divider 101 , automatic correction counter 102 , programmable counter 103 , pulse throughput counter 104 , gate circuit 105 . DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the frequency division circuit, phase-locked loop circuit and control method of the frequency division circuit of the present application are further described in detail below through embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0036] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings). In the description of this application, it should be understood that the orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to this application.

[0037] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0038] In the field of frequency source generation circuits, such as phase-locked loops, the feedback divider divides the high-frequency VCO (voltage-controlled oscillator) signal to near the reference frequency, and through the loop, the VCO outputs the desired frequency signal. The frequency coverage range of the VCO is divided into two by the switch capacitor. b Frequency sub-bands. In the process of automatic frequency sub-band correction, directly counting the high-frequency VCO signal will consume a lot of power. Therefore, it is necessary to first divide the high-frequency signal output by the VCO into a lower-frequency signal and then count the low-frequency signal. The counting result is sent to the digital baseband for judgment and selection of the appropriate VCO frequency sub-band. Therefore, the feedback divider and the VCO frequency sub-band automatic correction divider must divide the high-frequency signal output by the VCO and then perform subsequent operations. The feedback divider and the VCO frequency sub-band automatic correction divider increase the chip area and increase the power consumption of the chip.

[0039] Based on this, an embodiment of the present application provides a frequency division circuit 10. The frequency division circuit 10 includes a pre-divider 101, an automatic correction counter 102, a programmable counter 103, a pulse throughput counter 104 and a gate circuit 105. The first input end of the pre-divider 101 is used to receive the output frequency signal of the voltage-controlled oscillator (VCO outputs a high-frequency signal). The automatic correction counter 102 is connected to the output end of the pre-divider 101. The programmable counter 103 is connected to the output end of the pre-divider 101. The input end of the pulse throughput counter 104 is connected to the output end of the pre-divider 101 and the output end of the programmable counter. The first input end of the gate circuit 105 is connected to the output end of the pulse throughput counter 104, and the output end of the gate circuit 105 is connected to the second input end of the pre-divider. The second input end of the gate circuit 105 is used to input an automatic frequency correction enable signal.

[0040] See also Figure 2 , the pre-divider 101 may be an N / (N+1) dual-mode pre-divider 101. The pre-divider 101 may have two operating modes, namely, an N-times frequency division mode and an N+1-times frequency division mode. The specific mode may be determined by a control signal inputted at the second input terminal of the pre-divider 101. The pre-divider 101 may pre-divide a high-frequency VCO signal, so that the operating frequency of the subsequent counting and frequency division modules is reduced to save power consumption.

[0041] The automatic correction counter 102 may be a VCO frequency sub-band automatic correction counter 102 (AFC counter). The automatic correction counter 102 may have the function of automatically counting the output signal of the pre-divider 101. The programmable counter 103 (P counter) also has the function of counting and dividing the output signal of the pre-divider 101. The output end of the programmable counter 103 may also output a divided clock signal (Ndiv_out). The pulse throughput counter 104 (Swallow S counter) may count the signal output by the pre-divider 101 according to a preset count value. After counting, the pulse throughput counter 104 stops counting and may output a control signal (MOD_scnt) to the gate circuit 105. The divided clock signal output from the output end of the programmable counter 103 may control the pulse throughput counter 104 to reload the preset divided value and restart counting.

[0042] The first input end of the gate circuit 105 is connected to the output end of the pulse throughput counter 104. Therefore, the control signal output by the output end of the pulse throughput counter 104 can act on the gate circuit 105. The second input end of the gate circuit 105 is used to input the automatic frequency correction enable signal. Therefore, the automatic frequency correction enable signal can act on the gate circuit 105. Under the joint action of the control signal and the automatic frequency correction enable signal, the gate circuit 105 has different control logics and outputs different signals. The output end of the gate circuit 105 is connected to the second input end of the pre-divider 101. Therefore, the pre-divider 101 works in different modes under the control of the signal output by the gate circuit 105. For example, the pre-divider 101 can be switched between the N-times division mode and the N+1-times division mode.

[0043] The frequency division circuit 10 provided in the embodiment of the present application includes a pre-frequency divider 101, an automatic correction counter 102, a programmable counter 103, a pulse throughput counter 104 and a gate circuit 105. The first input end of the pre-frequency divider 101 is used to receive the output frequency signal of the voltage-controlled oscillator. The automatic correction counter 102 is connected to the output end of the pre-frequency divider 101. The programmable counter 103 is connected to the output end of the pre-frequency divider 101. The input end of the pulse throughput counter 104 is connected to the output end of the pre-frequency divider 101 and the output end of the programmable counter 103. The first input end of the gate circuit 105 is connected to the output end of the pulse throughput counter 104, and the output end of the gate circuit 105 is connected to the second input end of the pre-frequency divider. The second input end of the gate circuit 105 is used to input an automatic frequency correction enable signal. The signals output by the pre-frequency divider 101 are respectively sent to the automatic correction counter 102, the programmable counter 103 and the pulse throughput counter 104. After the first input terminal of the pre-divider 101 receives the output frequency signal of the voltage controlled oscillator, the pre-divider 101 pre-divides the output frequency signal of the voltage controlled oscillator, thereby reducing the operating frequency of the automatic correction counter 102 and the programmable counter 103 and reducing the power consumption of the chip.

[0044] In the voltage controlled oscillator frequency sub-band automatic correction stage, the automatic correction counter 102 counts the signal output by the pre-divider 101, and outputs an n-bit count value to the digital baseband for decision, so as to select a suitable VCO frequency sub-band.

[0045] In the phase-locked loop locking stage, the programmable counter 103 counts the signal output by the pre-divider 101 according to the preset count value. When the counting is finished, the final divided clock is output. At the same time, the programmable counter 103 can send the signal to the pulse throughput counter 104 as a loading signal for loading the pre-designed value of the pulse throughput counter 104. The pulse throughput counter 104 counts the signal output by the pre-divider 101 according to the preset count value. After the counting is finished, the pulse throughput counter 104 stops counting and outputs a control signal. The pulse throughput counter 104 can count and divide according to the new preset division value under the triggering of the loading signal. The automatic frequency correction enable signal input at the second input end of the gate circuit 105 and the control signal output by the pulse throughput counter 104 control the pre-divider 101 through the gate circuit 105 to realize the dual-mode pre-division function. Therefore, the frequency division circuit 10 can realize that the pre-divider 101 works only in one frequency division mode in the VCO frequency sub-band automatic correction frequency division stage, while the programmable counter 103 and the pulse throughput counter 104 do not work. In the phase-locked loop locking stage, the pre-divider 101, the programmable counter 103 and the pulse throughput counter 104 in the frequency division circuit 10 constitute the function of the phase-locked loop feedback divider as a whole, thereby reducing the use of devices, saving chip space, and saving energy consumption.

[0046] In one embodiment, the pre-divider 101 is a divide-by-N / (N+1) dual-mode pre-divider 101. Therefore, in the automatic correction stage of the voltage-controlled oscillator frequency sub-band, the pre-divider 101 can operate in a fixed divide-by-N mode. The pre-divider 101 divides the output frequency signal of the voltage-controlled oscillator by N to a low frequency. Therefore, the operating frequency of the automatic correction counter 102 and the programmable counter 103 can be reduced, and the power consumption of the chip can be reduced. The automatic correction counter 102 counts the output frequency signal of the voltage-controlled oscillator divided by N within a certain period of time, and outputs the count value of n bits to the digital baseband for judgment, and selects a suitable VCO frequency sub-band.

[0047] It can be understood that whether the division ratio of the dual-mode N / (N+1) divider is N or N+1 is controlled by the signal input from the gate circuit 105 to the second input terminal of the pre-divider 101, and the high and low levels of the signal input to the second input terminal of the pre-divider 101 respectively control the dual-mode division ratio to be in the N division mode or the N+1 division mode.

[0048] See also Figure 3In one embodiment, the gate circuit 105 is a two-input AND gate circuit 105. When the output frequency signal AFC_EN of the voltage-controlled oscillator is 1, the output signal MOD_pres of the gate circuit 105 is MOD_scnt. Wherein MOD_scnt is the control signal output by the pulse throughput counter 104. When the output frequency signal AFC_EN of the voltage-controlled oscillator is 0, the output signal MOD_pres of the gate circuit 105 is 0. The two-input AND gate circuit may include a logic "AND" circuit and an inverter. The input end of the inverter is the second input end of the two-input AND gate circuit. The automatic frequency correction enable signal is input to the two-input AND gate circuit through the inverter.

[0049] It can be understood that the output frequency signal AFC_EN=1 of the voltage controlled oscillator can correspond to a high level, and the output frequency signal AFC_EN=0 of the voltage controlled oscillator can correspond to a low level. When the prescaler 101 is an N / (N+1) prescaler 101, whether the division by N is controlled by a high level or a low level can be set as required.

[0050] See also Figure 3 In one embodiment, the pre-divider 101 operates in the divide-by-N mode when the output signal MOD_pres of the gate circuit 105 is 0, and the pre-divider 101 operates in the divide-by-(N+1) mode when the output signal MOD_pres of the gate circuit 105 is 1. When the automatic frequency correction enable signal AFC_EN is 1, the output signal MOD_pres of the gate circuit 105 is 0, that is, the pre-divider 101 operates in the divide-by-N mode. At this time, the control signal MOD_scnt output by the pulse throughput counter 104 is shielded. At this time, the purpose of saving power consumption can be achieved.

[0051] The automatic correction counter 102 counts the low frequency signal after the output frequency signal of the voltage controlled oscillator is divided by N. After a period of time, the counting result is sent to the digital baseband for decision to select the appropriate VCO frequency sub-band. This stage is the voltage controlled oscillator frequency sub-band automatic correction stage.

[0052] When the automatic frequency correction enable signal AFC_EN=0, the automatic frequency correction enable signal MOD_pres=the control signal MOD_scnt output by the pulse throughput counter 104. The frequency division ratio of the pre-divider 101 is controlled by the automatic frequency correction enable signal MOD_pres, that is, the control signal MOD_scnt output by the pulse throughput counter 104. When the control signal MOD_scnt output by the pulse throughput counter 104=1, the pre-divider 101 performs frequency division by (N+1). When the control signal MOD_scnt output by the pulse throughput counter 104=0, the pre-divider 101 performs frequency division by N. In combination with the programmable counter 103 and the pulse throughput counter 104, the output frequency of the divided clock signal Ndiv_out output by the output end of the programmable counter 103 is the output frequency signal of the voltage-controlled oscillator divided by (NP+S). That is, at this time, the prescaler 101, the pulse throughput counter 104, and the programmable counter 103 work together. At this time, the automatic correction counter 102 does not work to save power consumption.

[0053] Therefore, the frequency division circuit 10 is equivalent to the VCO frequency sub-band automatic correction frequency divider, which can be reused with the dual-mode pre-divider 101 to save chip area and power consumption. The frequency division circuit 10 can avoid the VCO frequency sub-band automatic correction counter 102 directly counting the output frequency signal of the voltage-controlled oscillator, and can also avoid the need for a separate divide-by-N frequency divider to divide the output frequency signal of the voltage-controlled oscillator by N before sending it to the VCO frequency sub-band automatic correction counter 102 for counting. The former works under high-frequency signals of GHz, and the power consumption increases. The latter requires a separate divide-by-N frequency divider, which increases the chip area.

[0054] See also Figure 4 In one embodiment, the gate circuit 105 is a two-input OR gate circuit 105. At this time, when the output frequency signal AFC_EN of the voltage-controlled oscillator is 1, the output signal MOD_pres of the gate circuit 105 is 1. When the output frequency signal AFC_EN of the voltage-controlled oscillator is 0, the output signal MOD_pres of the gate circuit 105 is MOD_scnt. MOD_scnt is the control signal output by the pulse throughput counter 104. The output frequency signal AFC_EN of the voltage-controlled oscillator is 1, which corresponds to a high level, and the output frequency signal AFC_EN of the voltage-controlled oscillator is 0, which corresponds to a low level. When the prescaler 101 is an N / (N+1) prescaler 101, whether the division by N is controlled by a high level or a low level can be set as needed.

[0055] In this embodiment, the pre-divider 101 operates in the divide-by-N frequency division mode when the output signal MOD_pres of the gate circuit 105 is 1, and operates in the divide-by-(N+1) frequency division mode when the output signal MOD_pres of the gate circuit 105 is 0. When the automatic frequency correction enable signal AFC_EN is 1, the control signal MOD_scnt output by the pulse throughput counter 104 is shielded. The output signal MOD_pres of the gate circuit 105 is constantly equal to 1, and the pre-divider 101 operates in the divide-by-N frequency division mode. When the automatic frequency correction enable signal AFC_EN is 0, the output signal MOD_pres of the gate circuit 105 is equal to the control signal MOD_scnt output by the pulse throughput counter 104, and the pre-divider 101 operates in the divide-by-N or divide-by-(N+1) mode according to the control signal MOD_scnt output by the pulse throughput counter 104. At this time, the pre-divider 101 can cooperate with the programmable counter 103 and the pulse throughput counter 104 to realize (NP+S) frequency division.

[0056] The embodiment of the present application further provides a phase-locked loop circuit, which includes the frequency division circuit 10 described in the above embodiment.

[0057] The embodiment of the present application also provides a control method of the frequency division circuit 10. The frequency division circuit 10 is applied to the frequency division circuit 10 described in the above embodiment. The control method includes:

[0058] S10, in the voltage controlled oscillator frequency sub-band automatic correction stage, the automatic frequency correction enable signal inputted from the second input terminal of the gate circuit 105 controls the divide-by-N / (N+1) dual-mode prescaler 101 to operate in the divide-by-N frequency division mode through the gate circuit 105, and the output frequency signal of the voltage controlled oscillator inputted from the input terminal of the divide-by-N / (N+1) dual-mode prescaler 101 is inputted to the automatic correction counter 102 for counting after being down-converted by the N / (N+1) dual-mode prescaler 101;

[0059] S20, in the phase-locked loop locking stage, the automatic frequency correction enable signal inputted from the second input terminal of the gate circuit 105 and the control signal outputted from the pulse throughput counter 104 control the prescaler 101 through the gate circuit 105 to realize the dual-mode prescaler function.

[0060] In the S10, the automatic frequency correction enable signal AFC_EN can be a high level. The signal output from the output end of the gate circuit 105 to the pre-divider 101 is always kept at a high level or a low level. The dual-mode N / (N+1) pre-divider 101 module always works in the N-division mode. The programmable counter 103 and the pulse throughput counter 104 do not work at this time. The output signal fpres of the output frequency signal of the voltage-controlled oscillator after being down-converted by the N / (N+1) dual-mode pre-divider 101 is input to the automatic correction counter 102 for counting. After the counting is completed, the automatic correction counter 102 sends the count value of n bits to the digital baseband to determine and select the appropriate VCO frequency sub-band.

[0061] In the S20, in the phase-locked loop locking stage, the automatic frequency correction enable signal AFC_EN can be at a low level. The signal MOD_pres output from the output end of the gate circuit 105 and the control signal MOD_scnt output from the pulse throughput counter 104 are the same signal. The pre-divider 101 for dividing N / (N+1) is controlled to work in the state of dividing N or dividing (N+1). The pre-divider 101 module for dividing N / (N+1) works in coordination with the programmable counter 103 and the pulse throughput counter 104. The frequency-divided clock signal Ndiv_out output from the output end of the programmable counter 103 is the frequency-divided result of the output frequency signal of the voltage-controlled oscillator divided by (NP+S).

[0062] In one embodiment, S20 includes:

[0063] The pulse throughput counter 104 counts the signal output from the output end of the prescaler 101 according to a preset count value;

[0064] The pulse throughput counter 104 outputs a control signal to the gate circuit 105 when counting is completed;

[0065] The gate circuit 105 enables the pre-divider 101 to implement a dual-mode pre-divider function under the control of the control signal and the automatic frequency correction enable signal.

[0066] In one embodiment, the S20 further includes:

[0067] The programmable counter 103 counts the signal output from the output end of the prescaler 101 according to a preset count value;

[0068] The programmable counter outputs a frequency-divided clock signal to the pulse throughput counter 104 when counting is completed;

[0069] The divided-frequency clock signal is used as a loading signal for loading the pulse throughput counter 104 with a preset value, so that the pulse throughput counter 104 starts counting and dividing according to a new divided-frequency preset value after receiving the loading signal.

[0070] Specifically, in the phase-locked loop locking stage, the programmable counter 103 counts the signal output by the pre-divider 101 according to a preset count value. When the counting is completed, the final divided clock is output. At the same time, the programmable counter 103 can send the signal to the pulse throughput counter 104 as a loading signal for loading the pre-designed value of the pulse throughput counter 104. The pulse throughput counter 104 counts the signal output by the pre-divider 101 according to the preset count value. After the counting is completed, the pulse throughput counter 104 stops counting and outputs a control signal. The pulse throughput counter 104 can count and divide according to a new preset division value under the triggering of the loading signal. The automatic frequency correction enable signal input at the second input end of the gate circuit 105 and the control signal output by the pulse throughput counter 104 control the pre-divider 101 through the gate circuit 105 to realize the dual-mode pre-division function. Therefore, the frequency division circuit 10 can realize that the pre-divider 101 works only in one frequency division mode in the VCO frequency sub-band automatic correction frequency division stage, while the programmable counter 103 and the pulse throughput counter 104 do not work. In the phase-locked loop locking stage, the pre-divider 101, the programmable counter 103 and the pulse throughput counter 104 in the frequency division circuit 10 constitute the function of the phase-locked loop feedback frequency divider as a whole, thereby reducing the use of devices, saving chip space, and saving energy consumption.

[0071] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0072] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A frequency division circuit, characterized in that: include: A pre-divider, wherein a first input terminal of the pre-divider is used to receive an output frequency signal of a voltage-controlled oscillator; The pre-divider is a divide-by-N / (N+1) dual-mode pre-divider; An automatic correction counter connected to the output end of the pre-divider; A programmable counter connected to the output end of the prescaler; A pulse throughput counter, wherein an input end of the pulse throughput counter is connected to an output end of the prescaler and an output end of the programmable counter; as well as A gate circuit, wherein a first input end of the gate circuit is connected to an output end of the pulse throughput counter, an output end of the gate circuit is connected to a second input end of the prescaler, and a second input end of the gate circuit is used to input an automatic frequency correction enable signal; The frequency division circuit is used for, in the automatic correction stage of the frequency sub-band of the voltage-controlled oscillator, the automatic frequency correction enable signal inputted at the second input terminal of the gate circuit controls the N / (N+1) dual-mode pre-divider to operate in the N-division mode through the gate circuit, and the output frequency signal of the voltage-controlled oscillator inputted from the input terminal of the N / (N+1) dual-mode pre-divider is down-converted by the N / (N+1) dual-mode pre-divider and then inputted into the automatic correction counter for counting; in the phase-locked loop locking stage, the automatic frequency correction enable signal inputted at the second input terminal of the gate circuit and the control signal outputted by the pulse throughput counter control the pre-divider through the gate circuit to realize the dual-mode pre-division function.

2. The frequency division circuit according to claim 1, characterized in that: The gate circuit is a two-input AND gate circuit.

3. The frequency division circuit according to claim 1, characterized in that: The gate circuit is a two-input OR gate circuit.

4. A phase-locked loop circuit, characterized in that: The invention comprises the frequency dividing circuit as described in any one of claims 1 to 2.

5. A control method for a frequency division circuit, applied to the frequency division circuit according to claim 1, characterized in that: include: In the voltage-controlled oscillator frequency sub-band automatic correction stage, the automatic frequency correction enable signal inputted from the second input terminal of the gate circuit controls the divide-by-N / (N+1) dual-mode prescaler to operate in the divide-by-N frequency division mode through the gate circuit, and the output frequency signal of the voltage-controlled oscillator inputted from the input terminal of the divide-by-N / (N+1) dual-mode prescaler is down-converted by the N / (N+1) dual-mode prescaler and then inputted into the automatic correction counter for counting; In the phase-locked loop locking stage, the automatic frequency correction enable signal input from the second input terminal of the gate circuit and the control signal output from the pulse throughput counter control the pre-divider through the gate circuit to realize the dual-mode pre-divider function.

6. The control method of the frequency division circuit according to claim 5, characterized in that: In the phase-locked loop locking stage, the automatic frequency correction enable signal inputted from the second input terminal of the gate circuit and the control signal outputted from the pulse throughput counter control the pre-divider through the gate circuit to realize the dual-mode pre-divider function, including: The pulse throughput counter counts the signal output from the output end of the prescaler according to a preset count value; The pulse throughput counter outputs a control signal to the gate circuit when counting is completed; The gate circuit enables the pre-frequency divider to realize a dual-mode pre-frequency division function under the control of the control signal and the automatic frequency correction enable signal.

7. The control method of the frequency division circuit according to claim 6, characterized in that: In the phase-locked loop locking stage, the automatic frequency correction enable signal inputted from the second input terminal of the gate circuit and the control signal outputted from the pulse throughput counter control the pre-divider through the gate circuit to realize the dual-mode pre-divider function, and further comprises: The programmable counter counts the signal output from the output end of the prescaler according to a preset count value; The programmable counter outputs a frequency-divided clock signal to the pulse throughput counter when counting is completed; The divided-frequency clock signal is used as a loading signal for loading the pre-designed value of the pulse throughput counter, so that the pulse throughput counter starts counting and dividing according to the new divided-frequency preset value after receiving the loading signal.

8. The control method of the frequency division circuit according to claim 5, characterized in that: The gate circuit is a two-input AND gate circuit.

9. The control method of the frequency division circuit according to claim 5, characterized in that: The gate circuit is a two-input OR gate circuit.

10. The control method of the frequency division circuit according to claim 5, characterized in that: The output frequency signal AFC_EN of the voltage controlled oscillator = 1 corresponds to a high level, and the output frequency signal AFC_EN of the voltage controlled oscillator = 0 corresponds to a low level.

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