Chip size packaging structure and manufacturing method thereof

Abstract

A chip-size packaging structure includes a base, a semiconductor element, and an electrical insulator. The base includes a first plane, a second plane opposite to the first plane, and a concave surface that is recessed from the first plane toward the second plane and defines a filling space, and the first plane, the concave surface, and the second plane are electrically connected to each other. The semiconductor element is arranged in the filling space to be surrounded by the concave surface of the base, and includes a chip and a first electrode and a second electrode that are arranged opposite to each other on the chip, and the second electrode is electrically connected to the concave surface of the base. The electrical insulator is filled in the filling space to cover the concave surface of the base and the semiconductor element and expose the first electrode. The present invention does not need to use a cantilever structure lead frame, and the second electrode of the semiconductor element is electrically connected to the first plane through the concave surface, and does not need to be hot-pressed to the cantilever structure lead frame through solder, which can avoid chip skew and avoid external electromagnetic wave interference. The present invention also provides a method for manufacturing a chip-size packaging structure.

Description

Technical Field

[0001] The present invention relates to a package structure, and more particularly to a chip scale package (CSP) structure and a manufacturing method thereof. Background Art

[0002] Semiconductor components such as diodes or transistors are usually carried by lead frames, and the electrodes in the semiconductor components are electrically connected to the lead frames by wire bonding. The semiconductor components, wires and lead frames are then covered with packaging glue to partially expose the lead frames to form a package structure. The package structure uses bonding wires to connect the electrical signals generated by the semiconductor components to the lead frames exposed outside the packaging glue, so as to transmit the electrical signals to the outside world through the lead frames exposed outside the packaging glue. In addition, the industry can also see the following Figure 1 As shown in FIG. 1 , the packaging structure is formed by omitting the bonding wire and replacing it with solder.

[0003] See also Figure 1 , a conventional packaging structure 1 includes a lead frame 11, a semiconductor element 12, two layers of solder 13, and a packaging glue 14. The lead frame 11 has a supporting cantilever 111 and a bridging cantilever 112 extending toward each other. The semiconductor element 12 is disposed on the supporting cantilever 111 of the lead frame 11, and has a chip 120, an upper electrode 121 located on the chip 120, and a lower electrode 122 located under the chip 120. The two layers of solder 13 are respectively sandwiched between the supporting cantilever 111 and the lower electrode 122 and between the bridging cantilever 112 and the upper electrode 121. The packaging glue 14 covers the semiconductor element 12, the solder 13, and the lead frame 11 to partially expose the supporting cantilever 111 and the bridging cantilever 112.

[0004] Although the existing packaging structure 1 can use the two layers of solder 13 to replace the welding wire. However, the two layers of solder 13 are respectively welded to the upper electrode 121 and the cross-cantilever 112 and the lower electrode 122 and the supporting cantilever 111 using hot pressing technology. Since the lead frame 11 is a cantilever beam structure, when the supporting cantilever 111 and the cross-cantilever 112 are subjected to the unidirectional pressure of the hot pressing mechanism, they are forced to produce elastic deflection. When the hot pressing technology is implemented, the two layers of solder 13 will also produce reflow, thereby causing the semiconductor element 12 to be crooked. In addition, the packaging glue 14 in the existing packaging structure 1 is a well-known polymer material, which is not conducive to reducing the electromagnetic interference (EMI) caused by the outside world to the semiconductor element 12. Furthermore, the overall appearance size of the existing packaging structure 1 is also difficult to meet the requirements of the portable electronic device related industry for lightness, thinness and miniaturization.

[0005] From the above description, it can be known that improving the packaging structure to solve the problems of semiconductor chip skewness and semiconductor chip interference by electromagnetic waves, and reducing the overall appearance size of the packaging structure are issues to be solved by relevant technicians in the relevant technical field. Summary of the invention

[0006] The first object of the present invention is to provide a chip size packaging structure that can solve the problems of semiconductor chip skewness and electromagnetic interference and reduce the overall appearance size.

[0007] The chip-scale packaging structure of the present invention includes a base, a semiconductor element, and an electrical insulator. The base includes a first plane, a second plane opposite to the first plane, and a concave surface that is recessed from the first plane toward the second plane and defines a filling space, and the first plane, the concave surface, and the second plane are electrically connected to each other. The semiconductor element is arranged in the filling space to be surrounded by the concave surface of the base, and includes a chip and a first electrode and a second electrode that are arranged opposite to each other on the chip, and the second electrode is electrically connected to the concave surface of the base. The electrical insulator is filled in the filling space to cover the concave surface of the base and the semiconductor element, and expose the first electrode of the semiconductor element.

[0008] The chip-size packaging structure of the present invention also includes an electrode pad unit, wherein the first plane of the base has an exposed area for external electrical connection adjacent to the concave surface; the electrical insulator also covers the first plane of the base and exposes the exposed area of ​​the first plane; the electrode pad unit includes a first electrode pad and a second electrode pad spaced apart from each other, the first electrode pad covers the electrical insulator and the first electrode of the semiconductor element, and the second electrode pad covers the electrical insulator and the exposed area.

[0009] The chip-size packaging structure of the present invention comprises a base formed by a composite plate having an insulating layer and two first metal layers, and the base further comprises a second metal layer and a third metal layer; the insulating layer has an inner annular surface that penetrates the upper surface and the lower surface of the insulating layer and defines a through hole, one of the first metal layers covers the lower surface of the insulating layer and defines the second plane of the base, and the other of the first metal layers covers the upper surface of the insulating layer and defines the first plane of the base; the second metal layer covers the inner annular surface of the insulating layer to connect the first metal layer; the third metal layer connects the second metal layer and one of the first metal layers A metal layer covers the first electrode of the semiconductor element, the electrical insulator adjacent to the first electrode, the exposed area and the electrical insulator adjacent to the exposed area, so that the second metal layer and the third metal layer connected to one of the first metal layers jointly define the concave surface of the base so that the first plane, the concave surface and the second plane of the base are electrically conductive with each other, and the third metal layer covering the first electrode of the semiconductor element and the electrical insulator adjacent to the first electrode is covered by the first electrode pad, and the third metal layer covering the exposed area and the electrical insulator adjacent to the exposed area is covered by the second electrode pad.

[0010] The chip-size packaging structure of the present invention comprises a base formed by a metal plate, and the base further comprises a third metal layer; the metal plate comprises an upper surface defining a first plane of the base, a lower surface opposite to the upper surface and defining a second plane of the base, and a concave surface which is recessed from the upper surface of the metal plate toward its lower surface and defines a concave surface of the base; the third metal layer covers the first electrode of the semiconductor element, the electrical insulator adjacent to the first electrode, the exposed area and the electrical insulator adjacent to the exposed area, so that the third metal layer covering the first electrode of the semiconductor element and the electrical insulator adjacent to the first electrode is covered by the first electrode pad, and the third metal layer covering the exposed area and the electrical insulator adjacent to the exposed area is covered by the second electrode pad.

[0011] The chip-size packaging structure of the present invention comprises a first electrode pad and a second electrode pad respectively having a metal foil, a first pad layer stacked on the corresponding metal foil, and a second pad layer stacked on the corresponding first pad layer, and the metal foil of the first electrode pad is connected to the third metal layer covering the first electrode of the semiconductor element and the electrical insulator adjacent to the first electrode, and the metal foil of the second electrode pad is connected to the third metal layer covering the exposed area and the electrical insulator adjacent to the exposed area.

[0012] In the chip-size packaging structure of the present invention, the first electrode pad and the second electrode pad located at a periphery of the filling space of the base are respectively recessed toward the second plane of the base by a step difference.

[0013] In addition, a second objective of the present invention is to provide a method for manufacturing a chip scale packaging structure.

[0014] The manufacturing method of the chip-size packaging structure of the present invention comprises the following steps: (a1) forming an inner annular surface penetrating the composite plate composed of an insulating layer and two first metal layers, so that the inner annular surface defines a through hole having two openings arranged oppositely, wherein one of the first metal layers covers the lower surface of the insulating layer and the other of the first metal layers covers the upper surface of the insulating layer; (a2) covering the inner annular surface with a second metal layer so that the second metal layer is connected to the first metal layer; (a3) ​​attaching an adhesive film to one of the first metal layers to close one of the openings of the through hole; (b) arranging a semiconductor including a chip and a first electrode and a second electrode arranged oppositely on the chip in the through hole. (a4) removing the adhesive film to open one of the openings of the through hole, exposing one of the first metal layers of the composite sheet and exposing the second metal layer and the second electrode of the semiconductor element from the electrical insulator; (d) removing a first portion of the electrical insulator to expose the first electrode of the semiconductor element; and (a5) after removing the first portion of the electrical insulator and the adhesive film, forming a third metal layer to cover the second electrode of the semiconductor element, so that the third metal layer connects the exposed one of the first metal layers and the second metal layer.

[0015] Furthermore, a third objective of the present invention is to provide another method for manufacturing a chip scale packaging structure.

[0016] Another method for manufacturing a chip-scale packaging structure of the present invention includes the following steps: (a) forming a concave surface on a metal plate that is recessed from the upper surface of the metal plate toward the lower surface thereof and defines a filling space; (b) arranging a semiconductor element including a chip and a first electrode and a second electrode arranged opposite to each other on the chip in the filling space, and the second electrode contacts the concave surface; (c) filling an electrical insulator in the filling space to cover the concave surface and the semiconductor element; and (d) removing a first portion of the electrical insulator to expose the first electrode of the semiconductor element.

[0017] The beneficial effects of the present invention are: there is no need to use a cantilever wire frame, and the second electrode of the semiconductor element is electrically connected to the first plane through the concave surface, and there is no need to heat-press the solder to the cantilever wire frame. In addition to avoiding the problem of chip skew, the semiconductor element is further surrounded by the electrically conductive concave surface, which can avoid external electromagnetic wave interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, in which:

[0019] Figure 1 is a front view schematic diagram illustrating an existing packaging structure;

[0020] Figure 2 is a front view schematic diagram illustrating a first embodiment of the chip scale package structure of the present invention;

[0021] Figure 3 This is a schematic diagram of the component manufacturing process, explaining Figure 2 Part of the process of the manufacturing method of the first embodiment shown;

[0022] Figure 4 This is a schematic diagram of the component manufacturing process, explaining the continuation Figure 3 The subsequent process of the manufacturing method of the first embodiment shown;

[0023] Figure 5 This is a schematic diagram of the component manufacturing process, explaining the continuation Figure 4 The subsequent process of the manufacturing method of the first embodiment shown;

[0024] Figure 6 This is a schematic diagram of the component manufacturing process, explaining the continuation Figure 5 The remaining process of the manufacturing method of the first embodiment shown;

[0025] Figure 7 is a front view schematic diagram illustrating a second embodiment of the chip scale package structure of the present invention;

[0026] Figure 8 This is a schematic diagram of the component manufacturing process, explaining Figure 7 A partial process of the manufacturing method of the second embodiment shown;

[0027] Fig. 9 This is a schematic diagram of the component manufacturing process, explaining the continuation Figure 8 The subsequent process of the manufacturing method of the second embodiment shown; and

[0028] Fig.10 This is a schematic diagram of the component manufacturing process, explaining the continuation Fig. 9 The remaining process of the manufacturing method of the second embodiment is shown. DETAILED DESCRIPTION

[0029] See also Figure 2 A first embodiment of the chip scale package structure of the present invention includes a base 2, a semiconductor element 3, and an electrical insulator 4.

[0030] The base 2 includes a first plane 24 , a second plane 25 opposite to the first plane 24 , and a concave surface 26 that is recessed from the first plane 24 toward the second plane 25 and defines a filling space 20 , and the first plane 24 , the concave surface 26 and the second plane 25 are electrically connected to each other.

[0031] The semiconductor element 3 is disposed in the filling space 20 to be surrounded by the concave surface 26 of the base 2 and includes a chip 30 and a first electrode 31 and a second electrode 32 disposed opposite to each other on the chip 30 , and the second electrode 32 is electrically connected to the concave surface 26 of the base 2 .

[0032] The electrical insulator 4 is filled in the filling space 20 to cover the concave surface 26 of the base 2 and the semiconductor element 3 , and expose the first electrode 31 of the semiconductor element 3 .

[0033] Preferably, the first plane 24 of the base 2 has an exposed area 241 for external electrical connection adjacent to the concave surface 26 ; the electrical insulator 4 also covers the first plane 24 of the base 2 and exposes the exposed area 241 of the first plane 24 .

[0034] Preferably, the first embodiment of the present invention further comprises an electrode pad unit 5. The electrode pad unit 5 comprises a first electrode pad 51 and a second electrode pad 52 which are spaced apart from each other. The first electrode pad 51 covers the electrical insulator 4 and the first electrode 31 of the semiconductor element 3, and the second electrode pad 52 covers the electrical insulator 4 and the exposed area 241.

[0035] In the first embodiment of the present invention, the base 2 includes a composite plate 201, the composite plate 201 has an insulating layer 200 and two first metal layers 21, and the base 2 also has a second metal layer 22 and a third metal layer 23. The insulating layer 200 has an upper surface 2001 and a lower surface 2002 that penetrate the insulating layer 200 and define an inner annular surface 2003 of the through hole 2000. One of the first metal layers 21 (that is, the lower first metal layer 21) covers the lower surface 2002 of the insulating layer 200 and defines the second plane 25 of the base 2, and the other of the first metal layers 21 (that is, the upper first metal layer 21) covers the upper surface 2001 of the insulating layer 200 and defines the first plane 24 of the base 2. The second metal layer 22 covers the inner annular surface 2003 of the insulating layer 200 to connect with the first metal layer 22. The third metal layer 23 connects the second metal layer 22 and one of the first metal layers 21 (i.e., the lower first metal layer 21), and covers the second electrode 32 of the semiconductor element 3, the electrical insulator 4 adjacent to the second electrode 32, the exposed area 241, and the electrical insulator 4 adjacent to the exposed area 241, so that the second metal layer 22 and the third metal layer 23 connected to one of the first metal layers 21 (i.e., the lower first metal layer 21) jointly define the concave surface 26 of the base 2, so that the first plane 24, the concave surface 26 and the second plane 25 of the base 2 are electrically conductive with each other, and the third metal layer 23 covering the first electrode 31 of the semiconductor element 3 and the electrical insulator 4 adjacent to the first electrode 31 is covered by the first electrode pad 51, and the third metal layer 23 covering the exposed area 241 and the electrical insulator 4 adjacent to the exposed area 241 is covered by the second electrode pad 52.

[0036] In addition, the first electrode pad 51 and the second electrode pad 52 each have a metal foil 510, 520, a first pad layer 511, 521 stacked on the corresponding metal foil 510, 520, and a second pad layer 512, 522 stacked on the corresponding first pad layer 511, 521, and the metal foil 510 of the first electrode pad 51 is connected to the third metal layer 23 covering the first electrode 31 of the semiconductor element 3 and the electrical insulator 4 adjacent to the first electrode 31, and the metal foil 520 of the second electrode pad 52 is connected to the third metal layer 23 covering the exposed area 241 and the electrical insulator 4 adjacent to the exposed area 241. In the first embodiment of the present invention, each metal foil 510, 520 and each first pad layer 511, 521 is made of copper (Cu), and each second pad layer 512, 522 is made of tin (Sn).

[0037] More preferably, the first electrode pad 51 and the second electrode pad 52 located at a periphery of the filling space 20 of the base 2 are respectively recessed with a step 513 , 523 toward the second plane 25 of the base 2 .

[0038] See also Figure 3 and Figure 4 The method for manufacturing the chip-size packaging structure of the first embodiment of the present invention includes the following steps: a step (a1), a step (a2), a step (a3), a step (b), a step (c), a step (a4), a step (d) and a step (a5).

[0039] like Figure 3 As shown, the step (a1) is to form an inner annular surface 2011 penetrating the composite plate 201 formed by the insulating layer 200 and the first metal layer 21, so that the inner annular surface 2011 defines a through hole 2010 having two oppositely arranged openings; wherein one of the first metal layers 21 (that is, the lower first metal layer 21) covers the lower surface 2002 of the insulating layer 200, and the other of the first metal layers 21 (that is, the upper first metal layer 21) covers the upper surface 2001 of the insulating layer 200. More specifically, the manufacturing method of the first embodiment of the present invention forms the through hole 2010 in the composite plate 201 by implementing a first laser ablation technology. The step (a2) is to cover the second metal layer 22 on the inner annular surface 2011, so that the second metal layer 22 is connected to the first metal layer 21. The step (a3) ​​is to attach a film 2012 to one of the first metal layers 21 (that is, the lower first metal layer 21) to close one of the openings (that is, the lower opening) of the through hole 2010. The step (b) is to dispose the semiconductor device 3 including the chip 30 and the first electrode 31 and the second electrode 32 disposed opposite to each other on the chip 30 in the through hole 2010, and the second electrode 32 is located on the film 2012.

[0040] like Figure 4As shown, the step (c) is to fill the electrical insulator 4 in the through hole 2010 to cover the second metal layer 22 and the semiconductor element 3 and close the other one of the openings of the through hole 2010 (that is, the upper opening). Preferably, the electrical insulator 4 is made by hot pressing or pouring a polymer composition. More preferably, the electrical insulator 4 is a film structure 6 having a polymer prepreg 400 and a metal foil (copper foil) 500 superimposed on the polymer prepreg 400 and arranged to face away from the composite board 201 by hot pressing, so that the polymer prepreg 400 is deformed after hot pressing and is filled into the through hole 2010 to solidify and form the electrical insulator 4, and the electrical insulator 4 also covers the other one of the first metal layers 21 (that is, the upper first metal layer 21) of the composite board 201.

[0041] See also Figure 4 The step (a4) is to remove the adhesive film 2012 to open one of the openings (i.e., the lower opening) of the through hole 2010, and expose one of the first metal layers 21 (i.e., the lower first metal layer 21) of the composite plate 201 and expose the second metal layer 22 and the second electrode 32 of the semiconductor element 3 from the electrical insulator 4. The step (d) is to remove a first portion 401 of the electrical insulator 4 to expose the first electrode 31 of the semiconductor element 3.

[0042] Specifically, the removal of the first portion 401 of the electrical insulator 4 described in step (d) is completed by implementing a second laser ablation technology, and the second laser ablation technology also removes a second portion 402 of the electrical insulator 4 located adjacent to the through hole 2010 of the other first metal layer 21 (i.e., the upper first metal layer 21) covering the composite plate 201, thereby correspondingly exposing an exposed area 211 of the other first metal layer 21 (i.e., the upper first metal layer 21) adjacent to the through hole 2010.

[0043] like Figure 4As shown, the step (a5) is to form the third metal layer 23 to cover the second electrode 32 of the semiconductor device 3 after removing the first portion 401, the second portion 402 and the adhesive film 2012 of the electrical insulator 4 so as to connect the exposed one of the first metal layers 21 (i.e., the lower first metal layer 21) and the second metal layer 22. Specifically, the third metal layer 23 is made by implementing the electroless plating technology (chemical plating) or sputtering technology (sputtering), and the third metal layer 23 also covers the first electrode 31 of the semiconductor device 3 and the electrical insulator 4 adjacent to the first electrode 31 to connect to the metal foil 500, and further covers the exposed area 211 of the other first metal layer 21 (i.e., the upper first metal layer 21) and the electrical insulator 4 adjacent to the exposed area 211 to connect to the metal foil 500.

[0044] See also Figure 5 and Figure 6 After completing the step (a5) of forming the third metal layer 23, the manufacturing method of the first embodiment of the present invention further includes a step (e), a step (f), a step (g), a step (h), a step (i), a step (j), and a step (k) in sequence.

[0045] like Figure 5 As shown, step (e) is a lithography step, and a photoresist layer 7 is formed on the metal foil 500 located between the first electrode 31 of the semiconductor element 3 and the exposed area 211 of the composite plate 201. The photoresist layer 7 exposes the third metal layer 23 and the metal foil 500 connected thereto covering the first electrode 31 of the semiconductor element 3, and exposes the third metal layer 23 and the metal foil 500 connected thereto covering the exposed area 211 of the composite plate 201. Specifically, as Figure 5 The step (e) shown is to first cover the metal foil 500 and the third metal layer 23 with a positive photoresist layer (not shown), then set a mask (not shown) above the positive photoresist layer to sequentially expose and develop the positive photoresist layer, and after development, leave the photoresist layer 7 on the metal foil 500 between the first electrode 31 of the semiconductor element 3 and the exposed area 211 of the composite board 201, thereby exposing the third metal layer 23 covering the first electrode 31 of the semiconductor element 3 and the metal foil 500 connected thereto, and exposing the third metal layer 23 covering the exposed area 211 of the composite board 201 and the metal foil 500 connected thereto.

[0046] See also Figure 5The step (f) is a first pad layer forming step, and the first pad layer 511 of the first electrode pad 51 is formed on the exposed third metal layer 23 covering the first electrode 31 of the semiconductor element 3 and the metal foil 500 connected thereto by electroplating, and the first pad layer 521 of the second electrode pad 52 is formed on the exposed third metal layer 23 covering the exposed area 211 of the composite sheet 201 and the metal foil 500 connected thereto; wherein the thickness of the first pad layers 511 and 521 is at least greater than 8 μm. The step (g) is a photoresist stripping step, and the photoresist layer 7 is removed to expose the metal foil 500 located between the first electrode 31 of the semiconductor element 3 and the exposed area 211 of the composite sheet 201. The step (h) is an etching step, and is to remove the metal foil 500 located between the first electrode 31 and the exposed area 211 of the composite plate 201 to disconnect the metal foil 500 located between the first electrode 31 and the exposed area 211 of the composite plate 201, and correspondingly expose the electrical insulator 4 located between the first electrode 31 and the exposed area 211 of the composite plate 201, thereby defining the metal foil 510 of the first electrode pad 51 and the metal foil 520 of the second electrode pad 52.

[0047] See also Figure 6 , step (i) is a step of partially thinning the first pad layer; that is, the step of partially thinning the first pad layer is to use a diamond grinding tool (not shown) to thin the first pad layers 511, 521 located at a periphery of the through hole 2010 of the composite plate 201, so as to form a corresponding pit 502 on each of the first pad layers 511, 521 located at the periphery of the through hole 2010 of the composite plate 201. The step (j) is a step of forming a second pad layer. Specifically, the step of forming the second pad layer is to form the second pad layers 512, 522 on each of the first pad layers 511, 521 by electroplating, so that each of the second pad layers 512, 522 forms a pit 503 corresponding to the pit 502 of the corresponding first pad layer 511, 521. As Figure 6 As shown, step (k) is a longitudinal cutting step. The longitudinal cutting step is to longitudinally cut the composite board 201 from the pits 503 of the second pad layers 512 and 522, so that the pits 503 of each second pad layer 512 and 522 become the corresponding step differences 513 and 523, and thus obtain the composite board 201 as shown in FIG. Figure 2 The wafer scale package structure of the first embodiment is shown.

[0048] It is worth mentioning here that the external dimensions of the package structure completed by the manufacturing method of the first embodiment of the present invention are less than or equal to 1.2 times the external dimensions of the semiconductor element 3, which is much smaller than the external dimensions of the existing package structure 1, and belongs to a chip size package structure (CSP), which can meet the requirements of portable electronic components for being thin and short. In addition, the semiconductor element 3 of the first embodiment of the present invention is arranged in the filling space 20 and is surrounded by the concave surface 26 of the base 2 (that is, the semiconductor element 3 arranged in the through hole 2010 of the composite plate 201 is surrounded by the second metal layer 22 and the third metal layer 23 connected to one of the first metal layers 21 (that is, the lower first metal layer 21)); therefore, the concave surface 26 can be used as a shielding layer to block electromagnetic interference from the outside, so as to prevent electromagnetic interference (EMI). Furthermore, the first electrode 31 and the second electrode 32 of the semiconductor element 3 are electrically connected to the outside through the first electrode pad 51 and the second electrode pad 52 located on the side of the first plane 24, respectively. It is not necessary to use the cantilever structure lead frame 11 to heat press the semiconductor element 12 between the supporting cantilever 111 and the bridging cantilever 112 through the solder 13 as in the prior art packaging structure 1, thereby avoiding the problem of chip misalignment. It is particularly worth mentioning that when the packaging structure of the first embodiment of the present invention is flipped 180 degrees to use the solder located under the step 513 of the first electrode pad 51 and the step 523 of the second electrode pad 52 to be soldered to a circuit board (not shown), the step 513 of the first electrode pad 51 and the step 523 of the second electrode pad 52 are more conducive to the solder underneath to climb upward during reflow, which can improve the electrical adhesion between the first electrode pad 51 and the second electrode pad 52 and the circuit board.

[0049] See also Figure 7 A second embodiment of the chip size package structure of the present invention is substantially the same as the first embodiment, except that the base 2 is formed of a metal plate 202, and the second embodiment lacks the second metal layer 22 of the first embodiment, and the connection relationship of the third metal layer 23 is slightly different from that of the first embodiment.

[0050] Specifically, the metal plate 202 of the second embodiment of the present invention has an upper surface 2021 that defines the first plane 24 of the base 2, a lower surface 2022 that is opposite to the upper surface 2021 of the metal plate 202 and defines the second plane 25 of the base 2, and a concave surface 2023 that is recessed from the upper surface 2021 of the metal plate 202 toward its lower surface 2022 and defines the concave surface 26 of the base 2. In addition, the third metal layer 23 of the second embodiment of the present invention only covers the first electrode 31 of the semiconductor element 3, the electrical insulator 4 adjacent to the first electrode 31, the exposed area 241 and the electrical insulator 4 adjacent to the exposed area 241, so that the third metal layer 23 covering the first electrode 31 of the semiconductor element 3 and the electrical insulator 4 adjacent to the first electrode 31 is covered by the first electrode pad 51, and the third metal layer 23 covering the exposed area 241 and the electrical insulator 4 adjacent to the exposed area 241 is covered by the second electrode pad 52.

[0051] See also Figure 8 , Fig. 9 and Fig.10 The manufacturing method of the chip scale package structure of the second embodiment of the present invention is substantially the same as that of the first embodiment, except that the manufacturing method of the second embodiment of the present invention replaces step (a1), step (a2), step (a3) ​​and step (a4) of the first embodiment with step (a), and steps (b), step (c), step (d), step (a5), step (e), step (f), step (g), step (h), step (i) and step (k) of the second embodiment are also slightly different from those of the first embodiment.

[0052] like Figure 8As shown, the step (a) of the manufacturing method of the chip scale package structure of the second embodiment of the present invention is to form a concave surface 2023 on the metal plate 202, which is recessed from the upper surface 2021 of the metal plate 202 toward the lower surface 2022 thereof and defines the filling space 20. In the manufacturing method of the second embodiment of the present invention, the step (a) of forming the concave surface 2023 on the metal plate 202 is also completed by implementing the first laser ablation technology. The step (b) is to arrange the semiconductor device 3 including the chip 30 and the first electrode 31 and the second electrode 32 arranged opposite to each other on the chip 30 in the filling space 20, and the second electrode 32 contacts the concave surface 2023. The step (c) is to fill the filling space 20 with the electrical insulator 4 to cover the concave surface 2023 and the semiconductor device 3. It should be noted here that the metal foil 500 of the film structure 6 used in the implementation of step (c) of the manufacturing method of the second embodiment of the present invention is stacked on the polymer semi-cured sheet 400 to be arranged with its back to the metal plate 202, and the polymer semi-cured sheet 400 is deformed after hot pressing and filled into the filling space 20 to be cured to form the electrical insulator 4, and the electrical insulator 4 also covers the upper surface 2021 of the metal plate 202.

[0053] See also Figure 8 In step (d) of the manufacturing method of the second embodiment of the present invention, the removal of the first portion 401 of the electrical insulator 4 is also completed by implementing the second laser ablation technology, and the second laser ablation technology also removes the second portion 402 of the electrical insulator 4, and the second portion 402 is located adjacent to the filling space 20 covering the upper surface 2021 of the metal plate 202, thereby corresponding to an exposed area 2024 adjacent to the filling space 20 exposing the upper surface 2021 of the metal plate 202.

[0054] See also Fig. 9, step (a5) of the second embodiment of the present invention is also to form the third metal layer 23 by performing electroless plating technology or sputtering technology after performing the second laser ablation technology, and the third metal layer 23 only covers the first electrode 31 of the semiconductor element 3 and the electrical insulator 4 adjacent to the first electrode 31 to connect to the metal foil 500, and the exposed area 2024 of the metal plate 202 and the electrical insulator 4 adjacent to the exposed area 2024 to connect to the metal foil 500. The lithography step of step (e) is to form the photoresist layer 7 on the metal foil 500 located between the first electrode 31 of the semiconductor element 3 and the exposed area 2024 of the metal plate 202. The photoresist layer 7 exposes the third metal layer 23 covering the first electrode 31 of the semiconductor element 3 and the metal foil 500 connected thereto, and exposes the third metal layer 23 covering the exposed area 2024 of the metal plate 202 and the metal foil 500 connected thereto. The first pad layer forming step of step (f) is also to form the first pad layer 511 of the first electrode pad 51 on the exposed third metal layer 23 covering the first electrode 31 of the semiconductor element 3 and the metal foil 500 connected thereto by electroplating, and to form the first pad layer 521 of the second electrode pad 52 on the exposed third metal layer 23 covering the exposed area 2024 of the metal plate 202 and the metal foil 500 connected thereto. The photoresist stripping step of step (g) is to remove the photoresist layer 7 to expose the metal foil 500 located between the first electrode 31 of the semiconductor element 3 and the exposed area 2024 of the metal plate 202.

[0055] See also Fig.10 The etching step of step (h) is to remove the metal foil 500 located between the first electrode 31 and the exposed area 2024 of the metal plate 202 to disconnect the metal foil 500 located between the first electrode 31 and the exposed area 2024 of the metal plate 202, and correspondingly expose the electrical insulator 4 located between the first electrode 31 and the exposed area 2024 of the metal plate 202, thereby defining the metal foil 510 of the first electrode pad 51 and the metal foil 520 of the second electrode pad 52.

[0056] The step (i) of partially thinning the first pad layer in the manufacturing method of the second embodiment of the present invention is to thin the first pad layers 511 and 521 located at the periphery of the filling space 20 of the metal plate 202, so as to form the corresponding pits 502 on each of the first pad layers 511 and 521 located at the periphery of the filling space 20 of the metal plate 202. The step (j) of forming the second pad layer is similarly to form the corresponding second pad layers 512 and 522 on each of the first pad layers 511 and 521 by electroplating, so that each of the second pad layers 512 and 522 forms its pit 503 corresponding to the pit 502 of the corresponding first pad layers 511 and 521. The longitudinal cutting step of step (k) is to longitudinally cut the metal plate 202 from the pits 503 of the second pad layers 512 and 522, so that the pits 503 of each second pad layer 512 and 522 become the corresponding step differences 513 and 523, and thus obtain Figure 7 The chip scale packaging structure is shown.

[0057] The external dimensions of the package structure completed by the manufacturing method of the second embodiment of the present invention are also less than or equal to 1.2 times the external dimensions of the semiconductor element 3, which is much smaller than the external dimensions of the existing package structure 1, and belongs to a chip size package structure (CSP), which is sufficient to meet the requirements of portable electronic components for being thin and short. In addition, the semiconductor element 3 of the second embodiment of the present invention is arranged in the filling space 20 of the metal plate 202 and surrounded by the concave surface 2023; therefore, the concave surface 2023 made of metal material can also block electromagnetic interference from the outside to prevent EMI. In addition, the first electrode 31 and the second electrode 32 of the semiconductor element 3 are respectively electrically connected to the outside through the first electrode pad 51 and the second electrode pad 52 located on the upper surface 2021 side of the metal plate 202, without using the cantilever structure lead frame 11, which can avoid the problem of chip misalignment. Furthermore, when the packaging structure of the second embodiment is flipped 180 degrees to be soldered to the circuit board (not shown), the step difference 513 of the first electrode pad 51 and the step difference 523 of the second electrode pad 52 also facilitate the solder (not shown) under the step difference 513 and 523 to climb upward during reflow, thereby improving the electrical adhesion between the first electrode pad 51 and the second electrode pad 52 and the circuit board.

[0058] In summary, the chip-size package structure and the manufacturing method thereof of the present invention have an overall appearance size of a chip-size package (CSP) that can meet the requirements of portable electronic devices for being thin, light and short, and the semiconductor element 3 is surrounded by the electrically conductive concave surface 26, which is beneficial for blocking external electromagnetic interference, and the second electrode 32 of the semiconductor element 3 is further conductively connected to the first plane 24 via the concave surface 26, and the problem of chip misalignment can be solved without using a cantilever structure lead frame, and the step difference 513 of the first electrode pad 51 and the step difference 523 of the second electrode pad 52 are more conducive to improving the electrical adhesion between it and the circuit board, so the purpose of the present invention can be achieved.

[0059] The above descriptions are merely embodiments of the present invention and should not be used to limit the scope of the present invention. All simple equivalent changes and modifications made according to the claims and description of the present invention are still within the scope of the present invention.

Claims

1. A chip size package structure, characterized in that: Include: A base, comprising a first plane, a second plane opposite to the first plane, and a concave surface that is recessed from the first plane toward the second plane and defines a filling space, wherein the first plane, the concave surface and the second plane are electrically connected to each other, and the first plane of the base has an exposed area adjacent to the concave surface for external electrical connection; A semiconductor element is disposed in the filling space to be surrounded by the concave surface of the base, and includes a chip and a first electrode and a second electrode disposed on the chip opposite to each other, and the second electrode is electrically connected to the concave surface of the base; An electrical insulator is filled in the filling space to cover the concave surface of the base and the semiconductor element and expose the first electrode of the semiconductor element, and the electrical insulator also covers the first plane of the base and exposes the exposed area of ​​the first plane; and The electrode pad unit includes a first electrode pad and a second electrode pad which are spaced apart from each other, wherein the first electrode pad covers the electrical insulator and the first electrode of the semiconductor element, and the second electrode pad covers the electrical insulator and the exposed area, wherein the first electrode pad and the second electrode pad each have a metal foil, a first solder pad layer stacked on the metal foil corresponding to each other, and a second solder pad layer stacked on the first solder pad layer corresponding to each other, and the first electrode pad and the second electrode pad located at the periphery of the filling space of the base are respectively recessed toward the second plane of the base with a difference step.

2. The wafer scale package structure according to claim 1, wherein: The base is made of a composite plate having an insulating layer and two first metal layers, and the base further comprises a second metal layer and a third metal layer; The insulating layer has an inner annular surface that penetrates the upper surface and the lower surface of the insulating layer and defines a through hole, one of the first metal layers covers the lower surface of the insulating layer and defines the second plane of the base, and the other of the first metal layers covers the upper surface of the insulating layer and defines the first plane of the base; The second metal layer covers the inner annular surface of the insulating layer to connect to the first metal layer; and The third metal layer connects the second metal layer and one of the first metal layers, and covers the first electrode of the semiconductor element, the electrical insulator adjacent to the first electrode, the exposed area, and the electrical insulator adjacent to the exposed area, so that the second metal layer and the third metal layer connected to one of the first metal layers jointly define the concave surface of the base so that the first plane, the concave surface, and the second plane of the base are electrically conductive with each other, and the third metal layer covering the first electrode of the semiconductor element and the electrical insulator adjacent to the first electrode is covered by the first electrode pad, and the third metal layer covering the exposed area and the electrical insulator adjacent to the exposed area is covered by the second electrode pad.

3. The wafer scale package structure according to claim 1, wherein: The base is made of a metal plate, and the base further includes a third metal layer; The metal plate has an upper surface defining a first plane of the base, a lower surface opposite to the upper surface and defining a second plane of the base, and a concave surface that is concave from the upper surface of the metal plate toward the lower surface thereof and defines a concave surface of the base; and The third metal layer covers the first electrode of the semiconductor element, the electrical insulator adjacent to the first electrode, the exposed area and the electrical insulator adjacent to the exposed area, so that the third metal layer covering the first electrode of the semiconductor element and the electrical insulator adjacent to the first electrode is covered by the first electrode pad, and the third metal layer covering the exposed area and the electrical insulator adjacent to the exposed area is covered by the second electrode pad.

4. The wafer scale package structure according to claim 2 or 3, characterized in that: The metal foil of the first electrode pad is connected to the third metal layer covering the first electrode of the semiconductor element and the electrical insulator adjacent to the first electrode, and the metal foil of the second electrode pad is connected to the third metal layer covering the exposed area and the electrical insulator adjacent to the exposed area.

5. A method for manufacturing a chip-scale packaging structure, characterized in that: The following steps are involved: An inner annular surface penetrating the composite sheet composed of an insulating layer and two first metal layers is formed so that the inner annular surface defines a through hole having two openings arranged opposite to each other, wherein one of the first metal layers covers the lower surface of the insulating layer and the other of the first metal layers covers the upper surface of the insulating layer; Covering the inner annular surface with a second metal layer so that the second metal layer is connected to the first metal layer; Adhere a glue film on one of the first metal layers to close one of the openings of the through hole; A semiconductor element including a chip and a first electrode and a second electrode oppositely disposed on the chip is disposed in the through hole, and the second electrode is located on the adhesive film; Filling the through hole with an electrical insulator to cover the second metal layer and the semiconductor element and to close the other of the openings of the through hole; Removing the adhesive film to open one of the openings of the through hole, exposing one of the first metal layers of the composite plate and exposing the second metal layer and the second electrode of the semiconductor element from the electrical insulator; removing a first portion of the electrical insulator to expose a first electrode of the semiconductor device; and After removing the first part of the electrical insulator and the adhesive film, a third metal layer is formed to cover the second electrode of the semiconductor element, so that the third metal layer connects the first metal layer exposed to the outside and the second metal layer.

6. A method for manufacturing a chip-scale packaging structure, characterized in that: The following steps are involved: Forming a concave surface on the metal sheet that is recessed from the upper surface of the metal sheet toward the lower surface thereof and defines a filling space; A semiconductor element including a chip and a first electrode and a second electrode disposed opposite to each other on the chip is disposed in the filling space, and the second electrode contacts the concave surface; Filling the filling space with an electrical insulator to cover the concave surface and the semiconductor element, the electrical insulator being a film structure having a polymer prepreg and a metal foil superimposed on the polymer prepreg and disposed facing away from the metal plate through heat pressing, so that the polymer prepreg is deformed after heat pressing and thus filled into the filling space to be cured to form the electrical insulator, and the electrical insulator also covers the upper surface of the metal plate; Removing a first portion of the electrical insulator to expose the first electrode of the semiconductor element, and removing a second portion of the electrical insulator, the second portion being located adjacent to the filling space and covering the upper surface of the metal plate, thereby correspondingly exposing an exposed area adjacent to the filling space on the upper surface of the metal plate; Forming a first pad layer of a first electrode pad and a first pad layer of a second electrode pad that are spaced apart from each other, wherein the first pad layer of the first electrode pad covers the electrical insulator and the first electrode of the semiconductor element and is stacked on the metal foil, and the first pad layer of the second electrode pad covers the electrical insulator and the exposed area and is stacked on the metal foil; Removing the metal foil between the first electrode and the exposed area of ​​the metal plate to disconnect the metal foil between the first electrode and the exposed area of ​​the metal plate and correspondingly expose the electrical insulator between the first electrode and the exposed area of ​​the metal plate, thereby defining the metal foil of the first electrode pad and the metal foil of the second electrode pad; The first pad layer located at the periphery of the filling space of the metal plate is subjected to a thinning process, so as to form corresponding pits on each of the first pad layers located at the periphery of the filling space of the metal plate; Forming second pad layers on each of the first pad layers so that each of the second pad layers forms a concave cavity corresponding to the concave cavity of the first pad layer; The metal plate is cut longitudinally from the concave part of the second pad layer, so that the concave part of each second pad layer becomes a step, and each step is recessed from the corresponding second pad layer toward the lower surface of the metal plate.

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