Systems and methods for unipolar charge-balanced semiconductor power devices

Abstract

A charge balance (CB) field effect transistor (FET) device may include a CB layer, the CB layer being defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a group of CB regions having a second conductivity type. The CB FET device may further include a device layer, the device layer being defined in a device epi layer having the first conductivity type arranged on the CB layer. The device layer may include a high-concentration doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type, the CB bus region extending between a certain CB region in the group of CB regions of the CB layer and the high-concentration doped region of the device layer and electrically coupling a certain CB region in the group of CB regions of the CB layer to the high-concentration doped region of the device layer.

Description

Background Art

[0001] The subject matter disclosed herein relates to semiconductor power devices, and more particularly to unipolar charge balance (CB) semiconductor power devices.

[0002] For semiconductor power devices, charge balance design provides several advantages. For example, CB FET devices exhibit higher voltage blocking and reduced resistance compared to traditional unipolar device designs. However, the switching speed of CB FET devices using suspended CB regions depends on the recombination generation rate of carriers in the semiconductor material. For some semiconductor materials (such as wide bandgap materials), the recombination generation rate may be relatively low and may result in relatively low switching speeds. In order to increase the recombination generation rate and switching speed of such CBFET devices, point defects can be introduced into the semiconductor material. However, point defects may increase the leakage current of the device. Summary of the invention

[0003] In one embodiment, a charge balance (CB) field effect transistor (FET) device includes a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer includes a plurality of CB regions having a second conductivity type. Further, the CB FET device includes a device layer defined in a device epi layer having a first conductivity type arranged on the charge balance layer. The device layer includes a high-concentration doped region having a second conductivity type. Further, the CBFET device includes a CB bus region having a second conductivity type, the CB bus region extending between a CB region in a plurality of charge balance regions of the CB layer and a high-concentration doped region of the device layer and electrically coupling a CB region in a plurality of charge balance regions of the CB layer to a high-concentration doped region of the device layer.

[0004] In another embodiment, a method for manufacturing a CB FET device includes forming a first epi layer having a first conductivity type on an underlying layer. The underlying layer may be formed of a wide bandgap material. The method further includes implanting a first plurality of CB regions having a second conductivity type into the first epi layer to produce a CB layer. Further, the method includes forming a device epi layer having a first conductivity type on the CB layer. The method may also include forming a high-concentration doped region having a second conductivity type in the device epi layer to produce a device layer. The method also includes implanting a CB bus region having a second conductivity type, the CB bus region extending between a certain CB region among the plurality of CB regions of the CB layer and the high-concentration doped region of the device layer and electrically coupling a certain CB region among the plurality of CB regions of the CB layer to the high-concentration doped region of the device layer.

[0005] In another embodiment, a CB FET device includes a CB layer, which is defined in a first epi layer having a first conductivity type and is arranged on a wide bandgap substrate layer having a first conductivity type. The CB layer includes a plurality of CB regions having a second conductivity type. The CB FET device further includes a device layer, which is defined in a device epi layer having a first conductivity type arranged on a CB balance layer. The device layer includes a high-concentration doped region having a second conductivity type arranged at the upper surface of the device epi layer. The first contact is directly arranged on the high-concentration doped region. The device layer also includes a source region having a first conductivity type, which is arranged at the upper surface of the device epi layer and is close to the high-concentration doped region. The source contact is directly arranged above at least a portion of the source region. Further, the CB FET device includes a CB bus region having a second conductivity type, which extends between a certain CB region in a plurality of charge balance regions of the CB layer and a high-concentration doped region of the device layer and electrically couples a certain CB region in a plurality of charge balance regions of the CB layer to a high-concentration doped region of the device layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] These and other features, aspects and advantages of the present invention will be better understood when the following detailed description is read with reference to the accompanying drawings, in which like numerals refer to like parts throughout, and in which:

[0007] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment, the semiconductor device including a plurality of charge balance (CB) layers, each charge balance layer having a set of CB regions, wherein a CB bus electrically couples at least a portion of the CB region to a region having the same conductivity type in a device layer of the semiconductor device;

[0008] Figure 2 is a cross-sectional view of a vertical channel junction field effect transistor (JFET) device including a CB bus according to an embodiment;

[0009] Figure 3A is a cross-sectional view of a first embodiment of a horizontal channel JFET device including a CB bus according to an embodiment;

[0010] Figure 3B is a cross-sectional view of a second embodiment of a horizontal channel JFET device including a CB bus according to an embodiment;

[0011] Figure 4 is a cross-sectional view of a vertical channel metal semiconductor field effect transistor (MESFET) device including a CB bus according to an embodiment;

[0012] Figure 5is a flow chart of a process for manufacturing a CB field effect transistor (FET) device according to an embodiment; and

[0013] Figure 6 is a flow chart of another process for fabricating a CB FET device according to an embodiment. DETAILED DESCRIPTION

[0014] One or more specific embodiments will be described below. In order to provide a concise description of these embodiments, all features of the actual implementation may not be described in the specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, a large number of decisions specifically for the implementation must be made to achieve the specific goals of the developer, such as meeting system-related and business-related constraints, which may vary from implementation to implementation. In addition, it should be understood that such development efforts may be complex and time-consuming, but this is still a routine work in design, production and manufacturing for ordinary technicians who benefit from the present disclosure.

[0015] When introducing elements of various embodiments of the present disclosure, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of these elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements in addition to the listed elements. Furthermore, any numerical examples in the following discussion are intended to be non-limiting, and thus other numerical values, ranges, and percentages are within the scope of the disclosed embodiments.

[0016] As used herein, the term "layer" refers to a material that is arranged on at least a portion of the bottom surface in a continuous or discontinuous manner. Further, the term "layer" does not necessarily mean a uniform thickness of the arranged material, and the arranged material may have a uniform or variable thickness. In addition, the term "layer (a layer)" as used herein refers to a single layer or multiple layers, unless the context clearly indicates other situations. Further, as used herein, the term "arranged on..." refers to a layer that is directly arranged in a way that contacts each other or is indirectly arranged through an intermediate layer therebetween, unless other situations are clearly indicated in addition. Accordingly, as used herein, the term "directly arranged on..." means that two layers are directly in contact with each other without an intermediate layer therebetween. As used herein, the term "adjacent" means that two layers and / or two features (e.g., implantation areas) are arranged adjacently and are in direct contact with each other.

[0017] In the present disclosure, when a layer / region is described as being "on" another layer or substrate, it is understood that the layers / regions may be in direct contact with each other or have one (or more) layers or features between the layers and between the regions. Further, the term "on..." describes the relative position of the layers / regions to each other and does not necessarily mean "on the top of...", because the relative position "above" or "below" depends on the orientation of the device relative to the viewer. In addition, the use of "top", "bottom", "above", "below", "upper" and variations of these terms is for convenience, and any specific orientation of the components is not required unless otherwise specified. With this in mind, as used herein, the terms "directly above..." and "directly below..." describe the relative positions of multiple layers / regions in direct contact with each other without an intermediate layer therebetween. Further, as used herein, the terms "lower", "middle" or "bottom" refer to features that are relatively close to the substrate layer (e.g., epitaxial layer), while the terms "top" or "upper" refer to specific features that are relatively far from the substrate layer (e.g., epitaxial layer).

[0018] The present embodiment relates to the design and manufacturing method of unipolar semiconductor charge balance (CB) devices. The disclosed design and method are beneficial for manufacturing CB field effect transistor (FET) devices such as vertical channel junction field effect transistor (JFET), horizontal channel JFET, vertical channel metal semiconductor field effect transistor (MESFET), and other devices that may be useful for medium voltage (e.g., 2 kilovolts (kV)-10kV) and high voltage (e.g., greater than or equal to 10kV or 10kV-20kV) power conversion related applications. Further, the disclosed design and method are beneficial for manufacturing wide bandgap CB FET devices such as silicon carbide (SiC) devices, gallium nitride devices, diamond devices, aluminum nitride devices, boron nitride devices, and other CB FET devices manufactured using one or more wide bandgap semiconductor materials.

[0019] As discussed below, the disclosed CB FET device includes a multilayer drift region implemented using repeated epitaxial growth and dopant implantation steps. As used herein, the term "multilayer" and references to a specific number of layers (e.g., "two layers," "three layers," "four layers") refer to the number of epitaxial (epi) layers of the CB FET device. The disclosed multilayer drift region design includes a charge balance (CB) layer having a first conductivity type (e.g., an n-type CB layer). Further, each of these CB layers includes a set of charge balance (CB) regions having a second conductivity type, which are discrete, buried, implanted regions that redefine the shape of the electric field of the active region of the CB FET device. These CB regions are described herein as "buried" because these CB regions are arranged in the lower epi layer of the CB FET device (e.g., located in a CB layer arranged between the upper / device epi layer and the substrate layer). For the disclosed CB FET device embodiments, as discussed below, these CB layer designs achieve low conduction losses and high blocking voltages while maintaining a relatively simple manufacturing process.

[0020] Further, as discussed below, the disclosed CB FET device includes a CB bus (e.g., a CB bus region) having the same conductivity type as the CB region, and the CB bus generally provides an electrical connection (e.g., a vertical connection) between one or more CB regions of one or more CB layers and a high-concentration doped region (e.g., a gate region or a portion of a blocking junction) having the same conductivity type (relative to the CB region), the high-concentration doped region being arranged in the device epi layer (e.g., relatively far from the substrate layer) of the device. In this way, when the CB FET device transitions from the off state to the on state, carriers can flow directly from the high-concentration doped region to the CB region via the CB bus. Conversely, during the transition from the on state to the off state, carriers can flow directly from the CB region to the high-concentration doped region via the CB bus. Therefore, the switching performance of the disclosed CB FET device is independent of the recombination generation rate of carriers, thereby increasing the switching speed and reducing the switching and dynamic on-resistance losses. Further, the high blocking voltage generated by the CB FET device is maintained or improved.

[0021] Figure 1 is a cross-sectional view of an embodiment of a semiconductor device 8, such as a charge balance (CB) field effect transistor (FET) device 10, having a drift region 12 including a device layer 14 disposed on a plurality of charge balance (CB) layers 16. It will be appreciated that certain well-known design elements (e.g., top metal layers, passivation layers, edge terminals, etc.) may be omitted in order to more clearly illustrate certain components of the CB FET device 10 and other devices discussed below.

[0022] As discussed below, the drift region 12 of the CB FET device 10 includes a plurality of epitaxial (epi) layers 18 having a first conductivity type (e.g., n-type epi layers 18) that form the device layer 14 and the CB layer 16 of the CB FET device 10. Additionally, in some embodiments, the epi layers 18 each have a dopant concentration that may be the same or different. Although the illustrated embodiment includes three epi layers 18 (e.g., 18A, 18B, and 18Z), the CB FET device 10 may include any suitable number of epi layers 18 (e.g., 2, 4, 5, 6, or more) to obtain a CB FET device 10 having a particular desired voltage rating. In some embodiments, the epi layer 18 is typically formed of one or more wide bandgap semiconductor materials, such as silicon carbide, gallium nitride, diamond, aluminum nitride, and / or boron nitride. The epi layer 18 may be fabricated using repeated cycles of epitaxial overgrowth. As illustrated, the first epi layer 18A is disposed over and adjacent to the substrate layer 20, the second epi layer 18B is disposed over and adjacent to the first epi layer 18A, and the third epi layer 18Z (e.g., a device epi layer) is disposed over and adjacent to the second epi layer 18B. In other embodiments, the CB FET device 10 may include additional epi layers 18 (e.g., 18C, 18D, etc.) between the first epi layer 18A and the second epi layer 18B and / or between the second epi layer 18B and the device epi layer 18Z.

[0023] To reduce the on-state resistance (Rds(on)) and the resulting on-state conduction losses, the CB FET device 10 includes two CB layers 16A and 16B implanted into epi layers 18A and 18B, respectively, each of which includes a corresponding set of CB regions 22 (e.g., 22A and 22B, respectively). Additionally, the CB FET device 10 includes a charge balancing (CB) bus 24 that is electrically coupled to at least a portion of the CB regions 22. Within the CB layer 16, the CB regions 22 are oppositely doped relative to the remainder 26 of the epi layer 18. In other words, for a CB FET device 10 having an n-type CB layer 16 (e.g., an n-type SiC epitaxial layer 18), the CB regions 22 are p-type, and for a CB FET device 10 having a p-type epi layer 18, the CB regions 22 are n-type. Further, in some embodiments, the dopant concentration in the set of CB regions 22A of the CB layer 16A may be the same as or different from the dopant concentration in the set of CB regions 22B of the CB layer 16B. In addition, the CB regions 22 and the remainder 26 of the epi layers 18A and 18B are each typically designed to be substantially depleted under reverse bias and to generally provide a similar amount (e.g., substantially equal amount) of effective charge (e.g., per cm 2 ) from the ionized dopant. 2, normalized with respect to the device active area). The demonstrated charge balanced structure allows the CB FET device 10 to achieve a high breakdown voltage and a low on-state resistance because both the p-type semiconductor portion and the n-type semiconductor portion are fully depleted under nominal blocking conditions.

[0024] As shown, the CB region 22 of the CB FET device 10 is separated by the epi layers 18A and 18B (e.g., not vertically connected through these epi layers) and does not extend through the entire thickness of these epi layers. Specifically, the thicknesses of the epi layers 18A, 18B, and 18Z are 28A, 28B, and 28Z, respectively, and the thicknesses may be the same or different in some embodiments. In some embodiments, the thicknesses 28A, 28B, and 28Z of the epi layers 18A, 18B, and 18Z may each be between 10 μm and 12 μm, respectively. Additionally, the CB regions 22A and 22B in the CB layers 16A and 16B of the shown CBFET device 10 have specific thicknesses 30A and 30B, respectively. It should be understood that in some embodiments, the corresponding thicknesses 30A and 30B of the CB regions 22A and 22B may be the same or different. As shown, the thickness 30B of the group of CB regions 22B in the second CB layer 16B is less than the thickness 28B of the epi layer 18B, and therefore, the first group of CB regions 22A and the second group of CB regions 22B are not vertically connected through the epi layer 18B (e.g., do not extend through the entire corresponding thickness 28B of the epi layer).

[0025] Additionally, with respect to size, each of the CB regions 22 may be described as having a specific width 32 and a specific spacing 34. In certain embodiments, the size (e.g., thickness 30, width 32, and / or spacing 34) of the CB regions 22 may be different in different CB layers 16. In different embodiments, the CB regions 22 may have different cross-sectional shapes (e.g., defined by an implant mask and / or implant energy / dose). For some embodiments, the shape of the CB regions 22 may be substantially constant along the Y-axis.

[0026] Further, it should be appreciated that for different embodiments, the doping of the epi layer 18, the doping of the CB regions 22, the thickness 28 of the epi layer 18, the thickness 30 of the CB regions 22, the width 32 of the CB regions 22, and the spacing 34 between the CB regions 22 may be varied to achieve desired electrical performance (e.g., a desired blocking voltage) of the CB FET device 10. For example, in some embodiments, certain device parameters (e.g., the thickness 28 and doping of the epi layer 18) may be selected to provide a blocking voltage of the CB FET device 10 between approximately 1 kilovolt (kV) and 10 kV, between 1 kV and 5 kV, or any other suitable range.

[0027] Further, in some embodiments, the disclosed CB region 22 and CB layer 17 may have one or more properties (e.g., doping, width 32, depth, spacing 34, etc.) as described for the suspended charge balance region in U.S. Pat. No. 9,735,237, filed on June 26, 2015, entitled “ACTIVE AREA DESIGNS FOR SILICON CARBIDE SUPER-JUNCTION POWERDEVICES”, the disclosure of which is incorporated herein by reference in its entirety for all purposes. For example, in some embodiments, the thickness 28A and 28B of each of the epi layers 18A and 18B is between 5 μm and 20 μm. The thickness 30A and 30B of the CB region 22 is in the range of 0.5 μm to 1.0 μm, the width 32 of the CB region 22 is between 0.1 μm and 2 μm, and the spacing 34 between the CB regions 22 is between 1 μm and 6 μm. For this embodiment, the dopant concentration of CB region 22 may be between 2×10 16 Per cubic centimeter (cm -3 ) and 1×10 18 cm -3 More specifically, in some embodiments, since CB region 22 may be implanted with a variable dopant concentration profile, CB region 22 may be described as having a density of approximately 2×10 13 (e.g., + / - 20% and / or + / - 50%) per cubic centimeter (cm -2 ) of the epi layer 18. The overall injection volume (e.g., dose) may be determined and / or adjusted based in part on the depth at which the CB region 22 is implanted and / or the implant acceleration energy used to implant the CB region 22. In such an embodiment, the epi doping of the epi layer 18 may be greater than or equal to 5×10 15 cm -3 This can result in devices with the following characteristics: a specific on-resistance (e.g., less than 7 megohms per square centimeter (mOhm / cm 2 )) and a specific breakdown voltage (e.g., greater than 3 kV, greater than 4.5 kV). In some embodiments, the doping concentration of the group of CB regions 22A divided by the corresponding thickness of the CB region 22A (e.g., 30A or 30B) can be greater than or equal to 5×10 12 cm -2 and less than or equal to approximately 1×10 14 cm -2 Accordingly, in this embodiment, the doping concentration of the group of CB regions 22A and / or the group of CB regions 22B may be between 5×10 16 cm -3 With 2x10 18cm -3 Furthermore, in some embodiments, for example, the CB FET device 10 may include fewer or more CB layers 12 (eg, one CB layer 16, three CB layers 16, four CB layers 16, etc.) to obtain a desired voltage rating.

[0028] As mentioned above, the CB FET device 10 also includes a CB bus 24 for reducing switching losses and increasing switching speed. The CB bus 24 has the same conductivity type as the CB region 22, which is opposite to the conductivity type of the remainder 26 of the epi layer 18. Therefore, for a CB FET device 10 having an n-type epi layer 18, the CB bus 24 and the CB region 22 are p-type, and for a CB FET device 10 having a p-type epi layer 18, the CB bus 24 and the CB region 22 are n-type. Further, the doping concentration of the CB bus 24 can be the same or different from the group of CB regions 22A of the CB layer 16A and / or the group of CB regions 22B of the CB layer 16B. In addition, as shown, the CB bus 24 contacts and is electrically coupled to the high concentration doped region 36 of the device layer 14, which has the same conductivity type as the CB bus 24 and the CB region 22. More specifically, the CB bus 24 is electrically coupled to a high concentration doped region 36 in the device layer 14, which may be a gate region, a portion of a blocking junction, such as a high concentration doped region, a shielding region, and / or the like. As used herein, the term "high concentration doped" refers to a region of approximately 1x10 19 cm -3 or greater doping concentration. Further, the CB bus 24 can be implanted into one or more epi layers 18. Specifically, the disclosed CB bus 24 can connect (e.g., electrically couple) a high concentration doping region 36 disposed in the device layer 14 to at least a portion of the CB region 22. Specifically, the disclosed CB bus 24 can extend vertically (e.g., along the Y-axis) from one or more high concentration doping regions 36 (e.g., from one or more features close to the top surface 38 of the device layer 14) to at least a portion of the CB region 22.

[0029] In some embodiments, the depth 40 (e.g., the vertical dimension, thickness along the Y-axis) of the CB bus 24 can reach the deepest CB region 22 (e.g., the CB region 22 closest to the substrate layer 20 and farthest from the device layer 14). Further, the depth 40 of the CB bus 24 can be such that the CB bus 24 extends to and contacts the deepest CB region 22 (e.g., is arranged adjacent to the deepest CB region), extends through a portion of the thickness 30 of the deepest CB region 22 (e.g., overlaps with it), or extends through the entire thickness 30 of the deepest CB region 22 (e.g., overlaps with it).

[0030] Specifically, in the illustrated embodiment, the CB bus 24 extends from the high-concentration doped region 36 (e.g., arranged adjacent to and in contact with the high-concentration doped region) through the device epi layer 18Z (e.g., through the thickness 28Z of the device epi layer 18Z), through the second epi layer 18B (e.g., through the thickness 28B of the second epi layer 18B), and through a portion of the thickness 28A of the first epi layer 18A (e.g., through a portion of the thickness 30A of the group of CB regions 22A in the first CB layer 16A). Therefore, the CB bus 24 can electrically couple the high-concentration doped region 36 to one or more CB regions 22 in one or more corresponding CB layers 16 (e.g., CB regions vertically separated on the Y axis). In addition, the CB bus 24 can electrically couple CB regions 22 within the same CB layer 16 (e.g., CB layers horizontally separated on the Z axis) and / or different CB layers 16 (e.g., CB layers vertically separated on the Y axis) to each other. However, it should be understood that in other embodiments, the depth 40 can be such that the CB bus 24 extends only through at least a portion of the thickness 28Z of the device epi layer 18Z and the thickness 28B of the epi layer 18B (e.g., the CB bus 24 does not contact the set of CB regions 22A in the bottom CB layer 16A), or such that the CB bus 24 extends through the entire thickness 30A of the set of CB regions 22A in the bottom CB layer 16A.

[0031] The CB bus 24 also includes a width 42. As shown, a certain subset of the CB regions 22 is confined (e.g., along the Z-axis) within the width 42 of the CB bus 24. However, it should be understood that in other embodiments, more or fewer CB regions 22 may be disposed within the CB bus 24 or partially contact the CB bus (e.g., only partially disposed within the CB bus). In addition, the CB bus 24 may be disposed at any suitable position along the Z-axis. Further, the depth 40, width 42, and dopant concentration of the CB bus 24 may be selected to maintain charge balance within the CB layer 16 (e.g., the lower epi layers 18A and 18B) having the CB regions 22 and to achieve desired electrical performance (e.g., desired blocking voltage) of the CBFET device 10.

[0032] Although the illustrated embodiment includes a single CB bus 24, in other embodiments, the CB FET device 10 may include one or more additional CB busses 24 along the Z axis and / or the X axis. That is, for example, the CB FET device 10 may include any suitable number of CB busses 24 in the form of continuous vertical pillars or continuous vertical blocks, each of which is implanted in one or more portions of the epi layer 18A-Z. It should be noted that in such embodiments, each additional CB bus 24 has the same conductivity type as the illustrated CB bus 24 and contacts the same or different high concentration doped regions 36. Therefore, in some embodiments, at least one CB bus 24 may extend through at least a portion of the thickness 28 of the epi layer 18 to contact each of the CB regions 22 and electrically couple each of the CB regions to at least one high concentration doped region 36. In addition, in different embodiments, the dimensions (e.g., width 42, depth 40) of each of the CB buses 24 may be the same or different from each other.

[0033] Furthermore, if Figures 2 to 4 (each of which provides a perpendicular Figure 1 As shown in each of the cross-sectional views of the CB bus 24, the CB bus 24 also includes a length 50. Generally, a narrower (e.g., smaller length) CB bus 24 helps the CB FET device 10 achieve higher switching speeds without significantly affecting the device blocking voltage. However, the length 50 can be selected to maintain charge balance within the CB layer 16 and achieve the desired electrical performance (e.g., desired blocking voltage) of the CB FET device 10. Figures 2 to 4 As further illustrated in each of the drawings, the CB region 22 includes a length 52. As illustrated, at least a portion of the length 50 of the CB bus 24 can be defined within or overlap (e.g., along the X-axis) the length 52 of the CB region 22. Additionally, the length 50 of the CB bus 24 and the length 52 of the CB region 22 can each be defined along any suitable portion of the X-axis.

[0034] The CB bus 24 can be made by introducing dopants (e.g., boron, aluminum, nitrogen, phosphorus) into the epi layer 18 of the CB FET device 10 using high energy ion implantation. A single CB bus 24 can include a single implant region or multiple overlapping implant regions. In some embodiments, the dopants can be implanted at an implant acceleration energy between about 500keV and about 60MeV to reach a desired depth of 40μm, such as 20μm. Additionally, in some embodiments, the CB bus 24 can be formed using high energy ion implantation and suitable high energy masking materials (e.g., silicon on insulator (SOI), polysilicon, thick silicon oxide, high Z metals such as platinum, molybdenum or gold). Specifically, after epitaxial growth, a high energy implantation mask can be set (e.g., formed, grown, deposited) on the top surface 54 of the device epi layer 18Z. Then, the high energy implantation mask can mask a first portion of the top surface 54 of the device epi layer 18Z, and can selectively expose a second portion of the top surface 54. Thus, the CB bus 24 can be implanted into the exposed second portion of the top surface 54 of the device epi layer 18Z. Further, in some embodiments, the CB bus 24 can be at least partially implanted between epi growth steps (e.g., implanted before or after the CB region 22 is formed in the epi layer 18A and before the epi growth of the next epi layer 18B) so that a low energy implant can be used to obtain a suitable depth. Additionally, in different embodiments, the CB bus 24 can be formed before or after the high concentration doping region 36.

[0035] For example, Figure 2 is an embodiment of a CB FET device 10 perpendicular to Figure 1 1 is a cross-sectional view of a CB FET device including a CB bus 24 electrically coupling a CB region 22 of a CB layer 16 to a high concentration doped region 36 of the CB FET device 10. More specifically, Figure 2 An embodiment of a vertical channel JFET device 60 is shown. The device layer 14 of the vertical channel JFET device 60 shown includes a gate region 62 having a second conductivity type (e.g., a p-gate region). A gate contact 64 (e.g., a gate electrode and / or a gate terminal) is arranged on the gate region 62. Further, the device epi layer 18Z vertically protrudes or extends (e.g., along the Y axis) to form an ascending terrace feature 66, which may include a channel region 68, and some portions of the gate region 62. Additionally, as shown, a source region 70 is arranged above the channel region 68 within the terrace feature 66. The source region 70 has a first conductivity type (e.g., an n-gate region) so that the substrate layer 20 and the source region 70 have matching conductivity types. A source contact 72 (e.g., a source electrode and / or a source terminal) is arranged directly above the source region 70.

[0036] In operation, during zero gate bias, the gate region 62 and the source region 70 can have a zero junction potential. That is, for example, the gate region 62 can deplete the channel region 68 within the terrace feature 66 so that the channel region 68 does not form (e.g., open) at this potential. More specifically, the gate region 62 can cut off the flow of electrons from the source region 70 to the drain contact 76. However, during on-state operation, an appropriate gate voltage (e.g., equal to or higher than the threshold voltage (VTH) of the vertical channel JFET device 60) helps accumulate carriers in the channel region 68, thereby forming a conductive path that allows current to flow from the drain contact 76 (e.g., drain electrode, drain terminal) to the source contact 72 (e.g., source electrode, source terminal).

[0037] Now go to Figure 3A , a cross-sectional view of a first embodiment 80A of a horizontal channel JFET device including a CB bus 24 (e.g., a CB FET device 10) is shown. The device layer 14 of the illustrated horizontal channel JFET device 80A includes a first gate region 62A (e.g., a p-gate region) having a second conductivity type, which is disposed within the device epi layer 18Z. A gate contact 64 (e.g., a gate electrode and / or a gate terminal) is disposed on a portion of the first gate region 62A. Further, a channel region 68 is disposed directly above another portion of the first gate region 62A, which is separated from a portion in contact with the gate contact 64. As shown, the channel region 68 has a first conductivity type. Further, a source region 70 is disposed directly above the channel region 68 and has a first conductivity type. Additionally, a second gate region 62B having a second conductivity type is disposed directly above the channel region 68, and the second gate region 62B is separated from the source region 70. A source contact 72 (e.g., a source electrode and / or a source terminal) is disposed directly above the source region 70 and the second gate region 62B and contacts both the source region and the second gate region. In some embodiments, the source contact 72 may additionally contact the channel region 68. Since the source contact 72 is disposed above the second gate region 62B, the source contact 72 may also be referred to as an additional gate contact 64.

[0038] Figure 3B80B (e.g., CB FET device 10) of a horizontal channel JFET device including a CB bus 24. As described above with reference to the first embodiment 80A of the horizontal channel JFET device, the second embodiment 80B of the horizontal channel JFET device includes a first gate region 62A, a second gate region 62B, a channel region 68, and a source region 70 in the device layer 14. Additionally, the second embodiment 80B of the horizontal channel JFET device includes a gate contact 64 and a source contact 72. However, the layout of these features is different between the first embodiment 80A of the horizontal channel JFET device and the second embodiment 80B of the horizontal channel JFET device. To this end, the device layer 14 of the second embodiment 80B of the horizontal channel JFET device shown includes a channel region 68 arranged in the device epi layer 18Z. Further, the first gate region 62A (e.g., p gate region) having a second conductivity type is arranged directly above the channel region 68. The gate contact 64 (e.g., gate electrode and / or gate terminal) is arranged on the first gate region 62A. Further, the device layer 14 includes a second gate region 62B arranged below the channel region 68 in the device layer 14Z, and the source region 70 is arranged on the upper portion of the channel region 68. Additionally, the source contact 72 (e.g., source electrode and / or source terminal) is arranged directly above the source region 70 and the second gate region 62B. Therefore, the source contact 72 is in direct contact with each of the second gate region 62B, the source region 70 and the channel region 68.

[0039] Although the layout of the first embodiment 80A of the horizontal channel JFET device varies with the second embodiment 80B of the horizontal channel JFET device, the operation of the two devices is substantially similar. For example, at zero gate bias, the first gate region 62A and the second gate region 62B of each device (e.g., 80A and 80B) deplete the channel region 68 through the zero bias p / n junction depletion structure, thereby cutting off the channel region 68. That is, for example, the channel region 68 can have a zero junction potential so that current does not flow through the channel region 68 without applying a gate bias. However, during on-state operation, a suitable gate voltage at each of the first gate region 62A and the second gate region 62B can promote the accumulation and lateral (e.g., along the X-axis) flow of carriers in the channel region 68. In addition, the flow of carriers in the channel region 68 forms a conductive path that allows current to flow from the drain contact 76 to the source contact 72. Further, it should be understood that since the source contact 72 is in direct contact with the second gate region 62B, the first gate region 62 and the second gate region 62 can have different biases, and in order to form an on-state operating condition, the appropriate corresponding gate voltages between the first gate region 62 and the second gate region 62 can be different or the same.

[0040] Figure 41 is a cross-sectional view of an embodiment of a vertical channel metal semiconductor field effect transistor (MESFET) device 90 (e.g., CB FET device 10) that includes a CB bus 24 that electrically couples a CB region 22 of a CB layer 16 to a portion of a blocking junction 92 (e.g., a high concentration doped region 36). As shown, the blocking junction 92 can be an interface (e.g., an intersection) between the high concentration doped region 36 and the device epi layer 18Z (e.g., between a region having a second conductivity type and a region having a first conductivity type). The blocking junction 92 is arranged at the bottom of a trench feature 94 within the device epi layer 18Z. An ohmic contact 96 (e.g., an ohmic connection point) is formed between the gate metal 98 and the high concentration doped region 36. More specifically, the sidewalls of the gate metal 98 and the sidewalls of the channel region 68 form a Schottky contact 100 (e.g., a Schottky barrier) within a terrace feature 93 arranged between the trench features 94. Furthermore, a source region 70 is arranged directly above the channel region 68. A source contact 72 is arranged directly above the source region 70.

[0041] During operation of the illustrated device 90, in the absence of an applied gate bias, the gate region 62 and the source region 70 have a zero junction potential. That is, for example, the gate region 62 and more specifically the Schottky contact 100 deplete the channel region 68 through a zero bias p / n junction depletion structure, thereby causing the channel region 68 to intercept and block or prevent the flow of electrons in the channel region 68. More specifically, the Schottky contact 100 will generally intercept the flow of electrons from the source region 70 to the drain contact 76. However, during on-state operation, an appropriate gate voltage (e.g., equal to or higher than the threshold voltage (V TH )) helps accumulate carriers in the channel region 68, thereby forming a conductive path that allows current to flow from the drain contact 76 (e.g., drain electrode, drain terminal) to the source contact 72 (e.g., source electrode, source terminal).

[0042] Further, in Figures 2 to 4In each of the embodiments of the CB FET device 10 (e.g., 60, 80A, 80B, and / or 90) shown in the drawings, the CB bus 24 electrically connects at least a portion of the CB region 22 to the high concentration doped region 36 (e.g., a portion of the gate region 62 and / or the blocking junction 92), which is electrically coupled to the terminals (e.g., the gate contact 64, the source contact 72, the body contact, etc.). To this end, the portion of the CB region 22 is electrically coupled to the device terminals via the CB bus 24. Therefore, during operation, the CB bus 24 generally reduces switching losses and increases the maximum switching speed of the CB FET device 10. Specifically, during the transition of the CBFET device 10 from the off state (e.g., blocking state) to the on state (e.g., conductive state), carriers from the gate region 62 and / or the portion of the blocking junction 92 may flow directly to the CB region 22 via the CB bus 24, and similarly, during the transition of the CB FET device 10 from the on state to the off state, carriers from the CB region 22 may flow directly to the gate region 62 and / or the portion of the blocking junction 92 via the CB bus 24. Therefore, during the transition of the CB FET device 10 from the off state to the on state, the conductive path may be formed faster, and during the transition of the CB FET device 10 from the on state to the off state, the conductive path may be cut off (e.g., closed) faster.

[0043] Figure 5 1 is a flow chart of a process 110 for manufacturing an embodiment of a CB FET device 10 (such as a vertical channel JFET device 60, a horizontal channel JFET device 80 (e.g., 80A and / or 80B), and / or a vertical channel MESFET device 90) having a CB bus 24 according to the embodiments described herein. Although the following description of the process 110 is described in a particular order (which represents a particular embodiment), it should be noted that the process 110 can be performed in any suitable order. Further, certain steps can be repeated or skipped entirely, and additional steps can be included in the process 110. The following description of the process 110 is with reference to Figures 1 to 4 The embodiment of the CB FET device 10 shown in FIG.

[0044] The illustrated process 110 begins by forming an epi layer 18 on a bottom layer (block 112). In some embodiments, the bottom layer may include a semiconductor substrate layer 18. As described above, the substrate layer 18 may be made of silicon, silicon carbide (SiC), gallium nitride, diamond, aluminum nitride, and / or boron nitride. Alternatively, the epi layer may be formed on another epi layer 18 and / or a CB layer 16 as described in more detail below.

[0045] To form the first epi layer 18A on the bottom layer, the epi layer 18A can be grown using chemical vapor deposition (CVD). However, in some embodiments, the epi layer 18A can be grown on the bottom layer using any suitable technique. The epi layer 18A can be formed of one or more wide bandgap semiconductor materials, such as silicon carbide, gallium nitride, diamond, aluminum nitride and / or boron nitride. Further, as discussed above, the epi layer 18A can have a first conductivity type (e.g., n-type) and a lower dopant concentration relative to other regions of the CB FET device 10 (e.g., CB region 22, gate region 62, source region 70 and / or the like).

[0046] After forming the epi layer 18 on the bottom layer, the illustrated process 110 proceeds to implanting (block 114) the CB layer 16A into the epi layer 18A. More specifically, a set of CB regions 22A that are oppositely doped relative to the epi layer 18A are implanted into the epi layer 18A to form the first CB layer 16A. As described above, the doping concentration of each of the set of CB regions 22A may be less than or equal to 1×10 18 cm -3 and / or greater than or equal to 2×10 16 cm -3 More specifically, in some embodiments, since each of the set of CB regions 22A may be implanted with a variable dopant concentration profile, the CB region 22 may be described as having a density of approximately 2×10 13 cm -2 (e.g., + / - 20% and / or + / - 50%) of the overall injection volume (e.g., dose). The overall injection volume can be determined and / or adjusted based in part on the depth of implantation of the group of CB regions 22A and / or the implantation acceleration energy used to implant the group of CB regions 22A. Further, the group of CB regions 22A can be implanted according to any suitable means (e.g., high energy implantation, low energy implantation). For example, in some embodiments, before implanting the group of CB regions 22A, a mask may be formed on at least a portion of the epi layer 18A. The mask may be formed of silicon oxide, silicon nitride, polysilicon, silicon, a metal layer, a resist layer, or a suitable combination thereof. In addition, any suitable means may be used to form the mask. That is, for example, the mask may be directly deposited, grown and / or coated on the portion of the epi layer 18A. Furthermore, once the mask material has been deposited on the surface of epi layer 18A, a mask can be formed by patterning the mask material (e.g., photolithographic patterning) to expose or uncover a portion of epi layer 18A. The set of CB regions 22A can then be selectively implanted through the exposed portion of epi layer 18A, and the mask can then be removed.

[0047] In some embodiments, the group of CB regions 22A can be implanted using standard low-energy implantation techniques. For example, the group of CB regions 22A can be implanted to a depth less than or equal to 1 μm. Therefore, each CB region 22A can be implanted using an implantation energy of less than 500 keV. However, in some embodiments, the group of CB regions 22A can be implanted according to a suitable high-energy ion implantation technique. Therefore, each CB region 22A can be implanted in the epi layer 18A to a depth greater than about 5 μm and / or less than about 15 μm. In addition, each implanted CB region 22A can be implanted using an implantation energy greater than 500 keV and / or less than 50 MeV. Therefore, the mask described above can be a high-energy implantation mask used in combination with high-energy ion implantation (e.g., silicon on insulator (SOI), polysilicon, thick silicon oxide, high-Z metals such as platinum, molybdenum, gold, etc.).

[0048] After implanting the CB layer 16A into the epi layer 18A, the first portion of the illustrated process 110 (e.g., blocks 112 and 114) may be repeated any suitable number of times in order to construct a CBFET device 10 having an additional CB layer 16 (e.g., 16B) (decision block 116). Figures 1 to 4 The illustrated embodiment of the CB FET device 10 includes two CB layers 16 (e.g., 16A and 16B). Thus, in such an embodiment, an additional epi layer 18B may be formed (block 112) on the implanted CB layer 16A, and the additional CB layer 16B may be implanted (block 114) into the additional epi layer 18B.

[0049] After determining that each CB layer 16 to be included in the CB FET device 10 has been formed (decision box 116), the process 110 can continue to form (box 118) a device epi layer 18Z on the top CB layer 16B (e.g., the last implanted CB layer 16B). As described above with reference to box 112, the device epi layer 18Z can be formed according to any suitable technique (e.g., CVD). The device epi layer 18Z can be formed of one or more wide bandgap semiconductor materials, such as silicon carbide, gallium nitride, diamond, aluminum nitride and / or boron nitride. Further, as discussed above, the device epi layer 18Z can have a first conductivity type and a certain low dopant concentration relative to other regions of the CB FET device 10 (e.g., CB region 22, gate region 62, source region 70, and / or the like). In some embodiments, the device epi layer 18Z may have the same dopant concentration as one or more epi layers 18 (eg, 18A and / or 18B) formed previously (eg, at block 112 ).

[0050] For the illustrated embodiment of process 110, the CB bus 24 may then be implanted (block 120) into the device epi layer 18. The CB bus 24 may be implanted using a high energy implantation technique. That is, for example, the CB bus 24 may be implanted at an implant acceleration energy between about 500 keV and about 60 MeV to reach the desired depth 40. Thus, in some embodiments, to implant the CB bus 24, a high energy implantation mask (e.g., silicon on insulator (SOI), polysilicon, thick silicon oxide, high Z metals such as platinum, molybdenum, gold, etc.) may be used, as described.

[0051] In some embodiments, the CB bus 24 may be implanted such that the CB bus is connected to and electrically coupled to one or more CB regions 22. Thus, the CB bus 24 may be implanted to extend through at least the entire thickness of the device epi layer 18Z such that the CB bus 24 electrically couples at least a portion of the CB region 22 to the high concentration doped region 36 of the device layer 14. For example, in some embodiments, the CB bus 24 may be implanted to a depth 40 such that the CB bus 24 extends through at least a portion of the thickness 30 of each CB layer 16 (e.g., 16A and 16B). It should be noted that the CB bus 24 may alternatively be implanted to a depth such that the CB bus 24 extends through at least a portion of the thickness of a subset of the CB layers 16. That is, for example, the CB bus 24 may not extend through or contact each implanted CB layer 16. Further, as described above, depending on the width 42 of the CB bus 24, the CB bus 24 may or may not contact each CB region 22 (e.g., 22A and / or 22B) within the corresponding CB layer 16 (e.g., 16A and / or 16B, respectively) contacted by the CB bus 24.

[0052] After implanting (block 120) the CB bus 24, the illustrated embodiment of process 110 proceeds to forming (block 122) the remainder of the device layer 14. As described above, in addition to the device epi layer 18Z, the device layer 14 also includes a high concentration doped region 36 (e.g., Figure 2 and the gate region 62 of FIG. 3 and / or Figure 4 The blocking knot 92 of the Figures 2 to 4 The source region 70, Figure 2 3 and / or any other suitable features of the gate region 62 and / or the CB FET device 10. In some embodiments, the high-concentration doped region 36 may have a second conductivity type (e.g., p-type) and a relatively higher dopant concentration than the device epi layer 18Z. Further, the high-concentration doped region 36 may be formed in the device layer 14 using any suitable technique. Accordingly, the high-concentration doped region 36 may be implanted into the device epi layer 18Z using a high-energy ion implantation technique and / or any suitable implantation technique.

[0053] In addition, the high concentration doping region 36 of the device layer 14 contacts the CB bus 24 and is electrically coupled to the CB bus. Therefore, in embodiments where the high concentration doping region 36 is implanted, the high concentration doping region 36 can be implanted to contact at least a portion of the CB bus 24. Further, in some embodiments, the high concentration doping region 36 can be implanted into the device epi layer 18Z before implanting (block 120) the CB bus 24. Therefore, the CB bus 24 can be implanted to contact the high concentration doping region 36 in addition to contacting at least a portion of the CB region 22. In some embodiments, in accordance with the present disclosure, other processing steps can then be performed to form other features of the CBFET device 10 (e.g., gate region 62, gate contact 64, source region, source contact 72, drain contact 76) to form a functional device.

[0054] Although process 110 is described as implanting the CB bus 24 in a single step, the CB bus 24 may alternatively be implanted in a series of steps. Figure 6 As shown in the flowchart of process 130 for manufacturing an embodiment of a CB FET device 10, two or more portions of the CB bus 24 may be implanted separately during different steps involved in making the CB FET device 10. Although the following description of process 130 is described in a specific order (which represents a specific embodiment), it should be noted that process 130 may be performed in any suitable order. Further, certain steps may be repeated or skipped entirely, and additional steps may be included in process 130.

[0055] The illustrated embodiment of process 130 begins by forming (block 132) an epi layer 18A on an underlying layer and implanting (block 134) a CB layer 16A into the epi layer 18A, as described above with reference to process 110 (e.g., blocks 112 and 122, respectively). A first portion of the CB bus 24 may then be implanted (block 136) into at least a portion of the thickness 30A of at least one of the set of CB regions 22 of the implanted CB layer 16A. In some embodiments, the first portion of the CB bus 24 may be implanted according to a high energy implantation technique. Accordingly, an implant acceleration energy between about 500 keV and about 60 MeV may be employed. Further, a high energy implantation mask (e.g., silicon on insulator (SOI), polysilicon, thick silicon oxide, high Z metals such as platinum, molybdenum, gold, etc.) may be used as described above with reference to block 120 of process 110. However, since only a portion of the CB bus 24 is implanted, in some embodiments, the implantation may be performed at a higher energy density than that of the implantation mask according to block 120 of process 110. Figure 5 The CB bus 24 implanted in the single step of the illustrated process 110 implants the CB bus 24 at a shallower depth (eg, with a lower implant acceleration energy).

[0056] To form a suitable number of CB layers 16, a portion of the process 130 (e.g., blocks 132, 134, and 136) may be repeated one or more times. Accordingly, after determining (decision block 138) that an additional CB layer 16B should be added, a second epi layer 18B may be formed (block 132) on the previously implanted CB layer 16A and the second CB layer 16B may be implanted (block 134). Further, as illustrated, a second portion of the CB bus 24 may be implanted (block 136). More specifically, in some embodiments, the second portion of the CB bus 24 may be implanted such that the CB bus 24 extends through at least one of the set of CB regions 22B of the second CB layer 16B and the thickness 28B of the second epi layer 18B. Furthermore, the second portion of the CB bus 24 may be implanted such that the CB bus contacts and / or extends through at least a portion of the previously implanted first portion of the CB bus 24. Thus, the total thickness of the CB bus 24 may be less than or equal to the sum of the thicknesses of each portion of the CB bus 24.

[0057] In some embodiments, subsequent portions of the CB bus 24 (e.g., the second portion, the third portion, and / or the like) may be implanted to a greater depth than the first portion of the CB bus 24 so as to extend through the entire thickness 28B of the second epi layer 18B and a portion of the thickness of the first portion of the CB bus 24. Thus, the implant acceleration energy used to implant the second portion of the CB bus 24 may be greater than the implant energy used to implant the first portion of the CB bus 24. Further, the thickness of the second portion of the CB bus 24 may be greater than the thickness of the first portion of the CB bus 24. However, in other embodiments, the thickness of the second portion of the CB bus 24 may be equal to or less than the thickness of the first portion of the CB bus 24.

[0058] As illustrated in process 130, after determining (decision block 138) that no additional CB layer 16 will be added during fabrication of the CB FET device 10, a device epi layer 18Z is formed (block 140). As described above with reference to process 110, the device epi layer 18Z may be formed according to any suitable technique, such as by CVD. In addition, the device epi layer 18Z may be formed of one or more wide bandgap semiconductor materials, such as silicon carbide, gallium nitride, diamond, aluminum nitride, and / or boron nitride.

[0059] After forming the device epi layer 18Z, the process 130 may proceed to implanting a final portion of the CB bus 24 (block 142). The final portion of the CB bus 24 may be implanted such that the final portion of the CB bus 24 extends through at least a portion of the thickness of the device epi layer 18Z and a portion of the thickness of the top CB layer 16B, such that the final portion of the CB bus contacts at least a portion of a previously implanted portion (e.g., the second portion) of the CB bus 24. Thus, the total thickness of the CB bus 24 may be less than or equal to the sum of the thickness of each previously implanted portion (e.g., the first portion and the second portion) of the CB bus 24 and the thickness of the final portion of the CB bus 24.

[0060] In some embodiments, the device layer 14 (e.g., the remaining portion of the device layer 14) may then be formed (block 144). As described above, forming the device layer 14 involves forming the high concentration doped region 36 such that it is electrically coupled to the CB bus 24. Thus, the high concentration doped region 36 may be implanted to contact at least a portion (e.g., a final portion) of the CB bus 24. Subsequently, other processing steps may be performed to form other features of the CB FET device 10 (e.g., gate region 62, gate contact 64, source region, source contact 72, drain contact 76) to form a functional device in accordance with the present disclosure.

[0061] It should be noted that in some embodiments, implanting (block 136) the portion of the CB bus 24 may be selectively performed during the formation of the CB layers 16. More specifically, in some embodiments, any suitable number of CB layers 16 may be formed before implanting the first portion of the CB bus 24 (e.g., blocks 132 and 134 may be repeated a suitable number of times). In these embodiments, the CB bus 24 may not extend through the entire thickness of each formed CB layer 16. That is, for example, the CB bus 24 may extend through at least a portion of the thickness of the top CB layer 16B and may not contact the bottom CB layer 16A. However, after implanting the first portion of the CB bus 24 into any suitable one or more CB layers 16, a corresponding additional portion of the CB bus 24 may be implanted after each subsequent CB layer 16 (e.g., 16B) is formed, so that a connected vertical CB bus 24 is formed or made. Alternatively, in some embodiments, a corresponding additional portion of the CB bus 24 may be implanted after a set of CB layers 16 are subsequently formed. That is, for example, the thickness of each implanted portion of the CB bus 24 may be adjusted so that additional portions of the CB bus 24 may be implanted at a lower or higher frequency.

[0062] The technical effects of the present invention include designs and methods for manufacturing CB FET devices that reduce the resistance of CB FET devices and increase their switching speed while maintaining a high blocking voltage of the CB FET devices. Specifically, the disclosed CB FET device includes a CB bus that electrically couples one or more CB regions of the CB FET device to a high-concentration doped region (such as a gate region or a portion of a blocking junction) having the same conductivity type as the one or more CB regions. The CB bus can be implanted using high-energy ion implantation. Therefore, the resulting CB FET device can have an improved switching speed and reduced switching losses while maintaining a high blocking voltage.

[0063] This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any device or system and performing any method involved. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims or if such other examples include equivalent structural elements that are not substantially different from the literal language of the claims.

Claims

1. A charge balance (CB) vertical channel junction field effect transistor (JFET) device, comprising: a first CB layer defined within a first epitaxial (epi) layer having a first conductivity type, wherein the first CB layer includes a plurality of first CB regions having a second conductivity type; a second CB layer defined within a second epi layer having the first conductivity type, wherein the second CB layer includes a plurality of second CB regions having the second conductivity type, wherein the second epi layer is disposed above the first epi layer; a device layer defined in a device epi layer disposed on the second epi layer, wherein the device layer includes a high-concentration doped region including a gate region and having the second conductivity type, wherein the device epi layer has the first conductivity type; and A CB bus region having the second conductivity type extends between at least one first CB region among the plurality of first CB regions of the first CB layer, at least one second CB region among the plurality of second CB regions of the second CB layer, and the gate region of the device layer, and electrically couples at least one first CB region among the plurality of first CB regions of the first CB layer and at least one second CB region among the plurality of second CB regions of the second CB layer to the gate region of the device layer.

2. The CB JFET device of claim 1, wherein: A thickness of each of the plurality of first CB regions is greater than or equal to a thickness of each of the plurality of second CB regions.

3. The CB JFET device of claim 1, wherein: A respective depth of each of the plurality of first CB regions is less than or equal to a thickness of the first epi layer.

4. The CB JFET device of claim 1, comprising a terminal arranged on the high concentration doping region, wherein: The CB bus region electrically couples the at least one first CB region of the plurality of first CB regions to the terminal.

5. The CB JFET device of claim 1, comprising a substrate layer, wherein: The substrate layer includes silicon carbide (SiC).

6. The CB JFET device of claim 1, wherein: The high-concentration doping region is arranged at a portion of the upper surface of the device epi layer.

7. A method of manufacturing a charge balance (CB) vertical channel junction field effect transistor (JFET) device, the method comprising: forming a first epitaxial (epi) layer having a first conductivity type on an underlying layer, wherein the underlying layer is formed of a wide bandgap material; implanting a plurality of first CB regions having a second conductivity type into the first epi layer to obtain a first CB layer; forming a second epitaxial (epi) layer having the first conductivity type on the first epi layer; implanting a plurality of second CB regions having the second conductivity type into the second epi layer to obtain a second CB layer; forming a device epi layer having the first conductivity type on the second epi layer; implanting a high-concentration doped region including a gate region and having the second conductivity type in the device epi layer to obtain a device layer; and A CB bus region having the second conductivity type is implanted, wherein the CB bus region extends between at least one first CB region among the plurality of first CB regions of the first CB layer, at least one second CB region among the plurality of second CB regions of the second CB layer, and the gate region of the device layer, and electrically couples at least one first CB region among the plurality of first CB regions of the first CB layer and at least one second CB region among the plurality of second CB regions of the second CB layer to the gate region of the device layer.

8. The method of claim 7, wherein: The implanted CB bus area includes: implanting a first portion of the CB bus region in the first epi layer before forming the device epi layer; and A second portion of the CB bus region is implanted in the device epi layer after forming the device epi layer.

9. The method of claim 7, wherein: The CB bus region is implanted after the high concentration doping region is implanted.

10. The method of claim 7, wherein: The high concentration doping region is implanted before the CB bus region.

11. The method of claim 7, wherein: Forming the device epi layer includes growing the device epi layer to a thickness between 10 micrometers (μm) and 12 μm.

12. The method of claim 7, wherein: Implanting the plurality of first CB regions comprises: forming a mask by disposing a masking material on first and second portions of a surface of the first epi layer, and then patterning the masking material to selectively expose the second portion of the surface of the first epi layer; and The plurality of first CB regions are selectively implanted into the exposed second portion of the surface of the first epi layer.

13. The method of claim 12, wherein: The masking material includes silicon on insulator (SOI), polysilicon, thick silicon oxide, platinum, molybdenum, gold, or a combination thereof.

14. The method of claim 7, wherein: Implanting the plurality of first CB regions includes implanting the plurality of first CB regions at a depth less than or equal to 1 μm.

15. A charge balance (CB) vertical channel junction field effect transistor (JFET) device comprising: a first CB layer defined in a first epitaxial (epi) layer having a first conductivity type and disposed on a wide bandgap substrate layer having the first conductivity type, wherein the first CB layer includes a plurality of first CB regions having a second conductivity type; a second CB layer defined within a second epi layer having the first conductivity type, wherein the second CB layer includes a plurality of second CB regions having the second conductivity type, wherein the second epi layer is disposed above the first epi layer; a device layer, the device layer being defined in a device epi layer arranged on the second epi layer, wherein the device epi layer has the first conductivity type, wherein the device layer comprises: a high-concentration doped region including a gate region and having the second conductivity type, the high-concentration doped region being arranged at an upper surface of the epi layer of the device, wherein the first contact is directly arranged on the high-concentration doped region; and a source region having the first conductivity type, the source region being arranged at the upper surface of the device epi layer and close to the high-concentration doped region, wherein a source contact is directly arranged on at least a portion of the source region; and A CB bus region having the second conductivity type extends between at least one first CB region among the plurality of first CB regions of the first CB layer, at least one second CB region among the plurality of second CB regions of the second CB layer, and the gate region of the device layer, and electrically couples at least one first CB region among the plurality of first CB regions of the first CB layer and at least one second CB region among the plurality of second CB regions of the second CB layer to the gate region of the device layer.

16. The device of claim 15, wherein: The device layer includes mesa features between trench features, and wherein the CB bus region is disposed under at least a portion of the trench features.

17. The device of claim 15, wherein: The first CB regions include approximately 2×10 13 Per square centimeter (cm -2 ) of the total injection volume.

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