A non-volatile memory structure and preparation method thereof

Abstract

The present invention discloses a non-volatile memory structure and a preparation method thereof, belonging to the field of integrated circuit technology. The memory structure of the present invention comprises: a substrate; at least two isolation structures, one end of each isolation structure extends into the substrate, so that the substrate exposes the side wall; a recess is formed between each isolation structure side wall and the adjacent substrate side wall, a part of the recess has an inclined straight line profile shape, and the other part of the recess has an arc curve profile shape; a tunneling oxide layer is formed on one side of the substrate and covers the substrate surface and the substrate side wall; a floating gate layer is formed on the side of the tunneling oxide layer away from the substrate, and covers the tunneling oxide layer, the recess and the isolation structure; a gate is formed between the floating gate layer and the tunneling oxide layer, and the gate gate includes a plurality of current tunneling channel control surfaces. The present invention effectively improves the control of the gate gate over the current tunneling channel and reduces leakage.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a non-volatile memory structure and a preparation method thereof. Background Art

[0002] Non-volatile memory (NVM) is all forms of solid-state memory that does not require regular refreshing of the data stored in the memory. Non-volatile memory includes all forms of read-only memory (ROM), such as programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM) and flash memory (Flash), as well as battery-powered random access memory (RAM). As device feature sizes continue to shrink and integration continues to increase, traditional non-volatile memory based on charge storage will face physical and technological limits. As the process size of non-volatile memory continues to shrink, the impact of short channel effect (SCE) intensifies, resulting in a weakened control of the gate over the current channel and increased leakage. In addition, the negative impact of the short channel effect will directly limit the size of advanced processes, making it impossible to obtain products with higher integration. Summary of the invention

[0003] The object of the present invention is to provide a non-volatile memory structure and a preparation method thereof, which solves the problem that the gate in the existing non-volatile memory has weak control capability over the current tunneling channel.

[0004] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0005] The present invention provides a non-volatile memory structure, comprising:

[0006] substrate;

[0007] at least two isolation structures, one end of each of the isolation structures extending into the substrate;

[0008] A recessed portion formed between each of the isolation structure sidewalls and the adjacent substrate sidewall, wherein a portion of the recessed portion has an inclined straight line cross-sectional shape, and another portion of the recessed portion has an arcuate curved line cross-sectional shape;

[0009] A tunneling oxide layer formed on the substrate surface and the substrate sidewall;

[0010] a floating gate layer, formed on a side of the tunnel oxide layer away from the substrate and covering the tunnel oxide layer, the recess and the isolation structure;

[0011] A gate is formed between the floating gate layer and the tunneling oxide layer, and the gate includes a plurality of current tunneling channel control surfaces.

[0012] In one embodiment of the present invention, a contour line where the recess intersects the side wall of the substrate is in the shape of the inclined straight line cross section.

[0013] In one embodiment of the present invention, a contour line where the recess intersects the side wall of the isolation structure is in the shape of the arc-shaped curve cross-section.

[0014] The present invention also provides a method for preparing a non-volatile memory, which at least comprises the following steps:

[0015] providing a substrate;

[0016] forming at least two isolation structures on the substrate, wherein one end of each isolation structure extends into the substrate;

[0017] forming a patterned photoresist layer on the isolation structure;

[0018] Using the patterned photoresist layer as a mask, dry etching is performed on the portion other than that blocked by the patterned photoresist layer, so as to form a concave portion between the side wall of the isolation structure and the adjacent side wall of the substrate, wherein a portion of the concave portion has an inclined straight line cross-sectional shape, and another portion of the concave portion has an arc-shaped curved cross-sectional shape;

[0019] forming a tunneling oxide layer on the surface of the substrate and the sidewalls of the substrate;

[0020] forming a floating gate layer on a side of the tunnel oxide layer facing away from the substrate, wherein the floating gate layer covers the tunnel oxide layer, the recess and the isolation structure;

[0021] A gate is formed between the floating gate layer and the tunneling oxide layer, and the gate includes a plurality of current tunneling channel control surfaces.

[0022] In one embodiment of the present invention, the dry etching is plasma dry etching.

[0023] In one embodiment of the present invention, the etching gas used in the dry etching is carbon tetrafluoride.

[0024] In one embodiment of the present invention, the preparation method further comprises forming a dielectric layer on a side of the floating gate layer facing away from the substrate.

[0025] In one embodiment of the present invention, the dielectric layer includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer formed in sequence.

[0026] In one embodiment of the present invention, the process of forming the isolation structure includes:

[0027] forming a pad oxide layer and a silicon nitride layer on the substrate;

[0028] Etching the silicon nitride layer, the pad oxide layer and the substrate, and stopping etching when etching reaches the substrate layer to form a first trench;

[0029] An insulating material is deposited in the first trench.

[0030] In one embodiment of the present invention, the process of forming the isolation structure further includes:

[0031] The silicon nitride layer is removed after planarizing the surface of the insulating material deposited in the first trench.

[0032] The present invention forms a gate gate structure with multiple current tunneling channel control surfaces in a non-volatile memory structure. The gate gate can effectively increase the control ability of the gate over the current tunneling channel through the multiple current tunneling channel control surfaces, thereby reducing leakage. In addition, the gate gate structure with multiple current tunneling channel control surfaces can increase the width of the effective current tunneling channel, thereby improving the saturation current of the non-volatile memory, and in practical applications, increasing the charge acquisition capability. Due to the increase in the width of the effective current tunneling channel, a certain degree of miniaturization can be performed in the horizontal direction while maintaining the original performance, so that the device can achieve a higher degree of integration.

[0033] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0035] Figure 1 is a schematic diagram of a non-volatile memory structure in one embodiment of the present invention;

[0036] Figure 2 is a flow chart of a method for preparing a non-volatile memory structure in another embodiment of the present invention;

[0037] Figure 3-Figure 6 for Figure 2 The structural schematic diagram corresponding to step S2 in FIG.

[0038] Figure 7 for Figure 2 The structural schematic diagram corresponding to step S3 in FIG.

[0039] Figure 8 for Figure 2 The structural schematic diagram corresponding to step S4;

[0040] Fig. 9 for Figure 2 The structural schematic diagram corresponding to step S5;

[0041] Fig.10 for Figure 2 The structural diagram corresponding to step S6-step S7;

[0042] Figure 11-Figure 17 FIG. 4 is a structural schematic diagram corresponding to a method for preparing a non-volatile memory structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] See also Figure 1The present invention provides a non-volatile memory structure. In one embodiment, the non-volatile memory structure may include a plurality of memory cells, each memory cell including a substrate 100, a source 200, a drain 300 and a gate 400 structure located between the source / drain 300, wherein the substrate 100 may include but is not limited to a single crystal or polycrystalline semiconductor material, and the substrate 100 may also include an intrinsic single crystal silicon substrate 100 or a doped silicon substrate 100. The substrate 100 includes a substrate 100 of a first doping type, and the first doping type may be a P type or an N type. In this embodiment, the first doping type is only taken as an example as the P type, that is, in this embodiment, the substrate 100 is only taken as an example as the P type substrate 100, for example, a P type silicon substrate 100. In some embodiments, the substrate 100 may also be a single crystal silicon substrate 100, a Ge substrate 100, a SiGe substrate 100, a silicon on insulator (Silion On Insulation, SOI) or any combination thereof. According to the actual needs of the device, a suitable semiconductor material may be selected as the substrate 100, which is not limited here. In some embodiments, the substrate 100 may also be composed of a compound semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material. On the substrate 100, a gate 400 structure is formed on the substrate 100 by chemical vapor deposition, physical vapor deposition, photolithography, and the like, and then a source / drain is formed on both sides of the gate 400 structure by ion implantation, thereby obtaining the storage unit, and connecting multiple storage units to obtain the non-volatile memory of the present invention. In one embodiment of the present invention, multiple storage units can be formed on a substrate 100 at the same time.

[0045] See also Figure 1 In one embodiment of the present invention, it can be considered that the following process steps have been completed on the substrate 100, but not limited to: well implantation is performed on the region corresponding to the memory cell on the substrate 100. In addition, the figure only shows a complete gate 400 structure and two adjacent partial gate 400 structures. However, those skilled in the art should understand that in order to make the figure clearly express the core idea of ​​the present application, the figure only shows the devices and structures of the partial memory cell region of the memory in the form of a schematic diagram, but this does not mean that the memory process involved in the present invention only includes these parts, and the known memory structure and process steps may also be included therein.

[0046] See also Figure 1The gate 400 structure in this embodiment can be a stacked gate structure, specifically including a tunneling oxide layer 410, a floating gate layer 411 and a control gate layer 417 stacked in sequence on the surface of the substrate 100, wherein the control gate layer 417 and the floating gate layer 411 can be made of polysilicon, and data can be written and erased through the tunneling effect. A gate gate can also be provided between the tunneling oxide layer 410 and the floating gate layer 411 to control the tunneling current channel from the floating gate layer 411 to the substrate 100. The more the number of gate gates increases, the stronger the control force on the tunneling current channel from the floating gate layer 411 to the substrate 100 is, and the leakage is reduced. In some embodiments, the structure of the non-volatile memory can also include a dielectric layer 419, which is formed between the floating gate layer 411 and the control gate layer 417. The dielectric layer 419 separates the control gate layer 417 from the floating gate layer 411 and cannot be directly electrically connected.

[0047] See also Figure 1 In the non-volatile memory structure of the present embodiment, the floating gate layer 411 is electrically isolated, so even after the voltage is removed, the electrons reaching the gate 400 will be captured, which is the principle of the non-volatility of the non-volatile memory. The threshold voltage of the non-volatile memory structure of the present embodiment depends on the amount of charge stored in the floating gate layer 411. The more charge, the higher the threshold voltage. When the voltage applied to the control gate layer 417 is higher than the threshold voltage, the non-volatile memory structure begins to conduct. Therefore, the information stored in the non-volatile memory structure is identified by measuring its threshold voltage and comparing it with a fixed voltage level, which is called the read operation of the non-volatile memory structure. The electrons can be placed in the floating gate layer 411 using the Fowler-Nordheim tunneling method. For Fowler-Nordheim tunneling, a strong electric field is applied between the negatively charged source 200 and the positively charged control gate layer 417, which causes the electrons from the source 200 to tunnel through the tunneling oxide layer 410 and reach the floating gate layer 411. The voltage required for tunneling depends on the thickness of the tunneling oxide layer. Electrons may be removed from the floating gate layer 411 using the Fowler-Nordheim tunneling effect by applying a strong negative voltage on the control gate layer 417 and a strong positive voltage on the source 200 and drain 300 terminals, which will cause the trapped electrons to tunnel back through the tunnel oxide layer 410. In a non-volatile memory structure, placing electrons in the floating gate layer 411 is considered a programming / writing operation and removing electrons is considered an erase operation.

[0048] See also Fig.17 In another embodiment of the present invention, the nonvolatile memory includes a plurality of memory cells, each memory cell includes: a substrate 100 , at least two isolation structures 500 , a recess 600 , a tunneling oxide layer 410 , a floating gate layer 411 and a gate 700 .

[0049] See also Fig.17 , the material of the storage unit substrate 100 may include but is not limited to single crystal or polycrystalline semiconductor materials, and the substrate 100 may also include an intrinsic single crystal silicon substrate 100 or a doped silicon substrate 100. The substrate 100 includes a substrate 100 of a first doping type, and the first doping type may be P-type or N-type. In this embodiment, the first doping type is only taken as an example of P-type, that is, in this embodiment, the substrate 100 is only taken as an example of a P-type substrate 100, for example, a P-type silicon substrate 100. In some embodiments, the substrate 100 may also be a single crystal silicon substrate 100, a Ge substrate 100, a SiGe substrate 100, a silicon on insulator (Silion On Insulation, SOI) or any combination thereof. According to the actual requirements of the device, a suitable semiconductor material may be selected as the substrate 100, which is not limited here. In some embodiments, the substrate 100 may also be composed of a compound semiconductor material, and the compound semiconductor material may be, for example, a III-V semiconductor material or a II-VI semiconductor material.

[0050] See also Fig.17 , at least two isolation structures 500, one end of each isolation structure 500 extends into the substrate 100. In some embodiments, multiple isolation structures 500 may be formed in the non-volatile memory, and the multiple isolation structures 500 divide the non-volatile memory into multiple storage units. The multiple storage units may be distributed in parallel and spaced apart, or may be arranged arbitrarily according to the semiconductor structure. In this embodiment, adjacent isolation structures 500 and the substrate 100 region therebetween constitute a high-voltage device storage unit region or a low-voltage device storage unit region.

[0051] See also Fig.17 In the present embodiment, the isolation structure 500 is, for example, a shallow trench isolation structure 500, and the isolation structure 500 is in an inverted trapezoidal shape. Since the isolation structure 500 is in an inverted trapezoidal structure and one end thereof extends into the substrate 100, an inclined sidewall is formed at the junction of the substrate 100 and the isolation structure 500. The material used for the isolation structure 500 may be, for example, silicon oxide, silicon nitride or silicon oxynitride, and the width of the isolation structure 500 may be set according to the design requirements of the semiconductor structure.

[0052] See also Fig.17 A recess 600 is formed between the two side walls of the isolation structure 500 and the adjacent side walls of the substrate 100, wherein part of the contour line of the recess 600 is in the shape of an inclined straight line cross-section, and another part of the contour line of the recess 600 is in the shape of an arcuate curve cross-section. Specifically, the part where the contour line of the recess 600 intersects with the side wall of the substrate 100 is in the shape of an inclined straight line cross-section, and the part where the contour line of the recess 600 intersects with the side wall of the isolation structure 500 is in the shape of an arcuate curve cross-section.

[0053] See also Fig.17 A tunneling oxide layer 410 is formed on one side of the substrate 100, and the tunneling oxide layer 410 covers the surface of the substrate 100 and the formed sidewalls of the substrate 100. The material of the tunneling oxide layer 410 may be, for example, silicon oxide. In this embodiment, the tunneling oxide layer 410 made of silicon oxide may be formed by, for example, furnace oxidation, rapid thermal annealing oxidation, in-situ steam oxidation or other thermal oxidation methods.

[0054] See also Fig.17 A floating gate layer 411 is formed on the side of the tunnel oxide layer 410 facing away from the substrate 100. The floating gate layer 411 covers the tunnel oxide layer 410, the recess 600 and the isolation structure 500. The floating gate layer 411 can be made of doped polysilicon. The polysilicon can also be deposited in an undoped form and then implanted to form doped polysilicon. In other embodiments, other suitable conductive materials can also be used instead of doped polysilicon.

[0055] See also Fig.17 , a gate gate 700 is formed between the floating gate layer 411 and the tunneling oxide layer 410, and the gate gate 700 includes a plurality of current tunneling channel control surfaces, and in this embodiment, for example, includes three current tunneling channel control surfaces, and the three current tunneling channel control surfaces include the upper surface of the substrate 100 and the surface formed by the inclined straight side walls on both sides of the substrate 100. The gate gate 700 can control the charge entering the floating gate from the tunneling oxide layer 410. As the number of gate gates 700 increases, the control force on the current tunneling channel from the floating gate layer 411 to the substrate 100 becomes stronger. In the present invention, the recess 600 formed between the side wall of the isolation structure 500 and the side wall of the substrate 100 on both sides effectively increases the number of gate gates 700, so that the control ability of the gate gate 700 on the current tunneling channel is further enhanced. In addition, the three-sided gate gate 700 structure can increase the width of the effective current tunneling channel, thereby improving the saturation current of the non-volatile memory, and in practical applications, the charge acquisition ability is increased. Due to the increase in the width of the effective current tunneling channel, it is possible to perform a certain degree of miniaturization in the horizontal direction while maintaining the original performance, so that the device can achieve a higher degree of integration.

[0056] See also Fig.17Each independent floating gate layer 411 is electrically isolated from the substrate 100 by means of a tunneling oxide layer 410. This electrical isolation allows the floating gate layer 411 to be used as a charge storage unit. The tunneling oxide layer 410 allows charges to enter the floating gate layer 411 under certain conditions. The charge level in the floating gate layer 411 may correspond to a logic level, so that data can be stored in the storage unit. A gate 700 is provided between the tunneling oxide layer 410 and the floating gate layer 411 to control the current tunneling channel from the tunneling oxide layer 410 to the floating gate. The more the number of gates 700 increases, the stronger the control over the current tunneling channel from the floating gate layer 411 to the substrate 100. The recess 600 formed between the sidewall of the isolation structure 500 and the sidewall of the substrate 100 of the present invention effectively increases the number of gates 700, so that the control capability of the gates 700 over the current tunneling channel is further enhanced. For example, a gate 700 structure having three current tunneling channel control surfaces can increase the width of the effective current tunneling channel, thereby increasing the saturation current of the non-volatile memory and increasing the charge acquisition capability in practical applications. Due to the increase in the width of the effective current tunneling channel, a certain degree of miniaturization can be performed in the horizontal direction while maintaining the original performance, so that the device can achieve a higher degree of integration.

[0057] See also Fig.17 In another embodiment of the present invention, the structure of the non-volatile memory may further include a control gate layer 417. The control gate layer 417 is formed on a side of the floating gate layer 411 facing away from the substrate 100. The control gate layer 417 may be a conductive gate 400 formed of doped polysilicon. By applying a strong negative voltage to the control gate layer 417 and applying a strong positive voltage to the source 200 and drain 300 terminals, electrons may be removed from the floating gate layer 411 using the Fowler-Nordheim tunneling effect, which will cause the electrons captured in the floating gate layer 411 to return to the tunnel through the tunneling oxide layer 410. This process of removing electrons is considered to be an operation of erasing the non-volatile memory.

[0058] See also Figure 1 and Fig.17In another embodiment of the present invention, the structure of the non-volatile memory may further include a dielectric layer 419, which is formed between the floating gate layer 411 and the control gate layer 417. The dielectric layer 419 separates the control gate layer 417 from the floating gate layer 411 and prevents direct electrical connection. The dielectric layer 419 may include a silicon oxide layer and a silicon nitride layer formed sequentially on the surface of the floating gate layer 411, wherein the silicon oxide layer may be, for example, silicon oxynitride or silicon dioxide. Specifically, the silicon oxide layer covers the exposed surface of the floating gate layer 411 and the isolation structure 500, and the silicon nitride layer is formed on the surface of the silicon oxide layer in a stacked manner. In some embodiments, the dielectric layer 419 may further include a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414 formed sequentially on the surface of the floating gate layer 411. In this embodiment, the silicon oxide layer and the silicon nitride layer 413 may be formed using a chemical vapor deposition process. In this embodiment, the thickness of each layer of the dielectric layer can be set using existing processes, and specifically may include a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414 having conventional thicknesses sequentially formed on the surface of the floating gate layer 411.

[0059] See also Figure 2 The present invention provides a method for preparing a non-volatile memory, which at least comprises the following steps:

[0060] S1. Providing a substrate 100;

[0061] S2. forming at least two isolation structures 500 on the substrate 100, wherein one end of each isolation structure 500 extends into the substrate 100 and exposes the sidewall of the substrate 100;

[0062] S3. Forming a patterned photoresist layer on the isolation structure 500;

[0063] S4. Using the patterned photoresist layer as a mask, dry etching is performed on the portion other than that blocked by the patterned photoresist layer, so as to form a concave portion 600 between the sidewall of the isolation structure 500 and the sidewall of the substrate 100, wherein a portion of the contour line of the concave portion 600 is in an inclined straight line cross-sectional shape, and a portion of the contour line of the concave portion 600 is in an arc-shaped curved cross-sectional shape;

[0064] S5. Forming a tunneling oxide layer 410 on the surface of the substrate 100 and the sidewalls of the substrate 100;

[0065] S6. forming a floating gate layer 411 on a side of the tunneling oxide layer 410 away from the substrate 100, wherein the floating gate layer 411 covers the tunneling oxide layer 410, the recess 600 and the isolation structure 500;

[0066] S7. Form a gate 700 between the floating gate layer 411 and the tunneling oxide layer 410 , wherein the gate 700 includes a plurality of current tunneling channel control surfaces.

[0067] The following combination Figures 2 to 17 , the preparation method of the non-volatile memory of the present invention is described in detail.

[0068] See also Figure 2 In this embodiment, taking the preparation of a memory cell as an example, specifically, in step S1, a substrate 100 is first provided. The material of the substrate 100 may include but is not limited to single crystal or polycrystalline semiconductor materials. The substrate 100 may also include an intrinsic single crystal silicon substrate 100 or a doped silicon substrate 100. The substrate 100 includes a substrate 100 of a first doping type. The first doping type may be P-type or N-type. In this embodiment, only the first doping type is P-type as an example, that is, in this embodiment, the substrate 100 is only an example of a P-type substrate 100, for example, a P-type silicon substrate 100. In some embodiments, the substrate 100 may also be a single crystal silicon substrate 100, a Ge substrate 100, a SiGe substrate 100, a silicon on insulator (Silion On Insulation, SOI) or any combination thereof. According to the actual requirements of the device, a suitable semiconductor material may be selected as the substrate 100, which is not limited here. In some embodiments, the substrate 100 may also be composed of a compound semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material.

[0069] See also Figure 3 In step S2, a pad oxide layer 401 is formed on one side of the substrate 100. The material of the pad oxide layer 401 may be, for example, silicon oxide or silicon oxynitride. During preparation, the pad oxide layer 401 of silicon oxide may be formed by, for example, furnace tube oxidation, rapid thermal annealing oxidation, in-situ steam oxidation or other thermal oxidation methods. Silicon oxide may be subjected to a nitridation process to form silicon oxynitride, wherein the nitridation process may be high-temperature furnace tube nitridation, rapid thermal annealing nitridation, plasma nitridation or other nitridation processes.

[0070] See also Figure 3 In step S2, a barrier layer 402 is formed on the side of the pad oxide layer 401 facing away from the substrate 100. The pad oxide layer 401 is used to reduce the stress between the substrate 100 and the barrier layer 402, and the barrier layer 402 is used to protect the active area in the subsequent etching process. In this embodiment, the material of the barrier layer 402 may be, for example, silicon nitride. The barrier layer 402 may be formed by, for example, chemical vapor deposition technology during preparation. The chemical vapor deposition technology here may be a low-pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method.

[0071] See also Figure 3 In other embodiments, the carbon layer 403 and / or the anti-reflection layer 404 may be formed on the barrier layer 402 by physical vapor deposition or chemical vapor deposition.

[0072] See also Figures 4 to 6 In step S2, at least two isolation structures 500 are formed on the substrate 100. The two isolation structures 500 are used to separate the adjacent gate 400 structures formed later. The isolation structures 500 may be shallow trench isolation structures 500, for example. In some embodiments, multiple isolation structures 500 may be formed in the substrate 100. The multiple isolation structures 500 divide the substrate 100 into multiple regions. The multiple regions may be distributed in parallel and spaced apart, or may be arranged arbitrarily according to the semiconductor structure. In this embodiment, the substrate 100 region between adjacent isolation structures 500 constitutes a high-voltage device region or a low-voltage device region.

[0073] See also Figures 4 to 6 In step S2, in this embodiment, the step of forming the isolation structure 500 specifically includes: forming a first patterned photoresist layer 405 on the barrier layer 402, the first patterned photoresist layer 405 exposing a portion of the barrier layer 402, and defining the position of the isolation structure 500 by the first patterned photoresist layer 405. In this embodiment, etching can be performed, for example, by using a reactive ion etching or plasma etching process, that is, the barrier layer 402 and the pad oxide layer 401 are sequentially etched by the reactive ion etching or plasma etching process to expose the surface material of the substrate 100, and then the substrate 100 is etched by using a fluorine-containing etching gas with the barrier layer 402 and the pad oxide layer 401 as a mask, thereby forming a first trench 501 extending into the substrate 100.

[0074] See also Figures 4 to 6In step S2, in some embodiments, a photoresist layer may be formed on the blocking layer 402 by, for example, a spin coating method. After exposure and development processes, an opening is formed on the photoresist layer to obtain a first patterned photoresist layer 405. The first patterned photoresist layer 405 is used as a mask to remove the blocking layer 402 and the pad oxide layer 401 under the opening pattern until the substrate 100 is exposed. Then, the photoresist layer may be removed by an ashing method, and then the blocking layer 402 and the pad oxide layer 401 are used as masks to etch the substrate 100 by dry etching to form a first groove 501. The first groove 501 penetrates the pad oxide layer 401 and the blocking layer 402 and extends into the substrate 100. In some embodiments, an anti-reflection layer 404 may be provided on the blocking layer 402. The anti-reflection effect of the anti-reflection layer 404 on the etching beam causes the first groove 501 to form an inverted trapezoidal shape during the etching process. The first trench 501 region will form an isolation structure 500 in the subsequent preparation process. One end of the isolation structure 500 extends into the substrate 100. The substrate 100 covered by the barrier layer 402 and the pad oxide layer 401 is used as an active area to form a semiconductor device.

[0075] See also Figures 4 to 6 In step S2, the specific steps of obtaining the isolation structure 500 include: firstly, forming a first oxide layer 406 on the bottom surface and sidewall of the first trench 501 by chemical vapor deposition, then depositing an insulating material on the first oxide layer 406 and the barrier layer 402 by high-density plasma chemical vapor deposition to fill the first trench 501, and then, for example, by chemical mechanical polishing, making the upper surface of the insulating material in the first trench 501 flush with the upper surface of the barrier layer 402 to form the isolation structure 500. In this embodiment, the material of the first oxide layer 406 can be, for example, silicon oxide or silicon oxynitride, and the insulating material can be, for example, silicon oxide, silicon nitride or silicon oxynitride. The width of the isolation structure 500 can be set according to the design requirements of the semiconductor structure.

[0076] See also Figures 4 to 6 In step S3 and step S4, dry or wet etching is used to remove the blocking layer 402 to expose the pad oxide layer 401. In this embodiment, for example, wet etching is used to remove the blocking layer 402, and the wet etching reagent is, for example, phosphoric acid or hydrofluoric acid.

[0077] See also Figures 4 to 6 In step S3 and step S4, after removing the barrier layer 402, ion implantation is performed on the substrate 100 region between adjacent isolation structures 500, for example, a P well 407 or an N well 408 is formed in the corresponding substrate 100 region, and the ion implantation source used is preferably a phosphorus source, a boron source or a fluorine source.

[0078] See also Figures 7 and 8In step S3 and step S4, the specific steps of forming a recess 600 between the side wall of the isolation structure 500 and the side wall of the substrate 100 include: firstly, forming a second patterned photoresist layer 409 on the upper surface of the isolation structure 500, the second patterned photoresist layer 409 exposes a portion of the upper surface of the isolation structure 500, and the position of the recess 600 is defined by the second patterned photoresist layer 409. In this embodiment, the second patterned photoresist layer 409 can be obtained by the same method as that of obtaining the first patterned photoresist layer 405, which will not be described in detail herein. In the present embodiment, etching can be performed, for example, by using reactive ion etching or plasma etching, that is, the pad oxide layer 401 is first removed by using reactive ion etching or plasma etching, and at the same time, dry etching is used to perform downward etching on the portion of the upper surface of the isolation structure 500 other than that blocked by the second patterned photoresist layer 409, so that arc-shaped curved side walls are formed on both sides of the isolation structure 500, and the side walls of the substrate 100 are exposed at the same time. During this etching process, since the etching selectivity of dry etching for the substrate 100 material and the isolation structure 500 material is different, the side walls of the substrate 100 are not etched at all while the isolation structure 500 is etched to form arc-shaped curved side walls. At this time, the side walls of the substrate 100 are consistent with the side walls of the substrate 100 in the first trench 501 formed in an inverted trapezoidal shape initially, that is, they are an inclined straight line. In this embodiment, the material used for the isolation structure 500 is, for example, silicon dioxide, and the material used for the substrate 100 is, for example, silicon. The dry etching is, for example, a plasma etching method. Since the plasma etching of silicon dioxide can be performed using a gas containing fluorocarbon compounds, the etching gas used can be carbon tetrafluoride (CF4), octafluoropropane or trifluoromethane, etc. In this embodiment, carbon tetrafluoride is used as an etching gas as an example, wherein the reaction rate of fluorine atoms with silicon is very fast, for example, 10-1000 times that of silicon dioxide, and a higher etching selectivity ratio of silicon dioxide to silicon can be obtained. It can be considered that in the fluorocarbon compound gas, the higher the proportion of carbon atoms, the more polymers are formed, so that a high etching selectivity ratio can be obtained. In some embodiments, the fluorine atoms can be increased by adding a silicon source, such as silicon tetrafluoride, to change the fluorine-carbon atomic ratio, thereby improving the etching selectivity ratio of silicon dioxide to silicon. In some embodiments, oxygen can be added to the reaction gas, and the oxygen concentration is, for example, 20%-40%. Oxygen will react with fluorocarbon compounds to release fluorine atoms, and consume a portion of carbon, thereby changing the fluorine-carbon atomic ratio, thereby increasing the etching selectivity of silicon dioxide to silicon. However, when the oxygen concentration is greater than 40%, the etching selectivity decreases. In some embodiments, hydrogen can be added to the etching gas to reduce the etching rate of silicon. When the concentration of hydrogen is, for example, 40%, the etching rate of silicon is approximately equal to 0, which can be regarded as etching only silicon dioxide at this time, but not silicon.

[0079] See also Figures 7 and 8In step S3 and step S4, the second patterned photoresist layer 409 is removed after the recess 600 is formed. The method used may be the same as the method for removing the first patterned photoresist layer 405, which will not be described in detail here.

[0080] See also Fig. 9 In step S5, a tunneling oxide layer 410 is formed on the exposed surface of the substrate 100 and on the side walls of the substrate 100 located in the recesses 600 on both sides. The material of the tunneling oxide layer 410 may be, for example, silicon oxide. In this embodiment, the tunneling oxide layer 410 of silicon oxide may be formed by, for example, furnace oxidation, rapid thermal annealing oxidation, in-situ steam oxidation or other thermal oxidation methods.

[0081] See also Fig.10 In step S6, a floating gate layer 411 is formed on the side of the tunnel oxide layer 410 facing away from the substrate 100. The floating gate layer 411 may be made of doped polysilicon. The polysilicon may also be deposited in an undoped form and then implanted to form doped polysilicon. In other embodiments, other suitable conductive materials may be used instead of doped polysilicon.

[0082] See also Fig.10 and Fig.11 In step S6, the specific steps of forming the floating gate layer 411 on the tunneling oxide layer 410 include: depositing polysilicon on the surface of the tunneling oxide layer 410, the recess 600 and the isolation structure 500, and flattening the deposited polysilicon until the surface of the isolation structure 500 is exposed, thereby obtaining the floating gate layer 411. The above-mentioned deposition process and flattening process preferably adopt conventional techniques in the art, such as using a chemical mechanical flattening method to flatten the polysilicon. In this embodiment, the floating gate layer 411 is used to store charges to set the threshold voltage characteristics of the storage unit, wherein the impurity layer interacts with the polycrystalline structure to weaken the thermally induced grain size growth of the polycrystalline structure and maintain the threshold voltage characteristics of the gate 400 structure, and the impurity layer is, for example, an impurity injected into the polycrystalline structure of the polysilicon floating gate.

[0083] See also Fig.10 and Fig.11In step S7, a gate 700 is formed between the floating gate layer 411 and the tunneling oxide layer 410. The gate 700 includes a plurality of current tunneling channel control surfaces. In this embodiment, for example, there are three current tunneling channel control surfaces. The three current tunneling channel control surfaces include the upper surface of the substrate 100 and the surface formed by the inclined linear sidewalls on both sides of the substrate 100. The gate 700 can control the current tunneling channel from the tunneling oxide layer 410 to the floating gate. The more the number of gates 700 increases, the stronger the control force on the current tunneling channel from the floating gate layer 411 to the substrate 100. The recess 600 formed between the sidewalls of the isolation structure 500 and the sidewalls of the substrate 100 on both sides of the present invention effectively increases the number of gates 700, so that the gate 700 further enhances the control capability of the current tunneling channel. In addition, the gate 700 structure with multiple current tunneling channel control surfaces can increase the width of the effective current tunneling channel, thereby improving the saturation current of the non-volatile memory, and in practical applications, increasing the charge acquisition capability. Due to the increase in the width of the effective current tunneling channel, a certain degree of miniaturization can be performed in the horizontal direction while maintaining the original performance, so that the device can achieve a higher degree of integration.

[0084] See also Fig.12 In other embodiments, a dielectric layer 419 may be formed on the side of the floating gate layer 411 away from the tunneling oxide layer 410, and the dielectric layer 419 covers the exposed surface of the floating gate layer 411 and the isolation structure 500. The dielectric layer 419 may include a silicon oxide layer and a silicon nitride layer 413 formed sequentially on the surface of the floating gate layer 411, wherein the silicon oxide layer may be, for example, silicon oxynitride or silicon dioxide. Specifically, the silicon oxide layer covers the exposed surface of the floating gate layer 411 and the isolation structure 500, and the silicon nitride layer 413 is formed on the surface of the silicon oxide layer in a stacked manner. In some embodiments, the dielectric layer 419 may also include a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414 formed sequentially on the surface of the floating gate layer 411. In this embodiment, the silicon oxide layer and the silicon nitride layer 413 may be formed using a chemical vapor deposition process. In this embodiment, the thickness of each layer of the dielectric layer 419 can be set using existing processes, and specifically may include a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414 having conventional thicknesses sequentially formed on the surface of the floating gate layer 411.

[0085] See also Fig.13 and Fig.14In some embodiments, a third patterned photoresist layer 415 is formed on the side of the dielectric layer 419 away from the floating gate layer 411, and the third patterned photoresist layer 415 exposes the surface of the dielectric layer 419 corresponding to the first groove 501, and the position of the second groove 416 is defined by the third patterned photoresist layer 415. In this embodiment, etching can be performed, for example, by using a reactive ion etching or plasma etching process, that is, etching is performed downward along the portion of the surface of the dielectric layer 419 other than that blocked by the third patterned photoresist layer 415 by using a reactive ion etching or plasma etching process, until the etching is stopped when the upper surface of the isolation structure 500 is exposed, thereby forming a second groove 416 penetrating the dielectric layer 419 in the dielectric layer 419. The width of the second groove 416 can be equal to the width of the upper surface of the isolation structure 500. In other embodiments, the width of the second groove 416 can also be greater than the width of the upper surface of the isolation structure 500. After forming the second groove 416 , the third patterned photoresist layer 415 is removed. The method used may be the same as the method for removing the first patterned photoresist layer 405 , which will not be described in detail here.

[0086] See also Fig.15 In other embodiments, a control gate layer 417 is formed on the side of the dielectric layer 419 facing away from the floating gate layer 411. The control gate layer 417 covers the dielectric layer 419 and fills the second trench 416. In this embodiment, the control gate layer 417 can be a conductive gate formed by doped polysilicon. The dielectric layer 419 separates the control gate layer 417 from the floating gate layer 411 and cannot be directly electrically connected. Each independent floating gate layer 411 is electrically isolated from the substrate 100 by a tunneling oxide layer 410. This electrical isolation allows the floating gate layer 411 to serve as a charge storage unit. The tunneling oxide layer 410 allows charges to enter the floating gate under certain conditions. The charge level in the floating gate can correspond to the logic level, so that data can be stored in the storage unit. A gate 700 is provided between the tunneling oxide layer 410 and the floating gate layer 411, which can control the charge entering the floating gate from the tunneling oxide layer 410. The more gates 700 there are, the stronger the control of the tunneling charge from the floating gate layer 411 to the substrate 100. The recess 600 formed between the sidewall of the isolation structure 500 and the sidewall of the substrate 100 of the present invention effectively increases the length of the gate 700, so that the control capability of the gate 700 on the tunneling charge is further enhanced.

[0087] See also Fig.16 and Fig.17A fourth patterned photoresist layer 418 is formed on the side of the control gate layer 417 away from the dielectric layer 419, and the fourth patterned photoresist layer 418 exposes the surface of the control gate layer 417 corresponding to the second groove 416. In this embodiment, etching can be performed, for example, by using a reactive ion etching or plasma etching process, that is, etching is performed downward along the portion of the control gate layer 417 surface other than that blocked by the fourth patterned photoresist layer 418 by using a reactive ion etching or plasma etching process. After the etching process penetrates the control gate layer 417, the control gate layer 417 material filled in the second groove 416 is etched together, and the etching is stopped when the upper surface of the isolation structure 500 is exposed, thereby obtaining the storage unit of the present invention, and then obtaining the non-volatile memory of the present invention.

[0088] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for preparing a non-volatile memory, characterized in that: It at least includes the following steps: providing a substrate; forming at least two isolation structures on the substrate, wherein one end of each isolation structure extends into the substrate; forming a patterned photoresist layer on the isolation structure; Using the patterned photoresist layer as a mask, dry etching is performed on the portion other than that blocked by the patterned photoresist layer, so as to form a concave portion between the side wall of the isolation structure and the adjacent side wall of the substrate, wherein a portion of the concave portion has an inclined straight line cross-sectional shape, and another portion of the concave portion has an arc-shaped curved cross-sectional shape, and a contour line where the concave portion intersects with the side wall of the substrate presents the inclined straight line cross-sectional shape; the dry etching is plasma dry etching, and the etching gas used in the plasma dry etching is carbon tetrafluoride; forming a tunneling oxide layer on the surface of the substrate and the sidewalls of the substrate; forming a floating gate layer on a side of the tunnel oxide layer facing away from the substrate, wherein the floating gate layer covers the tunnel oxide layer, the recess and the isolation structure; forming a gate between the floating gate layer and the tunneling oxide layer, wherein the gate includes a plurality of current tunneling channel control surfaces; Forming a dielectric layer on a side of the floating gate layer away from the substrate, etching the dielectric layer to form a second trench penetrating the dielectric layer, wherein the width of the second trench is greater than or equal to the width of the upper surface of the isolation structure, and forming a control gate layer on a side of the dielectric layer away from the floating gate layer; A fourth patterned photoresist layer is formed on the side of the control gate layer away from the dielectric layer, and the fourth patterned photoresist layer exposes the surface of the control gate layer corresponding to the second groove. Reactive ion etching or plasma etching is used for etching. After the etching process penetrates the control gate layer, the control gate layer material filled in the second groove is etched together, and the etching is stopped when the upper surface of the isolation structure is exposed.

2. The method for preparing a non-volatile memory according to claim 1, characterized in that: The contour line where the concave portion intersects the side wall of the isolation structure is in the shape of the arc-shaped curve cross-section.

3. The method for preparing a non-volatile memory according to claim 1, characterized in that: The dielectric layer includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer which are formed in sequence.

4. The method for preparing a non-volatile memory according to claim 1, characterized in that: The formation process of the isolation structure includes: forming a pad oxide layer and a barrier layer on the substrate; Etching the barrier layer, the pad oxide layer and the substrate, and stopping etching when etching into the substrate to form a first trench; An insulating material is deposited in the first trench.

5. The method for preparing a non-volatile memory according to claim 4, characterized in that: The formation process of the isolation structure further includes: The barrier layer is removed after planarizing the surface of the insulating material deposited in the first trench.

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