Semiconductor devices

Abstract

A semiconductor device comprising a substrate (6) having a ground electrode on the back side and including a plurality of resin layers (11), and a semiconductor chip (1) mounted on the surface of the substrate (6), comprises: a core (9) embedded in the substrate with one surface exposed on the surface side of the substrate; a filling through hole (12) provided to penetrate the resin layer arranged between the core (9) and the ground electrode in the resin layer (11) to electrically connect the back side of the core (9) to the ground electrode; a cover (4) with high thermal conductivity having an exposed surface provided on the surface of the substrate to cover the semiconductor chip; a bonding material including sintered silver (3) to bond the back side of the cover (4) to the surface of the core (9); and a molding resin (7) transfer-molded on the entire surface of the substrate to surround the cover (4).

Description

Technical Field

[0001] The present application relates to a semiconductor device. Background Art

[0002] In the conventional mold sealing technology, only the upper part of the semiconductor chip is usually sealed with a mold resin, thereby ensuring the electrical insulation of the semiconductor chip and preventing damage caused by physical impact from outside the semiconductor device. On the other hand, since the mold resin has a characteristic of significantly low thermal conductivity, the self-heating of the semiconductor chip is hardly dissipated from the mold resin, but is usually dissipated from the ground electrode surface formed on the back side of the multilayer printed circuit board or the like on which the semiconductor device is mounted (for example, refer to the following patent documents 1 and 2).

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 3-062955

[0004] Patent Document 2: Japanese Patent Application Publication No. 2013-183069

[0005] Since the conventional semiconductor devices are constructed as described above, the following problems exist. First, if the semiconductor chip is driven for a long time at a temperature exceeding about 200°C, the molded resin will burn to the semiconductor chip, causing the semiconductor chip to fail. In addition, in recent years, with the high output and high power density of semiconductor chips, represented by GaN on SiC (a semiconductor device made of gallium nitride that is crystallized and grown on a silicon carbide substrate), the self-heating has increased, but since the heat dissipation from the ground electrode surface through the filled via of the multilayer printed substrate is insufficient, it is difficult to achieve the target performance of high-frequency characteristics or long-term reliability. In addition, since the molded resin enters between the electrodes of the semiconductor chip, parasitic capacitance is generated, which deteriorates the high-frequency characteristics. In addition, since the molded resin does not prevent moisture from invading from the outside air, moisture reaches the semiconductor chip, resulting in deterioration of the moisture resistance of the semiconductor device. Moreover, when multiple semiconductor chips are driven simultaneously, the leakage electromagnetic field interferes between the semiconductor chips, deteriorating the high-frequency characteristics. Summary of the invention

[0006] The present application discloses a technology for solving the above-mentioned problems, and an object of the present application is to provide a semiconductor device that achieves the following.

[0007] (1) Even if the semiconductor chip is driven, the mold resin will not burn to the semiconductor chip.

[0008] (2) The thermal resistance of the entire semiconductor device can be reduced, making it easier to achieve target performance in terms of high-frequency characteristics or long-term reliability.

[0009] The semiconductor device disclosed in the present application comprises:

[0010] substrate;

[0011] A semiconductor chip is disposed on the surface of the substrate;

[0012] a cover bonded to the surface of the substrate and covering the semiconductor chip; and

[0013] a molded resin formed on the entire surface of the substrate and arranged to surround the cover in such a manner that the surface of the cover is exposed; and

[0014] In the thickness direction of the substrate, a height of a surface of the mold resin is lower than a height of a surface of the cover.

[0015] According to the semiconductor device disclosed in the present application, the following effects are achieved: even if the semiconductor chip is driven, the mold resin will not burn to the semiconductor chip, the thermal resistance of the entire semiconductor device can be reduced, and the target performance of high-frequency characteristics and long-term reliability can be easily achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a plan view showing the overall structure of the semiconductor device according to the first embodiment.

[0017] Figure 2 This is a partially enlarged cross-sectional view of the semiconductor device according to the first embodiment.

[0018] Figure 3 This is a partially enlarged plan view of the semiconductor device according to the first embodiment.

[0019] Figure 4 yes Figure 3 A three-dimensional schematic diagram of .

[0020] Figure 5 This is a plan view of the semiconductor chip and its surroundings involved in the semiconductor device of the second embodiment.

[0021] Figure 6 This is a first cross-sectional view of the semiconductor chip and its surroundings involved in the semiconductor device of the second embodiment.

[0022] Figure 7 This is a second cross-sectional view of the semiconductor chip and its surroundings involved in the semiconductor device of the second embodiment.

[0023] Figure 8 This is a third cross-sectional view of the semiconductor chip and its surroundings involved in the semiconductor device of the second embodiment.

[0024] Fig. 9 yes Figure 7 A three-dimensional schematic diagram of .

[0025] Fig.10This is a cross-sectional view of the semiconductor chip and its surroundings involved in the semiconductor device of the third embodiment.

[0026] Fig.11 This is a plan view of the semiconductor chip and its surroundings involved in the semiconductor device of the fourth embodiment.

[0027] Fig.12 This is a cross-sectional view of the semiconductor chip and its surroundings involved in the semiconductor device of the fourth embodiment.

[0028] Fig.13 This is a plan view of the semiconductor chip and its surroundings involved in the semiconductor device of the fifth embodiment. DETAILED DESCRIPTION

[0029] Implementation Method 1

[0030] Hereinafter, the semiconductor device according to the first embodiment will be described.

[0031] Figure 1 is a top view showing the entire image of the semiconductor device (excluding the Cu cover and the molded resin). Figure 2 Yes Figure 1 The semiconductor chip and its vicinity in the semiconductor device are shown in an enlarged manner. Figure 1 A longitudinal cross-sectional view of Figure 3 Yes Figure 1 A top view showing an enlarged view of a semiconductor chip and its vicinity in a semiconductor device (excluding the Cu cover and molded resin). Figure 1 The lateral direction is referred to as the x direction, the longitudinal direction is referred to as the y direction, and the direction perpendicular to the xy plane (the thickness direction of the printed circuit board) is referred to as the z direction.

[0032] exist Figure 1 , Figure 2 In the present embodiment, the semiconductor device of the first embodiment is based on the premise that the following components are included in its structure: a semiconductor chip 1 (in the present embodiment, Figure 2 As shown in FIG. 1 , the structure of GaN on SiC is formed), Au wire 2, sintered silver 3 (also referred to as Ag paste 3. The same below), Cu cover 4, SMD component 5 (SMD is the abbreviation of Surface Mount Device. The same below), printed circuit board 6, molded resin 7, and ceramic sub-mount 8. Among them, Figure 2 As shown, the sintered silver 3 is provided in a structure sandwiching the submount 8. In addition, the mold resin 7 is configured to surround the periphery of the Cu cover 4.

[0033] In addition, Figure 2In the figure, the printed circuit board 6 is composed of the following components in order from the bottom side of the figure: a ground electrode surface 10, a resin layer 11 composed of multiple layers, a filled through hole 12 electrically connecting the ground electrode surface 10 to the Cu core 9, and a peripheral pattern 13. In the figure, the filled through hole 12 is provided in a manner that penetrates two layers of the resin layer 11 close to the ground electrode surface 10. In more detail, the peripheral pattern 13 is equivalent to the first layer Cu wiring pattern 14 (hereinafter also referred to as L1 layer 14).

[0034] in addition, Figure 3 It is a top view of the semiconductor chip and its surroundings involved in the semiconductor device. Figure 1 , and a part thereof is enlarged. In this figure, the semiconductor chip 1 is connected to the peripheral pattern 13b through the input line 2a, and is connected to the peripheral pattern 13c through the output line 2b. In addition, the frame P surrounded by the dotted lines of the upper and lower parts of the peripheral pattern 13a represents the contact area of ​​the bonding material, that is, the sintered silver 3, through the Cu cap 4 and the Cu core 9. In addition, the parts indicated by the two dotted lines are the positions of the open holes.

[0035] Here, the Cu cap has the following features in order to avoid contact with the input line 2a and the output line 2b, that is, to route the lines in a non-contact manner: Figure 2 The tunnel structure with an open hole (refer to the portion indicated by the dotted frame line in the figure) that is open in space is shown, and its cross-sectional shape is C-shaped. In addition, the cross-sectional shape is not limited to the C-shaped structure as long as it can avoid the contact between the semiconductor chip and the Au wire, and can also be a U-shaped shape. The shape of the Cu cover is processed to maximize the contact area with the Cu core 9 of the printed circuit board and minimize the distance from the semiconductor chip, and is installed on the printed circuit board.

[0036] also, Figure 4 In order to clarify the configuration state of the Cu cover and Au wire in the above description in a three-dimensional manner, the above configuration state is shown by using a schematic diagram using a three-dimensional diagram. Through this figure, it can be seen that the input line 2a and the output line 2b connected to the semiconductor chip 1 and the peripheral pattern 13a, and the semiconductor chip 1 and the peripheral pattern 13b, respectively, do not contact the Cu cover 4 through the tunnel structure provided in the Cu cover 4 (in this figure, the two parallelogram parts indicated by the dotted lines indicate the positions of the open holes).

[0037] In the first embodiment, the self-heating of the semiconductor chip first diffuses toward the Cu core 9. Then, on the ground electrode surface 10 side, due to the difference in thermal conductivity between the resin layer 11 (made of FR4 or the like. Here, FR4 is the abbreviation of Flame Retardant Type 4) of the printed circuit board and the filled through hole 12 (for example, FR4 is about 0.3 W / m*K, and copper is 400 W / m*K), most of the heat is transferred from the filled through hole 12. Assuming that there are about 50 filled through holes 12 with a diameter of 1.0×10 －4 m, height 1.4×10 －4 Here, W: Watt, m: meter, K: Kelvin temperature (the same applies hereinafter).

[0038] On the other hand, on the Cu cap side, heat is transferred to the top surface side of the Cu cap via the sintered silver for fixing the Cu cap.

[0039] In this way, by fixing the ground electrode surface 10 and the Cu cap top surface to the housing of the final product by solder and thermally conductive paste, etc., heat dissipation paths of the semiconductor device can be ensured in both the upper and lower directions.

[0040] Here, for sintered silver, by selecting a high heat dissipation type (for example, thermal conductivity of about 150W / m*K), the thermal resistance from the semiconductor chip to the Cu cover can be set to about half of the thermal resistance from the semiconductor chip to the ground electrode surface (about 1K / W).

[0041] If this is converted into the specific size of the Cu cap, the thermal resistance of the metal material is proportional to its electrical resistance, and the proportionality constant is determined by the product of the volume resistivity and the thermal conductivity, so it is roughly the following value. The size of the Cu core related to the thermal resistance from the semiconductor chip to the ground electrode surface is, Figure 6 The cross-sectional area shown is approximately 7×10 －6 m 2 , thickness is about 2.5×10 －4 m, relative to the size of the Cu cover, the area of ​​the two legs is about 7×10 －6 m 2 , thickness is about 2.5×10 －4 m, and the area of ​​the top (described later) is approximately 7×10 －6 m 2 , thickness is about 6×10 －4 m.

[0042] In addition, in Patent Document 1 Figure 2 , Figure 3Patent Document 1 proposes a structure in which a heat sink is provided on the back of the semiconductor chip and exposed to the back of the package. However, the heat sink is joined to a metal cover on the side of the heat sink, and the heat dissipation path from the semiconductor chip to the outside is necessarily longer, which is essentially different from the present embodiment. Therefore, it is believed that the structure proposed in Patent Document 1 has almost no contribution to the heat dissipation of the semiconductor device.

[0043] In this embodiment, since a heat dissipation path can be provided directly above the semiconductor chip, the thermal resistance of the product can be significantly reduced compared to the conventional technology in which heat is dissipated only from the ground electrode surface of the printed circuit board.

[0044] In addition, in Patent Document 2 Fig.10 A semiconductor chip mounted on a component mounting area on a circuit board, a metal cover covering the semiconductor chip, and a sealing body covering only the side surface of the metal cover are proposed. Fig.10 The proposed structure is different from the present embodiment in that a metal cover is not mounted on the element mounting region of the metal cover.

[0045] Therefore, in the structure disclosed in Patent Document 2, it is considered that the separation between the metal cover and the semiconductor chip is quite large, and therefore it is difficult to consider that the metal cover effectively functions to dissipate the self-heat of the semiconductor chip.

[0046] In this embodiment, by directly mounting the semiconductor chip and the metal cover on the Cu core, the self-heating of the semiconductor chip is transmitted through the Cu core, and a heat dissipation path can be set directly above the semiconductor chip. Therefore, compared with the previous technology of dissipating heat only from the ground electrode surface of the printed circuit board, the thermal resistance of the product can be greatly reduced.

[0047] That is, in order to prevent the operating characteristics or reliability of the semiconductor device from being deteriorated due to self-heating, in a semiconductor device having a structure in which a semiconductor chip is sealed with a mold resin, it is possible to prevent the operating characteristics or reliability from being deteriorated due to the physical properties of the mold resin.

[0048] The following describes a method for producing this structure.

[0049] (1) After coating the printed circuit board with Cu core with sintered silver, the semiconductor chip, submount and Cu cover are mounted and heated to the heat setting temperature of the sintered silver (about 200°C) to heat set the sintered silver. The melting point of the temporarily heat-set sintered silver is several hundred degrees Celsius.

[0050] (2) Wire bonding of Au wires.

[0051] (3) The SMD components 5 such as the chip inductor 5a, the chip resistor 5b, and the chip capacitor 5c are mounted by soldering.

[0052] (4) The molding resin is transfer-molded over the entire surface of the printed circuit board.

[0053] (5) Use a grinding device to cut the molded top surface to expose the top surface of the Cu cover.

[0054] Although the bonding material is described above based on high-performance sintered silver, which generally has a thermal conductivity of about 150 W / m*K, as long as the thermal conductivity is 30 W / m*K or more, the thermal resistance from the semiconductor chip to the Cu cover side can be suppressed to be lower than the thermal resistance from the semiconductor chip to the Cu core side. In addition, although the description is based on the use of a Cu core, it is not limited to this. As long as the core has a heat dissipation performance equal to or higher than that of a Cu core and can be bonded with sintered silver, it can be used as a core to replace the Cu core. In addition, the wire is described based on the Au wire, but it is not limited to this. Even Cu wire can achieve the same effect.

[0055] In addition, the substrate constituting the semiconductor device of this embodiment is described above using the representative term "printed substrate", but it is not limited to this, and may also be called a common term, namely, an electronic circuit substrate (including a ceramic substrate). Hereinafter, these are collectively referred to as substrates.

[0056] In addition, the Cu core may not be present, and the semiconductor chip may be directly mounted on the substrate. In addition, the Cu core may not be embedded in the substrate, but may be on the surface of the substrate. In addition, although sintered silver is used for bonding, solder or adhesive may also be used as long as the heat dissipation conditions of the device can be met. Furthermore, although it is assumed that the heat dissipation between the Cu core and the ground electrode is undertaken by filling the through hole, the through hole may not be filled.

[0057] Implementation Method 2

[0058] In the first embodiment, the shape of the Cu cap has a tunnel structure in order to avoid contact with the input line and the output line. Figure 5 In that case, a wall blocking the entrance and exit of the tunnel structure can also be set up (replacing the previous Figure 2 , Figure 4 The open part shown is the inside of the dotted line frame, or Figure 3 The open portion shown is the wall filled with two dotted lines. At this time, the upper filled through hole 12a is set as a through hole directly below the relay pattern 13d for relaying the input line and the output line to the outside. The reason for setting it directly below as described above is to shorten the electrical distance between the input and output of the semiconductor chip and eliminate the need for adding wires.

[0059] exist Figure 5In the figure, the semiconductor chip 1 is connected to the left and right relay patterns 13d respectively through the input line 2a and the output line 2b. In each relay pattern, an upper filling through hole 12a connected to the signal electrode is provided directly below it. In addition, the upper and lower two frames P surrounded by dotted lines shown in the peripheral pattern arranged in the central part represent the contact area between the Cu core and the Cu cover that contributes to heat dissipation. In addition, the frame Q1 surrounded by blank dotted lines shown in the peripheral pattern arranged on the left and right sides of the peripheral pattern arranged in the above-mentioned central part is the contact area between the L1 layer and the Cu cover that does not contribute to heat dissipation.

[0060] Figure 6 , Figure 7 It is expressed from two directions Figure 5 Diagram of the cross-sectional shape. Figure 6 Yes Figure 5 The semiconductor chip and its vicinity in the semiconductor device are shown in an enlarged manner. Figure 5 A cross-sectional view in the y direction (refer to section AA), Figure 7 Yes Figure 5 The semiconductor chip and its vicinity in the semiconductor device are shown in an enlarged manner. Figure 5 A cross-sectional view in the x direction (see section BB). Figure 8 For the sake of Figure 5 The details of the upper filled through hole 12a shown in FIG. Figure 5 The cross section in the y direction is Figure 6 Cross-sectional views of different sections CC.

[0061] exist Figure 7 In the embodiment, an L1 layer 14 is provided in contact with the lower surface of the sintered silver 3. Furthermore, a portion of the Cu cap is formed in a form in which its height position is lower than the height position of the L1 layer 14. The partially protruding portion is a Cu cap protrusion 4b, which becomes a contact portion with the Cu core 9.

[0062] In addition, if Figure 8 As shown in FIG. 1 , an upper filled through hole 12a as a through hole is provided directly below a relay pattern 13d for leading an input line and an output line to the outside. The upper filled through hole 12a is connected to the Cu wiring pattern 15 of the fourth layer via two filled through holes 12 provided below it. With such a structure, the electrical distance between the input and output of the semiconductor chip can be shortened without additionally providing wires, etc.

[0063] Fig. 9 In order to show the Figure 7 The structure of the Cu cover shown in FIG. 1 is a stereoscopic image as an image showing only the Cu cover in three dimensions. Fig. 9 As shown, in Figure 7The Cu cap protrusion 4b described in the above is formed at two locations. Fig. 9 In the figure, the rectangular portion to which the pattern is applied corresponds to the top 16.

[0064] In the first embodiment, the tunnel structure of the Cu cover is open to avoid interference with the input line or the output line, but in the second embodiment, a wall is provided at the entrance and exit of the tunnel structure of the Cu cover and is bonded to the pattern of the L1 layer of the printed circuit board, thereby forming a structure that hermetically seals the semiconductor chip and the Au wire.

[0065] Thus, in addition to the effects of the first embodiment, the following effects are obtained.

[0066] (1) By preventing the mold resin from being burned onto the chip when the semiconductor chip is operated at a high temperature, the active layer temperature at which the semiconductor chip can operate without any problems can be increased.

[0067] (2) The mold resin does not enter the gaps between the source, gate and other electrode structures of the semiconductor chip, so no parasitic capacitance is generated, and degradation of high-frequency characteristics can be prevented.

[0068] (3) The semiconductor chip is sealed by the Cu cap and the Cu core to prevent moisture from entering the chip from the molding resin, thereby improving the moisture resistance of the product.

[0069] (4) The cross-sectional area of ​​the top of the Cu cover is enlarged, and in addition to the content of the above-mentioned item (1), the thermal resistance of the mold top surface side can be reduced.

[0070] (5) It is possible to prevent the leakage of electromagnetic fields from semiconductor chips.

[0071] Implementation 3

[0072] In the second embodiment, the top surface of the molded resin and the top surface of the Cu cap are made equal in height when the ground electrode surface is used as the height reference. However, the molded height may be lower than the height of the Cu cap when the molded resin is molded so that the upper part of the Cu cap is exposed.

[0073] Fig.10 is a diagram for explaining the Cu cap exposed portion and is similar to that of Embodiment 2. Figure 6 As shown in this figure, in this embodiment, a part of the Cu cap protrudes from the upper surface of the mold resin 7. This protruding part is the Cu cap exposed part 4a.

[0074] In this case, since the Cu cap is allowed to be exposed from the upper surface of the mold resin 7, the step of cutting the top surface of the Cu cap with a grinding device can be omitted, and the processing cost can be reduced.

[0075] Implementation 4

[0076] In the second embodiment, the number of semiconductor chips is one, but when multiple semiconductor chips are mounted, a tunnel structure having multiple Cu caps may be provided. For example, if the number of semiconductor chips is two, two tunnel structures may be provided.

[0077] Fig.11 An example of a semiconductor device having two tunnel structures is shown in a plan view. Fig.12 It is about Fig.11 It is seen that there are two tunnel structures corresponding to the number of semiconductor chips.

[0078] exist Fig.11 In the embodiment, a relay pattern 13d is provided on the input side and the output side respectively corresponding to each of the two semiconductor chips 1. When viewed from above, upper filling through holes 12a connected to the signal electrodes are arranged at positions corresponding to the inner sides of each relay pattern 13d, so that no extra wires for connecting between electrodes are required. In addition, the frame P surrounded by dotted lines represents the contact area between the Cu cover and the Cu core (a total of 3 places), and the frame Q1 surrounded by blank dotted lines represents the contact area between the Cu cover and the L1 layer (two places on the left and right). Here, the frame Q1 is also in the same C-shaped shape as the frame Q1 in the second embodiment.

[0079] like Fig.12 As shown, in this embodiment, unlike the above-mentioned embodiment 2, a tunnel structure is provided on the left and right sides respectively corresponding to each of the two semiconductor chips 1. In addition, a filled through hole 12 is provided corresponding to each semiconductor chip at the lower position of the two semiconductor chips 1. The structure other than the above is substantially the same as that of the embodiment 2.

[0080] As described above, when a plurality of semiconductor chips are mounted closely together, the heat dissipation path of the self-heating of the chip is not limited to one side of the chip but is ensured on both sides, thereby alleviating thermal interference between adjacent semiconductor chips.

[0081] Implementation method 5

[0082] In the semiconductor device of the fifth embodiment, when multiple semiconductor chips are mounted, the tunnel structures of the Cu cap are completely separated from each other in space, and a plurality of such structures are provided. In this case, if there are two semiconductor chips, there are two tunnel structures, which is the same as the fourth embodiment, but the shape of the contact area between the Cu cap and the Cu wiring of the first layer is different.

[0083] Specifically, in addition to the form of the fourth embodiment, electrodes are further prepared between relay pads for Cu cap mounting. Fig.131 shows a top view of this case. As shown in the figure, the feature of Q2 surrounded by a blank dashed line in the fifth embodiment, which represents the shape of the contact area between the Cu cap and the L1 layer, is that the C-shaped shape of the frame Q1 in the fourth embodiment is changed to an E-shaped shape. Thus, a sealed structure is formed in which the semiconductor chips, wires, and relay patterns are combined as a whole and separated from each other and sealed.

[0084] In Embodiment 5, the plurality of semiconductor chips can be completely separated from the input and output lines in space. That is, in addition to the effects of Embodiment 2, the electromagnetic fields generated by the plurality of semiconductor chips can be separated in space, thereby preventing characteristic changes caused by electromagnetic wave interference between the chips.

[0085] Implementation 6

[0086] The semiconductor device of the sixth embodiment is obtained by maintaining the structure of the semiconductor device of the first to fifth embodiments except that the material of the Cu cap is replaced from Cu to artificial diamond.

[0087] By replacing the material of the Cu cover with artificial diamond, the following effects are achieved. First, artificial diamond can be electrically insulated from the top surface, thereby eliminating the concern that the chip will be destroyed by ESD (here, ESD is the abbreviation of Electro Static Discharge) due to surges applied from the top surface of the cover as when using a Cu cover. In addition, when artificial diamond is used, the thermal conductivity is about 5 times that of Cu, which can further help reduce thermal resistance.

[0088] Various exemplary embodiments and examples are described in the present application, but various features, forms, and functions described in one or more embodiments are not limited to application in specific embodiments, and may be applied to the embodiments alone or in various combinations.

[0089] Therefore, numerous modifications not shown in the examples are conceivable within the technical scope disclosed in the present application, including, for example, modification, addition or omission of at least one component, and extraction of at least one component and combination with components of other embodiments.

[0090] Specifically, for example, the case where Cu and artificial diamond are used as the material of the cover has been described, but the present invention is not limited to this, and even if Ag is used, the same effect can be expected.

[0091] Description of Reference Numerals

[0092] 1...semiconductor chip; 2...Au line; 2a...input line; 2b...output line; 3...sintered silver (Ag paste); 4...Cu cover; 4a...Cu cover exposed part; 4b...Cu cover protrusion; 5...SMD component; 5a...chip inductor; 5b...chip resistor; 5c...chip capacitor; 6...printed substrate; 7...molded resin; 8...sub-mount; 9...Cu core; 10...ground electrode surface; 11...resin layer; 12...filled through hole; 12a...upper filled through hole; 13, 13a, 13b, 13c...peripheral pattern; 13d...relay pattern; 14...first layer Cu wiring pattern; 15...fourth layer Cu wiring pattern; 16...top.

Claims

1. A semiconductor device, It is characterized in that have: substrate; A semiconductor chip is disposed on the surface of the substrate; a cover having a thermal conductivity of 30 W / m*K or more, bonded to the surface of the substrate by a bonding material having a thermal conductivity of 30 W / m*K or more, and covering the semiconductor chip; a molded resin formed on the entire surface of the substrate and arranged to surround the cover in such a manner that the surface of the cover is exposed; as well as In the thickness direction of the substrate, the molded resin does not overlap with the cover, and a height of a surface of the molded resin is lower than a height of a surface of the cover, The heat of the semiconductor chip is transferred to the top surface side of the cover via the bonding material.

2. The semiconductor device according to claim 1, It is characterized in that The semiconductor device further includes a core having a thermal conductivity of 30 W / m*K or more, the core being embedded in the substrate so that one surface of the core is exposed on the surface side of the substrate. The substrate has a ground electrode on the back surface and includes a plurality of resin layers formed in layers. The semiconductor chip is arranged on the surface of the core opposite to the filled through hole, the filled through hole is provided to penetrate a specific resin layer arranged between the core and the ground electrode among the resin layers and electrically connect the back surface of the core to the ground electrode, the semiconductor chip transfers heat from the filled through hole to the ground electrode surface side due to the difference in thermal conductivity between the resin layer and the filled through hole, and The cover is a cover with high thermal conductivity and is bonded to the surface of the core by a bonding material including sintered silver.

3. The semiconductor device according to claim 2, It is characterized in that The semiconductor device comprises: a peripheral pattern disposed on the surface of the substrate and arranged around the semiconductor chip; and a line disposed on the surface of the substrate and connecting the semiconductor chip to the peripheral pattern, The cover has a tunnel structure formed with an open hole for routing the wires in a non-contact manner.

4. The semiconductor device according to claim 3, It is characterized in that The peripheral pattern is a relay pattern in which an upper filling via hole is arranged directly below, wherein the upper filling via hole is used to relay the line connected to the semiconductor chip to the signal electrode, The entrance and exit of the tunnel structure of the cover is blocked, The electrical signal input and output from the line can be extracted from the second or higher layer from the surface of the substrate to the outside of the cover through the upper filled via.

5. The semiconductor device according to claim 3, It is characterized in that The substrate has a plurality of semiconductor chips. The peripheral pattern has a relay pattern in proportion to the number of the semiconductor chips, the relay pattern being arranged just above an upper filling via hole for relaying the wire connected to the semiconductor chip to the signal electrode, The cover has a tunnel structure corresponding to the number of the semiconductor chips, and the tunnel structure has open holes for wiring the wires in a non-contact manner.

6. The semiconductor device according to claim 5, It is characterized in that The cover has a sealing structure that seals a plurality of combined structures formed by combining the semiconductor chip, the wire, and the relay pattern on the surface of the substrate so as to be separated from each other.

7. The semiconductor device according to any one of claims 1 to 6, It is characterized in that The cover covering the semiconductor chip is made of artificial diamond.

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