Data transmission method and system

Abstract

The present invention discloses a data transmission method and system, the method comprising: obtaining a first descriptor pointer and a second descriptor pointer in a cache space and judging whether the cache space is available based on the first descriptor pointer and the second descriptor pointer; if the cache space is available, transferring the data to be transmitted to the cache space and generating a descriptor; updating the first descriptor pointer based on the amount of data to be transmitted and the attribute of the cache space; reading the data to be transmitted based on the descriptor and updating the second descriptor pointer, and judging whether the second descriptor pointer is equal to the first descriptor pointer, if it is equal, the data transmission ends. Through the scheme of the present invention, the cache space can be recycled, the problem that the block transmission mode of DMA requires a large block of cache space is solved, the cache space is saved, and the fast transmission of data is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a data transmission method and system. Background Art

[0002] More and more sensors and intelligent devices are integrated on the server. The traditional system management bus (SMBus) has a slow transmission speed, a simple structure, and is prone to congestion. The monitoring, management, and upgrade of these devices have become a problem for the server baseboard management controller (BMC). The Management Component Transport Protocol (MCTP) is a media-independent protocol that only defines transport layer messages and is independent of the physical layer and link layer of the transport bus, that is, the MCTP message is encapsulated in the transport layer message of other buses as a data payload. Encapsulating the MCTP message in a high-speed expansion bus for transmission can achieve the purpose of fast transmission speed and high efficiency, thereby solving the problem of slow transmission speed, simple structure, and easy congestion of the traditional system management bus. However, the MCTP protocol does not define how to control the transmission of data, so there is an urgent need for a data transmission method that can enable MCTP messages to be quickly transmitted between the processor and the external device, solving the problem of slow transmission speed, simple structure, and easy congestion of the traditional system management bus.

[0003] DMA (Direct Memory Access) is a data transmission operation. Compared with non-DMA methods, DMA data movement speed is faster, and it can realize fast transmission of batch data and better match high-speed buses. However, the traditional block-based DMA transmission method requires a large block of cache space, and requires that the number of data to be transmitted should be a multiple of 16 bytes. If the transmission size or DMA count value is not a multiple of 16, DMA will not be able to completely transmit the data. Therefore, the present invention proposes a DMA data transmission method based on a linked list, which allows the cache space to be recycled, does not need to limit the size of the data to be transmitted, and does not require a large block of cache space. Summary of the invention

[0004] The present invention proposes a data transmission method and system, which solves the problem that a block-based DMA transmission mode requires a large cache space, saves cache space, and realizes rapid data transmission.

[0005] Based on the above purpose, the present invention provides a data transmission method on the one hand, which specifically includes the following steps:

[0006] Obtaining a first descriptor pointer and a second descriptor pointer in the cache space and determining whether the cache space is available based on the first descriptor pointer and the second descriptor pointer;

[0007] If the cache space is available, transferring the data to be transmitted to the cache space and generating a descriptor;

[0008] updating the first descriptor pointer after the data to be transmitted is transferred to the cache space based on the properties of the data to be transmitted and the cache space;

[0009] Reading the data to be transmitted based on the descriptor and updating the second descriptor pointer, and determining whether the second descriptor pointer is equal to the first descriptor pointer;

[0010] If the second descriptor pointer is equal to the first descriptor pointer, the data transmission is completed.

[0011] In some implementations, obtaining a first descriptor pointer and a second descriptor pointer in the cache space and determining whether the cache space is available based on the first descriptor pointer and the second descriptor pointer further includes:

[0012] The first descriptor pointer and the second descriptor pointer in the cache space are obtained, and the first descriptor pointer and the second descriptor pointer are compared to determine whether the cache space is available.

[0013] In some implementations, comparing the first descriptor pointer and the second descriptor pointer to determine whether the cache space is available includes:

[0014] comparing the first descriptor pointer and the second descriptor pointer;

[0015] If the first descriptor pointer plus 1 is not equal to the second descriptor pointer, the cache space is available.

[0016] In some implementations, obtaining a first descriptor pointer and a second descriptor pointer in a cache space includes:

[0017] If it is the first time to transmit data, the first descriptor pointer and the second descriptor pointer in the cache space are configured to be 0.

[0018] In some implementations, updating the first descriptor pointer after the data to be transmitted is transferred to the cache space based on the attributes of the data to be transmitted and the cache space includes:

[0019] The first descriptor pointer is obtained by adding the amount of the data to be transmitted and modulo the size of the cache space to update the first descriptor pointer after the data to be transmitted is transmitted to the cache space.

[0020] In some implementations, the descriptor includes: a cache address.

[0021] In some implementations, reading the data to be transmitted based on the descriptor includes:

[0022] The data to be transmitted is read from the cache address of the descriptor.

[0023] In some implementations, reading the data to be transmitted based on the descriptor and updating the second descriptor pointer includes:

[0024] In response to the completion of reading the data to be transmitted corresponding to each cache address, the current second descriptor pointer is incremented by 1 to obtain an updated second descriptor pointer.

[0025] In some embodiments, the method further comprises:

[0026] After the data transmission is completed, an interrupt signal is generated to wait for the next data transmission;

[0027] In response to performing the next data transmission, a first descriptor pointer and a second descriptor pointer in the cache space are obtained, and whether the cache space is available is determined based on the first descriptor pointer and the second descriptor pointer.

[0028] In another aspect, the present invention further provides a data transmission system, the data transmission system comprising:

[0029] an acquisition module, the acquisition module being configured to acquire a first descriptor pointer and a second descriptor pointer in the cache space and determine whether the cache space is available based on the first descriptor pointer and the second descriptor pointer;

[0030] a transmission module, wherein the transmission module is configured to transmit the data to be transmitted to the cache space and generate a descriptor if the cache space is available;

[0031] a configuration module, wherein the configuration module is configured to update the first descriptor pointer after the data to be transmitted is transferred to the cache space based on properties of the data to be transmitted and the cache space;

[0032] A reading module, wherein the reading module is configured to read the data to be transmitted based on the descriptor and update the second descriptor pointer, and determine whether the second descriptor pointer is equal to the first descriptor pointer;

[0033] A judgment module, wherein the judgment module is configured to terminate the data transmission if the second descriptor pointer is equal to the first descriptor pointer.

[0034] The present invention has the following beneficial technical effects: through the data transmission method of the present invention, the cache space can be recycled, the block-based DMA transmission method needs a large cache space, the cache space is saved, and the fast data transmission is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A block diagram of an embodiment of a data transmission method provided by the present invention;

[0037] Figure 2 A schematic diagram of an embodiment of a data transmission system provided by the present invention; DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0039] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two non-identical entities with the same name or non-identical parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. The subsequent embodiments will not explain this one by one.

[0040] Based on the above purpose, the first aspect of the embodiments of the present invention provides an embodiment of a data transmission method. Figure 1 As shown, it includes the following steps:

[0041] S1, obtaining a first descriptor pointer and a second descriptor pointer in a cache space and determining whether the cache space is available based on the first descriptor pointer and the second descriptor pointer;

[0042] S2. If the cache space is available, transferring the data to be transmitted to the cache space and generating a descriptor;

[0043] S3, updating the first descriptor pointer after the data to be transmitted is transferred to the cache space based on the attributes of the data to be transmitted and the cache space;

[0044] S4, reading the data to be transmitted based on the descriptor and updating the second descriptor pointer, and determining whether the second descriptor pointer is equal to the first descriptor pointer;

[0045] S5. If the second descriptor pointer is equal to the first descriptor pointer, the data transmission is completed.

[0046] According to the embodiment of the present invention, the first descriptor pointer and the second descriptor pointer in the cache space are used to realize the circular utilization of the cache space, save the cache space for reading and writing data, and realize the fast transmission of data.

[0047] Specifically, taking a data transmission process of a data transmission as an example, when there is data to be sent, assuming that the first address of the cache space of the sending descriptor is 0x8000_0000, the size of the cache space of the sending descriptor is 8, each descriptor occupies 8 bytes, and two packets of data need to be sent, the first descriptor pointer is 2 and the second descriptor pointer is 2, wherein the first descriptor pointer is defined as a send descriptor write pointer (TX Descriptor Write Pointer), and the second descriptor pointer is defined as a send descriptor read pointer (TX Descriptor Read Pointer). Based on the TX Descriptor Write Pointer and the TX Descriptor Read Pointer, it is determined that the cache space is available, and the two packets of data to be sent are transferred to the cache space corresponding to the descriptor. Two descriptors are generated according to the two packets of data to be sent. The TXDescriptor Write Pointer after the data to be transmitted is transferred to the cache space is configured according to the obtained TX DescriptorWrite Pointer, the data to be transmitted and the cache space. For example, the TX Descriptor Write Pointer can be configured as the currently obtained TX Descriptor Write Pointer + the number of data to be transmitted and it is determined whether it is less than the size of the cache space. If it is less, the TX The Descriptor Write Pointer is configured as the currently acquired TX Descriptor Write Pointer + the number of data to be sent, that is, 2+2=4; the TX Descriptor Write Pointer can also be configured as the currently acquired TX Descriptor Write Pointer + the number of data to be sent and modulo the size of the cache space, that is, the TX Descriptor Write Pointer is configured as (2+2)%8=4; assuming that the cache address of the first descriptor is 0x8000_0010, in DMA mode, read the first packet of data to be sent from the cache address corresponding to the first descriptor, update TX Descriptor Read Pointer=3, judge that TX Descriptor Write Pointer≠3, continue to read the second packet of data to be sent from the cache address corresponding to the second descriptor, update TX Descriptor Read Pointer=4, judge that TX Descriptor Write Pointer=4, and then the data sending is completed.

[0048] It should be noted that the method is not limited to using the method based on the obtained first descriptor pointer, the amount of data to be transmitted and the size of the cache space in the above specific implementation to update the first descriptor pointer after the data to be transmitted is transferred to the cache space. The first descriptor pointer after the data to be transmitted is transferred to the cache space can also be updated based on some other methods based on the obtained first descriptor pointer, the data to be transmitted and the attributes of the cache space.

[0049] Furthermore, if the cache space is unavailable, it means that the cache space has been fully used, and it is necessary to wait for the data in the cache space to be read out before transferring the data to be sent to the storage space to prevent the original data from being overwritten.

[0050] In some embodiments, obtaining a first descriptor pointer and a second descriptor pointer in the cache space and determining whether the cache space is available based on the first descriptor pointer and the second descriptor pointer further includes:

[0051] The first descriptor pointer and the second descriptor pointer in the cache space are obtained, and the first descriptor pointer and the second descriptor pointer are compared to determine whether the cache space is available.

[0052] In some embodiments, comparing the first descriptor pointer and the second descriptor pointer to determine whether the cache space is available includes:

[0053] comparing the first descriptor pointer and the second descriptor pointer;

[0054] If the first descriptor pointer plus 1 is not equal to the second descriptor pointer, the cache space is available.

[0055] Specifically, if the current first descriptor pointer is equal to 2 and the second descriptor pointer is equal to 1, the cache space is available; if the current first descriptor pointer is equal to 1 and the second descriptor pointer is equal to 2, the cache space is not available.

[0056] In some embodiments, obtaining a first descriptor pointer and a second descriptor pointer in a cache space includes:

[0057] If it is the first time to transmit data, the first descriptor pointer and the second descriptor pointer in the cache space are configured to be 0.

[0058] Specifically, if data is transmitted for the first time, the first descriptor pointer is configured to be equal to 0, and the second descriptor pointer is configured to be equal to 0.

[0059] In some embodiments, updating the first descriptor pointer after the data to be transmitted is transferred to the cache space based on the attributes of the data to be transmitted and the cache space includes:

[0060] The first descriptor pointer is obtained by adding the amount of the data to be transmitted and modulo the size of the cache space to update the first descriptor pointer after the data to be transmitted is transmitted to the cache space.

[0061] Specifically, if the amount of data to be transmitted is 7, the obtained first descriptor pointer is 2, and the cache space size is 8, then the first descriptor pointer needs to be configured to be (2+7)%8=1.

[0062] In some embodiments, the descriptor includes: a cache address.

[0063] Specifically, each descriptor corresponds to a cache address, and each descriptor occupies 8 bytes.

[0064] In some embodiments, reading the data to be transmitted based on the descriptor includes:

[0065] The data to be transmitted is read from the cache address of the descriptor.

[0066] Specifically, assuming that the cache address of a descriptor is 0x8000_0000, when reading the data to be transmitted contained in this descriptor, first take out the descriptor from 0x8000_0000, then parse the descriptor to obtain information such as the data cache address and data packet size, and then use DMA to take out the data to be transmitted from the data cache address indicated by this descriptor.

[0067] In some embodiments, reading the data to be transmitted based on the descriptor and updating the second descriptor pointer includes:

[0068] In response to the completion of reading the data to be transmitted corresponding to each cache address, the current second descriptor pointer is incremented by 1 to obtain an updated second descriptor pointer.

[0069] Assume that the current second descriptor pointer is 2, and there are data to be transmitted in 5 descriptors. When the data to be transmitted in the first descriptor is read, add 1 to the current second descriptor pointer, that is, 2+1=3, and the updated second descriptor pointer is 3. Then continue to read other descriptors until all 5 descriptors are read. At this time, the updated second descriptor pointer is 7.

[0070] In some embodiments, the method further comprises:

[0071] After the data transmission is completed, an interrupt signal is generated to wait for the next data transmission;

[0072] In response to performing the next data transmission, a first descriptor pointer and a second descriptor pointer in the cache space are obtained, and whether the cache space is available is determined based on the first descriptor pointer and the second descriptor pointer.

[0073] Further, in response to performing the next data transmission, obtaining a first descriptor pointer and a second descriptor pointer in the cache space and determining whether the cache space is available based on the first descriptor pointer and the second descriptor pointer, further includes:

[0074] Obtaining a first descriptor pointer and a second descriptor pointer in the cache space and determining whether the cache space is available based on the first descriptor pointer and the second descriptor pointer;

[0075] If the cache space is available, transferring the data to be transmitted to the cache space and generating a descriptor;

[0076] The first descriptor pointer after the data to be transmitted is transferred to the cache space is configured based on the data to be transmitted and the cache space;

[0077] Reading the data to be transmitted based on the descriptor and updating the second descriptor pointer, and determining whether the second descriptor pointer is equal to the first descriptor pointer;

[0078] If the second descriptor pointer is equal to the first descriptor pointer, the data transmission is completed.

[0079] Taking the data transmission process of sending data from the memory as an example, several embodiments of the present invention are described.

[0080] Assume that the first address of the send descriptor cache space is 0x8000_0000, the size of the send descriptor cache space is 8, each descriptor occupies 8 bytes, the data in the cache space is empty, and it is the first time to send data from the memory to the hardware register. Two packets of data need to be sent. The specific transmission process is as follows:

[0081] Configure the first descriptor pointer to 0 and the second descriptor pointer to 0, wherein the first descriptor pointer is defined as a TX Descriptor Write Pointer and the second descriptor pointer is defined as a TX Descriptor Read Pointer;

[0082] Based on the TX Descriptor Write Pointer and TX Descriptor Read Pointer, it is determined that the cache space is available and data transmission begins;

[0083] Transferring two packets of data to be sent to the cache space corresponding to the descriptor, and generating two descriptors according to the two packets of data to be sent;

[0084] According to the acquired TX Descriptor Write Pointer, the amount of data to be sent and the size of the buffer space, the TX Descriptor Write Pointer after the data to be sent is transferred to the buffer space is configured to be 2, that is, (0+2)%8=2;

[0085] Configure the hardware register to 1 and start reading the data to be sent from the cache space;

[0086] Take out the first descriptor from 0x8000_0000, parse the descriptor content to obtain the data cache address of the data to be sent, and take out the data of the specified length from the data cache address indicated by the descriptor, that is, the data to be sent;

[0087] Add 1 to the TX Descriptor Read Pointer and check whether the TX Descriptor Read Pointer is equal to the TX Descriptor Write Pointer;

[0088] TX Descriptor Read Pointer is not equal to TX Descriptor Write Pointer. Take the second descriptor from 0x8000_0008, parse the descriptor content, and take out the data of the specified length from the data cache address indicated by the second descriptor.

[0089] Add 1 to the TX Descriptor Read Pointer and check whether the TX Descriptor Read Pointer is equal to the TX Descriptor Write Pointer;

[0090] The first data transmission is completed and an interrupt signal is generated.

[0091] Let's start sending data for the second time. Assuming that 7 packets of data need to be sent, the specific process is as follows:

[0092] After the first data transmission, the obtained TX Descriptor Write Pointer is 2, and the TX Descriptor Read Pointer is 2;

[0093] Compare the TX Descriptor Write Pointer and the TX Descriptor Read Pointer to determine if there is data buffer space available and start transmitting data;

[0094] Write the 7 packets of data to be sent into the cache space and generate 7 descriptors;

[0095] Configure TX Descriptor Write Pointer = (2 + 7) % 8 = 1;

[0096] Configure hardware register TX Start = 1;

[0097] Take out the first descriptor from 0x8000_0010, parse the descriptor content to get the data cache address of the data to be sent, and take out the data of the specified length from the data cache address indicated by the descriptor;

[0098] Add 1 to the TX Descriptor Read Pointer and check whether the TX Descriptor Read Pointer is equal to the TX Descriptor Write Pointer;

[0099] TX Descriptor Read Pointer is not equal to TX Descriptor Write Pointer. Repeat reading until the first five descriptors are transmitted. At this time, TX Descriptor Read Pointer = 7.

[0100] TX Descriptor Read Pointer is not equal to TX Descriptor Write Pointer. Take out the sixth descriptor from 0x8000_0038, parse the descriptor content, and take out the data of the specified length from the data cache address indicated by the sixth descriptor.

[0101] Set the TX Descriptor Read Pointer to (7+1)%8=0, and determine whether the TX Descriptor Read Pointer is equal to the TX Descriptor Write Pointer;

[0102] TX Descriptor Read Pointer is not equal to TX Descriptor Write Pointer. Take out the seventh descriptor from 0x8000_0000, parse the descriptor content, and take out the data of the specified length from the data cache address indicated by the seventh descriptor.

[0103] Add 1 to the TX Descriptor Read Pointer and check whether the TX Descriptor Read Pointer is equal to the TX Descriptor Write Pointer;

[0104] The second data transmission is completed and an interrupt signal is generated.

[0105] The process of receiving data transmission from a memory may also be taken as an example to illustrate several embodiments of the present invention.

[0106] Assume that the first address of the cache space of the receive descriptor is 0x4000_0000, the size of the cache space of the receive descriptor is 8, each descriptor occupies 8 bytes, and two packets of data need to be received. The specific transmission process is as follows:

[0107] Configure the first descriptor pointer to 0 and the second descriptor pointer to 0, wherein the first descriptor pointer is defined as a receive descriptor read pointer (RX Descriptor Read Pointer), and the second descriptor pointer is defined as a receive descriptor write pointer (RX Descriptor Write Pointer);

[0108] Based on the RX Descriptor Read Pointer and RX Descriptor Write Pointer, it is determined that the cache space is available and data transmission begins;

[0109] Transferring two packets of data to be received to the cache space corresponding to the descriptor, and generating two descriptors according to the two packets of data to be received;

[0110] According to the acquired RX Descriptor Read Pointer, the amount of data to be received and the size of the cache space, the RX Descriptor Read Pointer after the data to be received is transferred to the cache space is configured to be 2, that is, (0+2)%8=2;

[0111] Configure the hardware register to 1 and start writing the data to be received into the buffer space;

[0112] Take out the first descriptor from 0x4000_0000, parse the descriptor content to get the data cache address of the data to be received, take out the data of the specified length from the data cache address indicated by the descriptor, that is, the data to be received, and write it into the memory;

[0113] Add 1 to the RX Descriptor Write Pointer and check whether the RX Descriptor Write Pointer is equal to the RX Descriptor Read Pointer.

[0114] RX Descriptor Write Pointer is not equal to RX Descriptor Read Pointer. Take the second descriptor from 0x8000_0008, parse the descriptor content, take out the data of the specified length from the data cache address indicated by the second descriptor, and write it into the memory.

[0115] Add 1 to the RX Descriptor Write Pointer and check whether the RX Descriptor Write Pointer is equal to the RX Descriptor Read Pointer.

[0116] The RX Descriptor Write Pointer is equal to the RX Descriptor Read Pointer, data reception is completed and an interrupt signal is generated.

[0117] Based on the same inventive concept, according to another aspect of the present invention, an embodiment of a data transmission system is provided, such as Figure 2 As shown, the data transmission system includes:

[0118] An acquisition module 110, the acquisition module is configured to acquire a first descriptor pointer and a second descriptor pointer in a cache space and determine whether the cache space is available based on the first descriptor pointer and the second descriptor pointer;

[0119] A transmission module 120, wherein the transmission module is configured to transmit the data to be transmitted to the cache space and generate a descriptor if the cache space is available;

[0120] A configuration module 130, the configuration module being configured to update the first descriptor pointer after the data to be transmitted is transferred to the cache space based on properties of the data to be transmitted and the cache space;

[0121] A reading module 140, wherein the reading module is configured to read the data to be transmitted based on the descriptor and update the second descriptor pointer, and determine whether the second descriptor pointer is equal to the first descriptor pointer;

[0122] The judgment module 150 is configured to terminate the data transmission if the second descriptor pointer is equal to the first descriptor pointer.

[0123] In some implementations, the acquisition module 110 is further configured to:

[0124] The first descriptor pointer and the second descriptor pointer in the cache space are obtained, and the first descriptor pointer and the second descriptor pointer are compared to determine whether the cache space is available.

[0125] In some implementations, the acquisition module 110 is further configured to:

[0126] comparing the first descriptor pointer and the second descriptor pointer;

[0127] If the first descriptor pointer plus 1 is not equal to the second descriptor pointer, the cache space is available.

[0128] In some implementations, the acquisition module 110 is further configured to:

[0129] If it is the first time to transmit data, the first descriptor pointer and the second descriptor pointer in the cache space are configured to be 0.

[0130] In some implementations, the configuration module 130 is further configured to:

[0131] The first descriptor pointer is obtained by adding the amount of the data to be transmitted and modulo the size of the cache space to update the first descriptor pointer after the data to be transmitted is transmitted to the cache space.

[0132] In some implementations, the configuration module 140 is further configured to:

[0133] The data to be transmitted is read from the cache address of the descriptor.

[0134] In some implementations, the configuration module 140 is further configured to:

[0135] Reading the data to be transmitted based on the descriptor and updating the second descriptor pointer includes:

[0136] In response to the completion of reading the data to be transmitted corresponding to each cache address, the current second descriptor pointer is incremented by 1 to obtain an updated second descriptor pointer.

[0137] In some implementations, the determination module 150 is further configured to:

[0138] After the data transmission is completed, an interrupt signal is generated to wait for the next data transmission;

[0139] In response to performing the next data transmission, a first descriptor pointer and a second descriptor pointer in the cache space are obtained, and whether the cache space is available is determined based on the first descriptor pointer and the second descriptor pointer.

[0140] In some embodiments, the present invention may also provide a computer device, the computer device comprising:

[0141] processor;

[0142] and a memory, wherein a computer program executable on the processor is stored in the memory, and when the processor executes the program, the following steps are performed:

[0143] S1. Obtain a first descriptor pointer and a second descriptor pointer in a cache space and determine whether the cache space is available based on the first descriptor pointer and the second descriptor pointer;

[0144] S2. If the cache space is available, transferring the data to be transmitted to the cache space and generating a descriptor;

[0145] S3, updating the first descriptor pointer after the data to be transmitted is transferred to the cache space based on the attributes of the data to be transmitted and the cache space;

[0146] S4, reading the data to be transmitted based on the descriptor and updating the second descriptor pointer, and determining whether the second descriptor pointer is equal to the first descriptor pointer;

[0147] S5. If the second descriptor pointer is equal to the first descriptor pointer, the data transmission is completed.

[0148] In some implementations, obtaining a first descriptor pointer and a second descriptor pointer in the cache space and determining whether the cache space is available based on the first descriptor pointer and the second descriptor pointer further includes:

[0149] The first descriptor pointer and the second descriptor pointer in the cache space are obtained, and the first descriptor pointer and the second descriptor pointer are compared to determine whether the cache space is available.

[0150] In some implementations, comparing the first descriptor pointer and the second descriptor pointer to determine whether the cache space is available includes:

[0151] comparing the first descriptor pointer and the second descriptor pointer;

[0152] If the first descriptor pointer plus 1 is not equal to the second descriptor pointer, the cache space is available.

[0153] In some implementations, obtaining a first descriptor pointer and a second descriptor pointer in a cache space includes:

[0154] If it is the first time to transmit data, the first descriptor pointer and the second descriptor pointer in the cache space are configured to be 0.

[0155] In some implementations, updating the first descriptor pointer after the data to be transmitted is transferred to the cache space based on the attributes of the data to be transmitted and the cache space includes:

[0156] The first descriptor pointer is obtained by adding the amount of the data to be transmitted and modulo the size of the cache space to update the first descriptor pointer after the data to be transmitted is transmitted to the cache space.

[0157] In some implementations, the descriptor includes: a cache address.

[0158] In some implementations, reading the data to be transmitted based on the descriptor includes:

[0159] The data to be transmitted is read from the cache address of the descriptor.

[0160] In some implementations, reading the data to be transmitted based on the descriptor and updating the second descriptor pointer includes:

[0161] In response to the completion of reading the data to be transmitted corresponding to each cache address, the current second descriptor pointer is incremented by 1 to obtain an updated second descriptor pointer.

[0162] In some embodiments, the steps further include:

[0163] After the data transmission is completed, an interrupt signal is generated to wait for the next data transmission;

[0164] In response to performing the next data transmission, a first descriptor pointer and a second descriptor pointer in the cache space are obtained, and whether the cache space is available is determined based on the first descriptor pointer and the second descriptor pointer.

[0165] In some embodiments, the present invention further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of any of the above data transmission methods are performed.

[0166] Finally, it should be noted that a person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium of the program can be a disk, an optical disk, a read-only storage memory (ROM) or a random access memory (RAM), etc. The above-mentioned computer program embodiments can achieve the same or similar effects as the corresponding above-mentioned arbitrary method embodiments.

[0167] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0168] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.

[0169] The serial numbers of the embodiments disclosed in the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0170] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0171] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A data transmission method, characterized in that: include: Obtaining a first descriptor pointer and a second descriptor pointer in a cache space and judging whether the cache space is available based on the first descriptor pointer and the second descriptor pointer, wherein the first descriptor pointer is a send descriptor write pointer and the second descriptor pointer is a send descriptor read pointer, configuring a send descriptor write pointer after the data to be transmitted is transferred to the cache space according to the acquired send descriptor write pointer, the data to be transmitted and the cache space, which comprises: configuring the send descriptor write pointer to the currently acquired send descriptor write pointer plus the amount of data to be transmitted and judging whether it is less than the size of the cache space, and if it is less than, configuring the send descriptor write pointer to the currently acquired send descriptor write pointer plus the amount of data to be transmitted and taking the modulus of the size of the cache space to update the first descriptor pointer after the data to be transmitted is transferred to the cache space; If the cache space is available, transferring the data to be transmitted to the cache space and generating a descriptor; updating the first descriptor pointer after the data to be transmitted is transferred to the cache space based on the properties of the data to be transmitted and the cache space; Reading the data to be transmitted based on the descriptor and updating the second descriptor pointer, and determining whether the second descriptor pointer is equal to the first descriptor pointer; If the second descriptor pointer is equal to the first descriptor pointer, the data transmission is completed; Acquiring a first descriptor pointer and a second descriptor pointer in the cache space and determining whether the cache space is available based on the first descriptor pointer and the second descriptor pointer, further comprising: Obtaining the first descriptor pointer and the second descriptor pointer in the cache space, and comparing the first descriptor pointer and the second descriptor pointer to determine whether the cache space is available; Comparing the first descriptor pointer and the second descriptor pointer to determine whether the cache space is available includes: comparing the first descriptor pointer and the second descriptor pointer; If the first descriptor pointer plus 1 is not equal to the second descriptor pointer, the cache space is available; Obtaining the first descriptor pointer and the second descriptor pointer in the cache space includes: If it is the first time to transmit data, the first descriptor pointer and the second descriptor pointer in the cache space are configured to be 0; The descriptor includes: a cache address; Reading the data to be transmitted based on the descriptor includes: Reading data to be transmitted from the cache address of the descriptor; Reading the data to be transmitted based on the descriptor and updating the second descriptor pointer includes: In response to the completion of reading the data to be transmitted corresponding to each cache address, adding 1 to the current second descriptor pointer to obtain an updated second descriptor pointer; Also includes: After the data transmission is completed, an interrupt signal is generated to wait for the next data transmission; In response to performing the next data transmission, a first descriptor pointer and a second descriptor pointer in the cache space are obtained, and whether the cache space is available is determined based on the first descriptor pointer and the second descriptor pointer.

2. A data transmission system, characterized in that: include: An acquisition module, the acquisition module is configured to acquire a first descriptor pointer and a second descriptor pointer in a cache space and determine whether the cache space is available based on the first descriptor pointer and the second descriptor pointer, wherein the first descriptor pointer is a send descriptor write pointer and the second descriptor pointer is a send descriptor read pointer, and the send descriptor write pointer after the data to be transmitted is transferred to the cache space is configured according to the acquired send descriptor write pointer, the data to be transmitted and the cache space, which includes: configuring the send descriptor write pointer to the currently acquired send descriptor write pointer plus the amount of data to be transmitted and determining whether it is less than the size of the cache space, and if it is less than, configuring the send descriptor write pointer to the currently acquired send descriptor write pointer plus the amount of data to be transmitted and taking the modulus of the size of the cache space to update the first descriptor pointer after the data to be transmitted is transferred to the cache space; a transmission module, wherein the transmission module is configured to transmit the data to be transmitted to the cache space and generate a descriptor if the cache space is available; a configuration module, the configuration module being configured to update the first descriptor pointer after the data to be transmitted is transferred to the cache space based on properties of the data to be transmitted and the cache space; A reading module, wherein the reading module is configured to read the data to be transmitted based on the descriptor and update the second descriptor pointer, and determine whether the second descriptor pointer is equal to the first descriptor pointer; A judgment module, wherein the judgment module is configured to terminate the data transmission if the second descriptor pointer is equal to the first descriptor pointer; Acquiring a first descriptor pointer and a second descriptor pointer in the cache space and determining whether the cache space is available based on the first descriptor pointer and the second descriptor pointer, further comprising: Obtaining the first descriptor pointer and the second descriptor pointer in the cache space, and comparing the first descriptor pointer and the second descriptor pointer to determine whether the cache space is available; Comparing the first descriptor pointer and the second descriptor pointer to determine whether the cache space is available includes: comparing the first descriptor pointer and the second descriptor pointer; If the first descriptor pointer plus 1 is not equal to the second descriptor pointer, the cache space is available; Obtaining the first descriptor pointer and the second descriptor pointer in the cache space includes: If it is the first time to transmit data, the first descriptor pointer and the second descriptor pointer in the cache space are configured to be 0; The descriptor includes: a cache address; Reading the data to be transmitted based on the descriptor includes: Reading data to be transmitted from the cache address of the descriptor; Reading the data to be transmitted based on the descriptor and updating the second descriptor pointer includes: In response to the completion of reading the data to be transmitted corresponding to each cache address, adding 1 to the current second descriptor pointer to obtain an updated second descriptor pointer; Also includes: After the data transmission is completed, an interrupt signal is generated to wait for the next data transmission; In response to performing the next data transmission, a first descriptor pointer and a second descriptor pointer in the cache space are obtained, and whether the cache space is available is determined based on the first descriptor pointer and the second descriptor pointer.

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