Semiconductor structure and semiconductor layout structure

Abstract

The present invention discloses a semiconductor structure and a semiconductor layout structure, wherein the semiconductor layout structure includes a substrate, a plurality of gate structures and a plurality of conductive structures. The substrate includes a plurality of active regions extending along a first direction, wherein the plurality of active regions are separated from each other by an isolation structure. The plurality of gate structures are constructed to span across the plurality of active regions along a second direction perpendicular to the first direction, wherein each active region includes a pair of source / drain portions located on opposite sides of the gate structure. The plurality of conductive structures are embedded in the first portion of the isolation structure, wherein the isolation structure is disposed between the plurality of active regions adjacent to each other in the first direction, and the plurality of conductive structures extend along a second direction and are separated from the source / drain portions by the isolation structure. Thus, the semiconductor layout structure of the present invention can reduce the size of a unit cell, thereby achieving a high device density.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a semiconductor layout structure. More specifically, the present invention relates to a semiconductor structure and a semiconductor layout structure having an anti-fuse structure. Background Art

[0002] Fuse elements are often used in semiconductor devices, such as semiconductor memories or logic devices. Antifuses have electrical characteristics opposite to those of fuses, and can repair defective cells by replacing them with redundant cells.

[0003] Usually, an antifuse needs to be controlled by a control gate adjacent to it. Therefore, a memory cell is defined as 1T1C, which represents a transistor (gate) and a capacitor (antifuse). However, when the number of antifuses increases, the traditional 1T1C structure will occupy a large area. In order to achieve high-density memory units or redundancy, the memory cell should be as small as possible. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor structure and a semiconductor layout structure, which can reduce the size of a unit cell, thereby achieving a high device density.

[0005] According to various embodiments of the present invention, a semiconductor layout structure is provided, including a substrate, a plurality of gate structures, and a plurality of conductive structures. The substrate includes a plurality of active regions extending along a first direction, wherein the active regions are separated from each other by an isolation structure. The gate structure is constructed across the active regions along a second direction perpendicular to the first direction, wherein each active region includes a pair of source / drain portions located on opposite sides of the gate structure. The conductive structure is embedded in a first portion of the isolation structure, wherein the isolation structure is disposed between adjacent active regions in the first direction, and the conductive structure extends along a second direction and is separated from the source / drain portion by the isolation structure.

[0006] According to some embodiments of the present invention, the first portion of the isolation structure includes a bottom isolation structure disposed between active regions, and a top isolation structure disposed above the bottom isolation structure and extending along a first direction into the active region opposite to the first portion of the isolation structure.

[0007] According to some embodiments of the present invention, the conductive structure has a sidewall, a portion of which is covered by the top isolation structure.

[0008] According to some embodiments of the present invention, the first portion of the isolation structure has a width greater than a width of the conductive structure in the first direction.

[0009] According to some embodiments of the present invention, the isolation structure further includes a second portion disposed between the active regions in the second direction.

[0010] According to some embodiments of the present invention, the first gate structure and the second gate structure are disposed on the active region, and the active region has a common source / drain portion shared by the first gate structure and the second gate structure.

[0011] According to some embodiments of the present invention, the semiconductor layout structure further includes a plurality of contact plugs respectively connected to the conductive structure, the source / drain portions, and the gate structure.

[0012] According to some embodiments of the present invention, the semiconductor layout structure further includes a plurality of connection lines extending along the first direction and connected to the gate structure through contact plugs.

[0013] According to various embodiments of the present invention, a semiconductor structure is provided, comprising a substrate, a first transistor and a second transistor, an isolation structure, and a conductive structure. The substrate has a first active region and a second active region separated from each other. The first transistor and the second transistor are respectively disposed in the first active region and the second active region. The isolation structure is disposed between the first transistor and the second transistor, wherein the isolation structure has a protruding portion extending laterally into the first active region and the second active region. The conductive structure is embedded in the isolation structure, wherein the conductive structure is separated from the first transistor and the second transistor by the protruding portion of the isolation structure.

[0014] According to some embodiments of the present invention, the conductive structure has a sidewall, a portion of which is covered by the protruding portion of the isolation structure.

[0015] According to some embodiments of the present invention, the isolation structure has a width greater than a width of the conductive structure.

[0016] According to some embodiments of the present invention, the first transistor and the second transistor each include a gate structure located on a substrate and a pair of source / drain portions located in the substrate.

[0017] According to some embodiments of the present invention, the source / drain portion has a lower surface below the lower surface of the conductive structure.

[0018] According to some embodiments of the present invention, the protruding portion of the isolation structure has an upper surface flush with an upper surface of the source / drain portion.

[0019] According to some embodiments of the present invention, the semiconductor structure further includes a plurality of contact plugs respectively connected to the conductive structure, one of the source / drain portions away from the conductive structure, and the gate structure.

[0020] Compared with the prior art, the semiconductor structure and the semiconductor layout structure according to the present invention can reduce the size of the unit cell, thereby achieving high device density. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] When reading the accompanying drawings, the various aspects of the present invention can be fully understood from the following detailed description. It is worth noting that, according to standard practice in the industry, the various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various features can be arbitrarily increased or reduced.

[0022] Figure 1 FIG. 1 is a top view of a semiconductor layout structure according to some embodiments of the present invention.

[0023] Figure 2 According to some embodiments of the present invention, Figure 1 Cross-sectional view taken along line segment AA.

[0024] Figure 3 FIG. 1 is a top view of a semiconductor layout structure having a pair of blown out anti-fuse structures according to some embodiments of the present invention.

[0025] Figure 4 According to some embodiments of the present invention, Figure 3 Cross-sectional view taken along line segment AA.

[0026] Description of main reference numerals:

[0027] 100-substrate, 102a, 102b, 102c, 104a, 104b, 104c, 106a, 106b, 106c-active region, 200-isolation structure, 202-first portion, 204-second portion, 202U-top isolation structure, 202L-bottom isolation structure, 206, 316, 326-upper surface, 210, 210a, 210b, 210c-conductive structure, 214, 314, 324-lower surface, 300, 302a, 302b, 302c, 340a, 304b, 304c, 306a, 306b, 306c - transistors, 310, 320 - gate structures, 312, 322 - source / drain portions, 400, 410, 420, 430 - contact plugs, 502, 504, 506 - connecting lines, 1000 - semiconductor layout structure, A-A' - line segment, AF1, AF2 - anti-fuse structures, W1, W2 - widths. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples to realize the different features of each embodiment. The following describes the specific examples of parts and arrangements to simplify the present invention. Of course, these examples are only examples and are not intended to be restrictive. For example, the formation of the first feature above or on the second feature in the subsequent description may include an embodiment in which the first and second features are formed as direct contacts, and may also include an additional feature that may be formed between the first and second features so that the first and second features may not be directly contacted. In addition, the present invention may repeat element symbols and / or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0029] Spatially relative terms such as "below", "under", "above", "on", etc. are used in this article to facilitate the description of the relative relationship between one element or feature and another element or feature, as shown in the figure. The true meaning of these spatially relative terms includes other orientations. For example, when the figure is flipped 180 degrees up and down, the relationship between one element and another element may change from "below" or "under" to "above" or "on". In addition, the spatially relative descriptions used in this article should also be interpreted in the same way.

[0030] Figure 1 FIG. 1 is a top view of a semiconductor layout structure 1000 according to some embodiments of the present invention. Figure 1 The semiconductor layout structure 1000 includes a substrate 100, a plurality of transistors 300, and a plurality of conductive structures 210a, 210b, 210c. The semiconductor layout structure 1000 may selectively include other elements, which will be described below.

[0031] The substrate 100 includes a plurality of active regions (e.g., active regions 102a, 102b, 102c, 104a, 104b, 104c, 106a, 106b, 106c) extending along a first direction D1, and these active regions are separated from each other by an isolation structure 200. For example, each active region 102a, 102b, 102c, 104a, 104b, 104c, 106a, 106b, 106c extends along the first direction D1. The active regions 102a, 102b, and 102c are separated from each other in the first direction D1. For example, the active regions 102a, 104a, and 106a are parallel to each other and separated in a second direction D2 perpendicular to the first direction D1. In some embodiments, the substrate 100 may be a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, etc., a silicon on insulator (SOI) substrate, etc. It will be appreciated that the number, size and arrangement of active regions may be varied as desired.

[0032] The transistor 300 may include transistors 302a, 302b, 302c, 304a, 304b, 304c, 306a, 306b and 306c disposed in active regions 102a, 102b, 102c, 104a, 104b, 104c, 106a, 106 and 106c, respectively. Figure 1 As shown. In some embodiments, the transistors 300 are respectively disposed in a p-well region (not shown) of the substrate 100. For example, the transistor 302a includes a gate structure 310 and a pair of source / drain portions 312. The gate structure 310 is disposed on the substrate 100 and extends through the active region 102a along a second direction D2 perpendicular to the first direction D1. In some embodiments, the gate structure 310 includes polysilicon, a metal such as aluminum (Al), copper (Cu) or tungsten (W), other conductive materials or a combination thereof. The source / drain portions 312 are disposed on opposite sides of each gate structure 310. In some embodiments, the source / drain portions 312 are doped with an N-type dopant, such as phosphorus or arsenic.

[0033] In some embodiments, the first gate structure (the gate structure 310 adjacent to the conductive structure 210b) and the second gate structure (the gate structure 310 adjacent to the conductive structure 210a) are disposed on each active region (eg, the active region 102a). Figure 1 As shown, two gate structures 310 cross the active region 102a along the second direction D2. The source / drain portion 312 is disposed on both sides of the gate structure 310. Therefore, the active region 102a has a common source / drain portion 312 shared by the gate structures 310 (i.e., the source / drain portion 312 between the gate structures 310). The transistor (e.g., Figure 1 The materials and structures of the transistors 302b, 302c, 304a, 304b, 304c, 306a, 306b and 306c) shown may be the same as those of the transistor 302a and will not be described again below.

[0034] The isolation structure 200 insulates the active regions. Figure 1As shown, the isolation structure 200 may include a first portion 202 and a second portion 204 extending along a first direction D1 and a second direction D2, respectively. For example, the first portion 202 is inserted between the active regions 102a, 102b, and 102c, respectively, to separate these active regions in the first direction D1. The second portion 204 of the isolation structure 200 is inserted between the active regions 102a, 104a, and 106a, respectively, to separate these active regions in the second direction D2. In some embodiments, the isolation structure 200 is a shallow trench isolation (STI). In some embodiments, the isolation structure 200 includes silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), or fluoride-doped silicate (FSG). In some embodiments, the material of the first portion 202 is the same as that of the second portion 204. In other embodiments, the material of the first portion 202 is different from that of the second portion 204.

[0035] The conductive structures (e.g., conductive structures 210a, 210b, and 210c) are embedded in the first portion 202 of the isolation structure 200 and extend along the second direction D2. For example, the conductive structure 210b passes through the active regions 102a, 102b, 104a, 104b, 106a, and 106b. In some embodiments, the conductive structures 210a, 210b, and 210c include conductive materials (e.g., polysilicon, metal, metal alloy), other suitable materials, and / or combinations thereof.

[0036] The semiconductor layout structure 1000 may further include a plurality of contact plugs 400 that are in contact with the conductive structures 210a, 210b, 210c, the source / drain portions 312, 322, 332, and the gate structures 310, 320, 330, respectively. Specifically, the plurality of contact plugs 410 are coupled to the conductive structures 210a, 210b, and 210c, respectively. The plurality of contact plugs 420 are coupled to, for example, the source / drain portions 312 between the gate structures 310, the source / drain portions 322 between the gate structures 320, and the source / drain portions 332 between the gate structures 330, respectively. The contact plugs 430 are coupled to the gate structures 310, 320, 330, respectively. In some embodiments, the plurality of contact plugs 400 include conductive materials (e.g., polysilicon, metal, metal alloy), other suitable materials, and / or combinations thereof.

[0037] In some embodiments, the semiconductor layout structure 1000 further includes a plurality of connection lines 502, 504 and 506 extending along the first direction D1. Figure 1As shown. The connection lines 502, 504 and 506 may pass through the active regions 102a, 102b, 102c, the active regions 104a, 104b, 104c and the active regions 106a, 106b, 106c, respectively. Specifically, the connection line 502 is connected to the gate structures 310, 320, 330 in the active regions 102a, 102b, 102c through the contact plug 430. The connection line 504 is connected to the gate structures 310, 320, 330 in the active regions 104a, 104b, 104c through the contact plug 430. Similarly, the connection line 506 is connected to the gate structures 310, 320, 330 in the active regions 106a, 106b, 106c through the contact plug 430. In some embodiments, the connection lines 502 , 504 , 506 include conductive materials (eg, polysilicon, metal, metal alloy), other suitable materials, and / or combinations thereof.

[0038] Figure 2 According to some embodiments of the present invention, Figure 1 Please refer to the cross-section diagram of the line segment AA. Figure 2 The substrate 100 includes active regions 102a and 102b separated from each other. Transistors 302a and 302b are disposed in the active regions 102a and 102b, respectively. The transistor 302a includes a gate structure 310 and a pair of source / drain portions 312. Similarly, the transistor 302b includes a gate structure 320 and a pair of source / drain portions 322. In some embodiments, each gate structure 310, 320 includes a gate electrode on the substrate 100, and one or more gate dielectric layers (not shown) disposed between the substrate 100 and the gate electrode.

[0039] The first portion 202 of the isolation structure 200 is disposed between the transistors 302a and 302b. The first portion 202 of the isolation structure 200 includes a bottom isolation structure 202L and a top isolation structure 200U disposed thereon. Specifically, the bottom isolation structure 202L is disposed between the active regions 102a and 102b, and the top isolation structure 200U is disposed on the bottom isolation structure 202L and extends into the active regions 102a and 102b on opposite sides of the first portion 202 of the isolation structure 200. Therefore, the top isolation structure 202U protrudes laterally from the sidewall of the bottom isolation structure 202L into the active regions 102a and 102b along the second direction D2. In some embodiments, the top isolation structure 202U of the isolation structure 200 has an upper surface 206 that is flush with the upper surfaces 316 and 326 of the source / drain portions 312 and 322. In some embodiments, source / drain portions 312 and 322 have upper surfaces 316 and 326 , respectively, that are flush with upper surface 206 of top isolation structure 202U of isolation structure 200 . Figure 2As shown, the conductive structure 210b is disposed between the active regions 102a and 102b and is separated from the adjacent source / drain portions 312 and 322 by the top isolation structure 202U. In some embodiments, the lower surface 214 of the conductive structure 210b is located below the lower surfaces 314, 324 of the source / drain portions 312 and 322. In other words, a portion of the sidewall 212 of the conductive structure 210b is covered by the top isolation structure 202U of the isolation structure 200. In some embodiments, the width W1 of the first portion 202 of the isolation structure 200 is greater than the width W2 of the conductive structure 210b. The configurations of other conductive structures (e.g., conductive structures 210a, 210c) may be the same as that of the conductive structure 210b and will not be described again below.

[0040] A plurality of contact plugs 420 are formed on the source / drain portions 312 and 322 respectively away from the first portion 202 of the isolation structure 200. In some embodiments, the contact plugs 420 may pass through an interlayer dielectric layer (not shown) covering the transistors 302a, 302b and the conductive structure 210b to couple the source / drain portions 312 and 322.

[0041] like Figure 2 As shown, a pair of anti-fuse structures AF1 and AF2 are formed between active regions 102a and 102b. The conductive structure 210b serves as the top plate of the anti-fuse structures AF1 and AF2. The source / drain portions 312 and 322 serve as the bottom plates of the anti-fuse structures AF1 and AF2, respectively. The top isolation structure 202U of the isolation structure 200 serves as a dielectric layer between the top plate and the bottom plate of the anti-fuse structures AF1 and AF2. Specifically, the anti-fuse structure AF1 includes a conductive structure 210b, a top isolation structure 202U, and a source / drain portion 312 shared with the transistor 302a. Similarly, the anti-fuse structure AF2 includes a conductive structure 210b, a top isolation structure 202U, and a source / drain portion 322 shared with the transistor 302b. Other anti-fuse structures can be formed between other active regions. For example, another pair of anti-fuse structures can be formed between active regions 104a and 104b (shown in Figure 1 ), and the conductive structure 210b and the top isolation structure 202U can also serve as a top plate and a dielectric layer, respectively.

[0042] Figure 3 FIG. 1 is a top view of a semiconductor layout structure 1000 having a pair of blown anti-fuse structures AF1 and AF2 according to some embodiments of the present invention. Figure 4 According to some embodiments of the present invention, Figure 3 Cross-sectional view taken along line segment AA.

[0043] Please refer to Figure 3. In the case of burnout Figure 2 During the anti-fuse structures AF1 and AF2 shown, a voltage (e.g., 1V) is applied to the connection line 502 to select the transistors 302a, 302b, and 302c, a voltage (e.g., 6V) is applied to the conductive structure 210b, and the source / drain portion 312 between the gate structures 310 and the source / drain portion 322 between the gate structures 320 are grounded through the contact plug 420. Figure 4 As shown, the voltage difference between the two ends of the anti-fuse structures AF1 and AF2 (i.e., the source / drain portions 312 and 322 and the conductive structure 210) causes the dielectric layer (i.e., the top isolation structure 202U) to rupture. In this way, the anti-fuse structures AF1 and AF2 are broken down and become low resistance, while other unselected anti-fuse structures in the semiconductor layout structure 1000 maintain high resistance. That is, for example, the top isolation structure 202U between the conductive structure 210c and the active regions 102b and 102c in the semiconductor layout structure 1000 is not broken. A pair of anti-fuse structures AF1 and AF2 can be blown at the same time and generate a conductive path, so that the blowing efficiency is increased.

[0044] As described above, according to an embodiment of the present invention, a semiconductor layout structure is provided. In the semiconductor layout structure of the present invention, an isolation structure separates a plurality of active regions. A plurality of transistors are respectively arranged in the active regions, and a pair of anti-fuse structures are arranged between adjacent active regions. Specifically, the bottom plate of each anti-fuse structure is the source / drain portion of the adjacent transistor. That is, the transistor shares a source / drain portion with the adjacent anti-fuse structure. The top plate of the anti-fuse structure is embedded in the isolation structure, and the isolation structure separates the transistors in the adjacent active regions so that a pair of anti-fuse structures have the same top plate. The dielectric layer of the anti-fuse structure is an isolation structure arranged between the top plate and the shared source / drain portion. Therefore, a pair of anti-fuse structures can be blown at the same time, so that the blow efficiency is increased. The semiconductor layout structure of the present invention includes a plurality of unit cells, which have a transistor and an anti-fuse structure. Since the top plate of the anti-fuse structure is formed to be embedded in the isolation structure, the size of the unit cell can be reduced, thereby achieving a high device density.

[0045] Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A semiconductor layout structure, characterized in that: Include: A substrate comprising a plurality of active regions extending along a first direction, wherein the plurality of active regions are separated from each other by isolation structures; a plurality of gate structures, arranged across the plurality of active regions along a second direction perpendicular to the first direction, wherein each of the plurality of active regions comprises a pair of source / drain portions located on opposite sides of each of the gate structures; as well as a plurality of conductive structures embedded in a first portion of the isolation structure, wherein the isolation structure is disposed between the plurality of active regions adjacent to each other in the first direction, the plurality of conductive structures extend along the second direction and are separated from the source / drain portion by the isolation structure, and the first portion of the isolation structure has a width greater than a width of the plurality of conductive structures in the first direction, The first portion of the isolation structure comprises: A bottom isolation structure, disposed between the plurality of active regions; as well as A top isolation structure is disposed above the bottom isolation structure and extends along the first direction to the multiple active regions on opposite sides of the first portion of the isolation structure. The top isolation structure has an upper surface flush with an upper surface of the source / drain portion.

2. The semiconductor layout structure according to claim 1, wherein: The bottom isolation structure and the top isolation structure are made of the same material.

3. The semiconductor layout structure according to claim 1, wherein: The plurality of conductive structures have sidewalls, a portion of which is covered by the top isolation structure.

4. The semiconductor layout structure according to claim 1, wherein: The isolation structure further includes a second portion disposed between the plurality of active regions in the second direction.

5. The semiconductor layout structure according to claim 1, wherein: The first gate structure and the second gate structure are disposed on each of the active regions, and each of the active regions has a common source / drain portion shared with the first gate structure and the second gate structure.

6. The semiconductor layout structure according to claim 1, wherein: Also included are a plurality of contact plugs respectively connected to the plurality of conductive structures, the pair of source / drain portions, and the plurality of gate structures.

7. The semiconductor layout structure according to claim 6, characterized in that: Also included are a plurality of connection lines extending along the first direction and connected to the gate structure through the plurality of contact plugs.

8. A semiconductor structure, characterized in that: Include: A substrate having a first active region and a second active region separated from each other; A first transistor and a second transistor are disposed in the first active region and the second active region, respectively, and the first transistor and the second transistor respectively include a pair of source / drain portions located in the substrate; an isolation structure disposed between the first transistor and the second transistor, wherein the isolation structure has a protruding portion extending laterally into the first active region and the second active region, the protruding portion of the isolation structure has an upper surface flush with an upper surface of the pair of source / drain portions, and the isolation structure has a width greater than a width of the conductive structure in the first direction; as well as A conductive structure is embedded in the isolation structure, wherein the conductive structure is separated from the first transistor and the second transistor by the protruding portion of the isolation structure.

9. The semiconductor structure according to claim 8, characterized in that The entire isolation structure is made of the same material.

10. The semiconductor structure according to claim 8, wherein: The first transistor and the second transistor also respectively include a gate structure located on the substrate.

11. The semiconductor structure according to claim 10, characterized in that The pair of source / drain portions have a lower surface below the lower surface of the conductive structure.

12. The semiconductor structure according to claim 10, wherein: A plurality of contact plugs are also included, which are respectively connected to the conductive structure, one of the pair of source / drain portions away from the conductive structure, and the gate structure.

13. The semiconductor structure according to claim 12, wherein: A connecting line is also included which is coupled to the gate structure.

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