Three-dimensional memory and preparation method thereof

Abstract

The present application provides a three-dimensional memory and a method for preparing the same. The method includes: providing a semiconductor structure, including a substrate, a conductive gate layer stacking structure, a top selection gate layer stacking structure, and a dielectric layer stacked in sequence; wherein a channel structure is formed in the core region of the semiconductor structure, and the top selection gate layer and the plug at one end of the channel structure away from the substrate are made of the same type of material; using a first mask plate to form a first through hole in the dielectric layer that stops at the plug of the channel structure by etching, and forming a second through hole of the top selection gate layer that stops at the top selection gate step in the dielectric layer corresponding to the top selection gate step; using a second mask plate to form a third through hole of the conductive gate layer that stops at the conductive gate step in the dielectric layer corresponding to the conductive gate step by etching. The method uses a mask plate to form the first through hole and the second through hole through a single etching process, which can reduce the manufacturing process and save production costs.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a three-dimensional memory and a preparation method thereof. Background Art

[0002] 3D memory is an emerging type of 3D memory that solves the problem of limited storage capacity of 2D or planar NAND memory by stacking memory chips together.

[0003] At present, three-dimensional memories mainly include a step area and a core area. The step area includes at least a top select gate (TSG) and a control gate. When preparing a three-dimensional memory, how to construct contact holes on the step area and how to construct connection holes on the core area is one of the most critical technologies.

[0004] In the existing method for preparing three-dimensional memory, two masks are usually used to etch the contact holes on the step area and the connection holes on the core area respectively. However, when the number of control gate layers is large, for example, 128 layers or more, since the height difference between the top selection gate and the bottom control gate is large, in order to avoid "etching through" the top selection gate during etching, a mask is usually made separately for the top selection gate to etch and form the contact hole of the top selection gate, which will increase the manufacturing process and increase the production cost. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a three-dimensional memory and a method for manufacturing the same. The method for manufacturing the three-dimensional memory provided by the present application uses a mask plate to simultaneously form the connection holes of the core channel structure and the contact holes of the top selection gate of the step area, which can not only prevent the top selection gate from being over-etched, but also reduce the manufacturing process and save production costs.

[0006] A first aspect of the present application provides a method for preparing a three-dimensional memory, the method comprising: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a stacking structure arranged on the substrate, and a dielectric layer covering the stacking structure; the stacking structure comprises a conductive gate layer stacking structure arranged on the substrate and a top selection gate layer stacking structure arranged on the conductive gate layer stacking structure; the semiconductor structure also comprises a step region and a core region, the conductive gate layer stacking structure forms a plurality of conductive gate steps in the step region, each of the conductive gate steps comprises an insulating layer close to the dielectric layer and a conductive gate layer close to the substrate; the top selection gate layer stacking structure forms at least one top selection gate step in the step region, each of the top selection gate steps comprises an insulating layer close to the dielectric layer and a top selection gate layer close to the substrate; a layer penetrating the stacking structure is formed in the core region. A plurality of channel structures are provided, each of the channel structures is provided with a plug at one end away from the substrate, and the top selection gate layer and the plug are made of the same type of material; a first mask plate is covered on the outer surface of the dielectric layer away from the substrate, and etching is started at a preset position on the first mask plate in a direction perpendicular to the outer surface of the dielectric layer until a plurality of first through holes are formed in the dielectric layer, which stop at the plugs of the plurality of channel structures respectively, and second through holes of the top selection gate layer are formed in the dielectric layer corresponding to the at least one top selection gate step, which stop at each top selection gate step; a second mask plate is covered on the outer surface of the dielectric layer away from the substrate, and etching is started at a preset position on the second mask plate in a direction perpendicular to the outer surface of the dielectric layer, until a plurality of third through holes of the conductive gate layer are formed in the dielectric layer, which stop at the plurality of conductive gate steps respectively.

[0007] A second aspect of the present application provides a three-dimensional memory, which is prepared by the preparation method described in the first aspect.

[0008] The preparation method of the three-dimensional memory provided in the present application, the top selection gate layer adopts the same type of material as the plug, so that the mask plate used to form the second through hole of the top selection gate step can be combined with the mask plate used to form the first through hole of the core area into one mask plate. In this way, the first through hole and the second through hole can be formed by one mask plate through one etching process, which can not only prevent the top selection gate from being over-etched, but also reduce the manufacturing process and save production costs.

[0009] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the process of the method for preparing the three-dimensional memory provided in the embodiment of the present application.

[0011] Figure 2 It is a schematic diagram of the structure of a three-dimensional memory provided in the first embodiment of the present application.

[0012] Figure 3 It is a schematic structural diagram of the three-dimensional memory provided by the first embodiment of the present application in the step of forming the first through hole and the second through hole.

[0013] Figure 4 It is a schematic structural diagram of the three-dimensional memory provided in the first embodiment of the present application in the step of forming the third through hole.

[0014] Figure 5 It is a structural schematic diagram of the steps of filling the first through hole, the second through hole and the third through hole of the three-dimensional memory provided by the first embodiment of the present application.

[0015] Figure 6 yes Figure 1 Detailed flowchart of step 601 in FIG.

[0016] Figure 7 It is a schematic diagram of the structure of a three-dimensional memory provided in the second embodiment of the present application.

[0017] Figure 8 It is a structural schematic diagram of the step of forming a channel structure of a three-dimensional memory provided in the second embodiment of the present application.

[0018] Fig. 9 It is a schematic structural diagram of the step of forming a top selection gate step in a three-dimensional memory provided by the second embodiment of the present application.

[0019] Figure 10a-Figure 10d It is a schematic structural diagram of the step of forming a top selection gate step in a three-dimensional memory provided by the second embodiment of the present application.

[0020] Description of main component symbols:

[0021] Semiconductor structures 100, 100'

[0022] Substrate 60

[0023] Stacking structure 10

[0024] Initial stacking structure 10'

[0025] Core Area 101

[0026] Step area 102

[0027] Channel structure 20

[0028] Dielectric layer 30

[0029] Plug 21

[0030] Conductive gate layer stack structure 11

[0031] Top selection gate layer stack structure 12

[0032] Insulation layer / sacrificial layer alternating stacking structure 11'

[0033] Conductive gate step 110

[0034] Top select gate step 120

[0035] Insulation layers 112, 122

[0036] Top selection gate layer 121

[0037] Conductive gate layer 111

[0038] Sacrificial layer 111'

[0039] First through hole 311

[0040] The second through hole 312

[0041] The third through hole 313

[0042] Mask plates 200, 210, 220, 230

[0043] Etching windows 201, 202, 211

[0044] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] In the description of the present invention, it should be noted that the terms "upper", "lower", "inner side", "outer side" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and the like are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. The term "plurality" refers to a number greater than 1, for example, two, three or more.

[0047] See also Figure 1 The present application provides a method for preparing a three-dimensional memory, the method comprising:

[0048] Step 601 , providing a semiconductor structure 100 .

[0049] Specifically, Figure 2 As shown, the semiconductor structure 100 includes a substrate 60 , a stacked structure 10 disposed on the substrate 60 , and a dielectric layer 30 covering the stacked structure 10 .

[0050] In the embodiment of the present application, the material of the substrate 60 is single crystal silicon (Si). Of course, in other embodiments, the material of the substrate 60 can be elemental semiconductors such as germanium (Ge), compound semiconductors such as germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb), alloy semiconductors such as gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and / or gallium indium arsenide phosphide (GaInAsP) or a combination of the above materials. In addition, the substrate 60 can be a "semiconductor on insulator" wafer, such as silicon on insulator (SOI) or germanium on insulator (GOI), etc., and various potential wells of p-type / n-type or deep or shallow required for a three-dimensional memory can be formed in the substrate 60 by processes such as ion implantation.

[0051] Further, the stacked structure 10 includes a conductive gate layer stacked structure 11 disposed on the substrate 60 and a top selection gate layer stacked structure 12 disposed on the conductive gate layer stacked structure 11. The conductive gate layer stacked structure 11 is formed on the top surface of the substrate 60, the conductive gate layer stacked structure 11 includes an insulating layer 112 and a conductive gate layer 111 alternately stacked on the substrate 60, and the top selection gate layer stacked structure 12 is stacked on the top insulating layer 112 of the conductive gate layer stacked structure 11. The top selection gate layer stacked structure 12 includes a top selection gate layer 121 and an insulating layer 122 alternately stacked. Exemplarily, in the embodiment of the present application, the top selection gate layer stacked structure 12 includes a top selection gate layer 121 / insulating layer 122 pair, that is, a top selection gate layer 121 and an insulating layer 122 sequentially stacked on the top insulating layer 112 of the conductive gate layer stacked structure 11. In other embodiments, the top selection gate layer stack structure 12 may include a plurality of top selection gate layer 121 / insulation layer 122 pairs, which is not limited herein.

[0052] Furthermore, the semiconductor structure 100 further includes a core region 101 for storing data and a step region 102 arranged around the core region 101, wherein the step region 102 is arranged at the end of the semiconductor structure 100. The conductive gate layer stacking structure 11 forms a plurality of conductive gate steps 110 in the step region 102, and each of the conductive gate steps 110 includes an insulating layer 112 close to the dielectric layer 30 and a conductive gate layer 111 close to the substrate 60. Figure 2As shown, each of the conductive gate steps 110 has a conductive gate layer 111 / insulating layer 112 pair. In other embodiments, each of the conductive gate steps 110 may also have multiple conductive gate layer 111 / insulating layer 112 pairs, which are not limited here. Wherein, the conductive gate layer 111 includes a control gate layer. The top selection gate layer stacking structure 12 forms at least one top selection gate step 120 in the step area 102, and each of the top selection gate steps 120 includes a layer of insulating layer 122 close to the dielectric layer 30 and a layer of top selection gate layer 121 close to the substrate 60. A plurality of channel structures 20 penetrating the stacking structure 10 are formed in the core area 101, and a plug 21 is provided at one end of each of the channel structures 20 away from the substrate 60, and the top selection gate layer 121 and the plug 21 are made of the same type of material. It should be noted that the plug 21 can be used to lead out and control the gate of each storage particle in the core area 101. In the core area 101, the number of stacking layers of the conductive gate layer stacking structure 11 can be, for example, 32 layers, 64 layers, etc. It can be understood that the more the number of stacking layers of the conductive gate layer stacking structure 11 is, the higher the integration of the three-dimensional memory can be.

[0053] In the embodiment of the present application, the materials of the top selection gate layer 121 and the plug 21 in the channel structure 20 both include polysilicon. Exemplarily, in order to solve the problem of high resistivity of polysilicon, in some embodiments, the plug 21 and the top selection gate layer 121 are made of doped polysilicon, for example, p-type doping ions are implanted into the plug 21 made of polysilicon, so that the threshold voltage of the plug 21 can be reduced, which is convenient for its ohmic contact with the metal wiring and for controlling the threshold voltage of the top selection gate. In other embodiments, the thickness of the top selection gate layer 121 in the top selection gate layer stacking structure 12 is greater than the thickness of the conductive gate layer 111 in the conductive gate layer stacking structure 11, so that the resistance of the top selection gate layer 121 can be reduced by increasing the thickness of the top selection gate layer 121. Preferably, the thickness of the top selection gate layer 121 is 200nm.

[0054] In step 602, a first mask plate 200 is covered on the outer surface of the dielectric layer 30 away from the substrate 60, and etching is started at a preset position on the first mask plate 200 along a direction perpendicular to the outer surface of the dielectric layer 30 until a plurality of first through holes 311 are formed in the dielectric layer 30, which stop at the plugs 21 of the plurality of channel structures 20 respectively, and a second through hole 312 is formed in the dielectric layer 30, which stops at the top selection gate layer 121 of each top selection gate step 120, corresponding to the at least one top selection gate step 120.

[0055] Specifically, Figure 3 As shown, a mask is covered on the outer surface of the dielectric layer 30 away from the substrate 60, and a first etching window 201 corresponding to a preset formation position of the first through hole 311 of the core region 101 is formed on the mask, and a second etching window 202 corresponding to a preset formation position of the second through hole 312 of the top selection gate step 120 is formed, thereby obtaining the first mask 200. In a direction perpendicular to the outer surface of the dielectric layer 30 (such as Figure 3 The semiconductor structure 100 exposed to the etching window of the first mask plate 200 is etched to form the first through hole 311 and the second through hole 312, so that each of the first through holes 311 exposes the corresponding plug 21, and the second through hole 312 exposes the top selection gate layer 121, wherein the first through hole 311 is a connection hole connected to the plug 21, and the second through hole 312 is a contact hole connected to the top selection gate. It can be understood that the first through hole 311 and the second through hole 312 can be formed by wet etching or dry etching, and the etching method is not specifically limited here, as long as it can meet the corresponding processing requirements.

[0056] In the embodiment of the present application, after forming the first through hole 311 and the second through hole 312 , the method further includes removing the first mask plate 200 .

[0057] It should be noted that, in the existing three-dimensional memory, the top selection gate layer 121 is made of the same material as the conductive gate layer 111 (for example, metal tungsten W). However, when the conductive gate layer stacking structure 11 has a large number of stacked layers, for example, 128 layers or more, due to the large height difference between the top selection gate and the bottom control gate, if a mask plate is used to form the connecting hole between the conductive gate layer and the top selection gate layer, the top selection gate layer 121 is prone to be "etched through" due to excessive etching.

[0058] In the method for preparing a three-dimensional memory provided in the present application, since the top selection gate layer 121 is made of the same material as the plug 21, such as polysilicon, and the height difference between the two is small (not exceeding 200nm), a first mask plate 200 can be used to form the first through hole 311 and the second through hole 312 through a single etching process (both using polysilicon as an etching stop layer). In this way, not only can the top selection gate layer 121 be prevented from being "etched through", but there is no need to make a mask plate for the top selection gate layer 121 separately, thereby reducing the manufacturing process and saving production costs.

[0059] In step 603, a second mask plate 210 is covered on the outer surface of the dielectric layer 30 away from the substrate 60, and etching is started at a preset position on the second mask plate 210 along a direction perpendicular to the outer surface of the dielectric layer 30 until a plurality of third through holes 313 of the conductive gate layer 111 that respectively stop at the plurality of conductive gate steps 110 are formed in the dielectric layer 30 corresponding to the plurality of conductive gate steps 110.

[0060] Specifically, Figure 4 As shown, a mask is covered on the outer surface of the dielectric layer 30 away from the substrate 60, and an etching window 211 corresponding to a preset formation position of a third through hole 313 of the conductive gate step 110 is formed on the mask to obtain the second mask 210. Figure 4 The semiconductor structure 100 exposed to the etching window 211 of the second mask plate 210 is etched to form a plurality of the third through holes 313, so that the plurality of the third through holes 313 expose the conductive gate layer 111 in the conductive gate step 110 of different layers.

[0061] In the embodiment of the present application, the method further includes: after forming the third through hole 313 , removing the second mask plate 210 .

[0062] It should be noted that the order of step 602 and step 603 is not limited in the present application. In other embodiments, step 603 may be performed before step 602. Figure 5 As shown, after the first through hole 311 , the second through hole 312 and the third through hole 313 are formed by processing, each through hole can be used to fill a conductive material (such as metal tungsten) so that the semiconductor structure 100 meets corresponding functional requirements.

[0063] For details, please refer to Figure 6-10d , step 601 specifically includes the following steps:

[0064] Step 6011, forming an initial stacking structure 10' and a dielectric layer 30 covering the initial stacking structure 10' on the substrate 60 in sequence. The initial stacking structure 10' includes an insulating layer / sacrificial layer alternating stacking structure 11' formed on the substrate 60 and a top selection gate layer stacking structure 12 formed on the insulating layer / sacrificial layer alternating stacking structure 11'. The structural schematic diagram of the semiconductor structure 100' formed after executing step 6011 is shown in FIG. Figure 7 shown.

[0065] It is understandable that there are many methods for forming the insulating layer / sacrificial layer alternating stacking structure 11', and chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods can be used to alternately deposit insulating layers 112 and sacrificial layers 111' on the substrate 60. Among them, the insulating layer 112 and the insulating layer 122 are made of silicon oxide (SixOy, such as SiO2), silicon nitride (SixNy, such as SiN), silicon oxide nitride (SiON) or a combination of the above materials, and the sacrificial layer is made of silicon nitride (SixNy, such as SiN) amorphous silicon, polycrystalline silicon, aluminum oxide or a combination of the above materials. The sacrificial layer 111' will be replaced by a conductive material in the subsequent manufacturing process and serve as a conductive gate layer 111, and the material of the dielectric layer 30 includes silicon oxide (SixOy, such as SiO2).

[0066] Step 6012: Cover the outer surface of the dielectric layer 30 away from the substrate 60 with a third mask plate (not shown), and a predetermined position on the third mask plate is perpendicular to the outer surface of the dielectric layer 30 (eg Figure 3 The semiconductor structure 100 is etched in the YO direction as shown in FIG. 6 , until a plurality of channel holes are formed in the dielectric layer 30 corresponding to the initial stacked structure 10′ and stop at the substrate 60, and the channel structure 20 is formed in each of the channel holes. Exemplarily, the plurality of channel holes can be formed by a dry etching process. After executing step 6012, a schematic diagram of a structure in which a plurality of channel structures 20 are formed in the core region 101 of the semiconductor structure 100′ is shown in FIG. Figure 8 As shown, a plug 21 is formed at one end of each channel structure 20 away from the substrate 60 .

[0067] Step 6013 , forming at least one top selection gate step 120 in the step region 102 .

[0068] Exemplarily, the step of forming the top selection gate step 120 in the step region 102 is as follows: covering the outer surface of the dielectric layer 30 away from the substrate 60 with a fourth mask plate 220, wherein the fourth mask plate 220 includes a mask pattern, and the position of the mask pattern corresponds to the preset formation position of the top selection gate step 120 in the core region 101 and the step region 102. Fig. 9The semiconductor structure 100 exposed to the mask pattern of the fourth mask plate 220 is etched to remove the top selection gate layer 121, the insulation layer 122 and the dielectric layer 30 on the insulation layer / sacrificial layer alternating stack structure 11' to form a top selection gate step 120. After executing step 6013, a schematic diagram of the structure of the top selection gate step 120 is shown in FIG. Fig. 9 shown.

[0069] In other embodiments, a plurality of the top selection gate steps 120 may be formed by a trimming / etching process.

[0070] Step 6014 , forming a plurality of conductive gate steps 110 in the step region 102 .

[0071] See also Figure 10a-Figure 10d In the embodiment of the present application, the plurality of conductive gate steps 110 are formed by a trimming / etching process. Exemplarily, the specific steps of the trimming / etching process include:

[0072] Perform a first trimming step, where the outer surface of the semiconductor structure 100' away from the substrate 60 is covered with a fifth mask plate 230, and a fifth mask plate 230 is formed along a horizontal direction parallel to the substrate 60 (for example, Fig.10a The edge of the fifth mask plate 230 is trimmed by a step width (in the XO direction shown), exposing a portion of the surface of the insulating layer / sacrificial layer alternating stack structure 11' below the top selection gate step 120. Exemplarily, the fifth mask plate 230 can be trimmed with an oxygen-containing gas, and the oxygen-containing gas can include one of gases containing oxygen elements such as O2, O3, NO, NO2, CO and CO2. Perform a first etching step, along a direction perpendicular to the outer surface of the dielectric layer 30 (such as Fig.10a The semiconductor structure 100' exposed to the fifth mask 230 is etched to remove n (for example, 1) insulating layer 112 / sacrificial layer 111' pairs to form a first step. The schematic diagram of the structure of forming the first step in the step region 102 of the semiconductor structure 100' is shown in FIG. Fig.10a shown.

[0073] A second trimming step is performed, again in a horizontal direction parallel to the substrate (e.g. Fig.10b The edge of the fifth mask plate 230 is trimmed by a step width in the XO direction shown in FIG. 1 . A second etching step is performed to form a second step on the first step. A schematic diagram of a structure in which a second step is formed in the step region 102 of the semiconductor structure 100 ′ is shown in FIG. Fig.10b shown.

[0074] A third trimming step is performed, again in a horizontal direction parallel to the substrate (e.g., Fig.10c The third etching step is performed to form a third step on the second step. The schematic diagram of the structure of forming the third step in the step region 102 of the semiconductor structure 100' is shown in FIG. Fig.10c shown.

[0075] It is understandable that a number of steps, for example, 64, 128, etc., can be formed by repeatedly performing the above trimming / etching steps. Preferably, the width of each step is substantially the same.

[0076] like Fig.10d As shown, after forming a plurality of the conductive gate steps 110 , the method further includes: covering the plurality of the conductive gate steps 110 with a dielectric layer 30 .

[0077] Step 6015 , using a conductive gate layer 111 to replace the sacrificial layer 111 ′ in the insulating layer / sacrificial layer alternating stacking structure 11 ′, to obtain the stacking structure 10 .

[0078] For details, please refer to Fig.10d and Figure 2 , illustratively, the material of the sacrificial layer includes silicon nitride, and step 6015 specifically includes the following steps:

[0079] The silicon nitride in the insulating layer / sacrificial layer alternating stacked structure 11 ′ is removed.

[0080] An adhesion material and a high-K dielectric layer are deposited at the sacrificial layer 111' position in the insulating layer / sacrificial layer alternating stacking structure 11', and then filled with a conductive material to form the conductive gate layer 111. Preferably, the high-K dielectric layer is selected from any one or more combinations of aluminum oxide, zirconium oxide, and hafnium oxide. The adhesion material is selected from any one or more combinations of Ti, TiN, and TaN, and the adhesion material is disposed between the conductive material and the insulating layer 112. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or any combination thereof.

[0081] It should be noted that, in the step of forming the conductive gate layer 111, since the adhesion material and the high-K dielectric layer are deposited first and then filled with the conductive material, wherein the thickness of the adhesion material and the high-K dielectric layer is about 10 nm, this will reduce the filling space of the conductive material to a certain extent and increase the process difficulty of forming the conductive gate. However, in the embodiment of the present application, the conductive material of the top selection gate layer 121 is polysilicon. Therefore, there is no need to deposit the adhesion material and the high-K dielectric layer. Then, the top selection gate layer 121 in the present application can provide a larger filling space for the conductive material.

[0082] The preparation method of the three-dimensional memory provided in the present application, the top selection gate layer adopts the same type of material as the plug, so that the mask plate used to form the second through hole of the top selection gate step can be combined with the mask plate used to form the first through hole of the core area into one mask plate. In this way, the first through hole and the second through hole can be formed by one mask plate through one etching process, which can not only prevent the top selection gate from being over-etched, but also reduce the manufacturing process and save production costs.

[0083] In addition to the above-mentioned method for preparing the three-dimensional memory, the embodiment of the present application also provides a three-dimensional memory. In a specific embodiment, the three-dimensional memory device is prepared by the above-mentioned preparation method. The three-dimensional memory and the preparation method of the three-dimensional memory in the embodiment of the present application can achieve the advantages of the present application, and the two can be used together or separately, and the present application has no special restrictions on this.

[0084] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for preparing a three-dimensional memory, characterized in that: include: A semiconductor structure is provided, wherein the semiconductor structure comprises a substrate, a stacking structure arranged on the substrate, and a dielectric layer covering the stacking structure; the stacking structure comprises a conductive gate layer stacking structure arranged on the substrate and a top selection gate layer stacking structure arranged on the conductive gate layer stacking structure; the semiconductor structure further comprises a step region and a core region, the conductive gate layer stacking structure forms a plurality of conductive gate steps in the step region, each of the conductive gate steps comprises an insulating layer close to the dielectric layer and a conductive gate layer close to the substrate; the top selection gate layer stacking structure forms at least one top selection gate step in the step region, each of the top selection gate steps comprises an insulating layer close to the dielectric layer and a top selection gate layer close to the substrate; a plurality of channel structures penetrating the stacking structure are formed in the core region, a plug is provided at one end of each of the channel structures away from the substrate, and the top selection gate layer and the plug are made of the same type of material; A first mask is covered on the outer surface of the dielectric layer away from the substrate, and etching is started at a preset position on the first mask in a direction perpendicular to the outer surface of the dielectric layer until a plurality of first through holes are formed in the dielectric layer, respectively stopping at the plugs of the plurality of channel structures, and a second through hole of the top selection gate layer is formed in the dielectric layer corresponding to the at least one top selection gate step, stopping at each top selection gate step; A second mask plate is covered on the outer surface of the dielectric layer away from the substrate, and etching is started at a preset position on the second mask plate in a direction perpendicular to the outer surface of the dielectric layer until a plurality of third through holes of the conductive gate layer are formed in the dielectric layer corresponding to the plurality of conductive gate steps and respectively stop at the plurality of conductive gate steps.

2. The method according to claim 1, characterized in that The semiconductor structure provided herein specifically comprises: An initial stacking structure and a dielectric layer covering the initial stacking structure are sequentially formed on the substrate, wherein the initial stacking structure comprises an insulating layer / sacrificial layer alternating stacking structure disposed on the substrate and a top selection gate layer stacking structure on the insulating layer / sacrificial layer alternating stacking structure; Covering the outer surface of the dielectric layer away from the substrate with a third mask plate, and starting etching at a preset position on the third mask plate in a direction perpendicular to the outer surface of the dielectric layer, until a plurality of channel holes respectively stopping at the substrate are formed in the dielectric layer corresponding to the initial stacking structure, and the channel structure is formed in each of the channel holes; forming at least one of the top selection gate steps in the step region; forming a plurality of conductive gate steps in the step region; The stacked structure is obtained by replacing the sacrificial layer in the insulating layer / sacrificial layer alternating stacked structure with a conductive gate layer.

3. The method according to claim 2, characterized in that The sacrificial layer comprises silicon nitride; The step of replacing the sacrificial layer in the insulating layer / sacrificial layer alternating stacking structure with a conductive gate layer specifically includes: Removing silicon nitride from the insulating layer / sacrificial layer alternating stacking structure; An adhesion material and a high-K dielectric layer are deposited at the sacrificial layer position in the insulating layer / sacrificial layer alternating stacking structure, and then filled with a conductive material to form the conductive gate layer.

4. The method according to claim 3, characterized in that The conductive material in the conductive gate layer includes at least one of tungsten, cobalt, copper and aluminum.

5. The method according to claim 1, characterized in that The method further comprises: After forming the first through hole and the second through hole, the first mask is removed.

6. The method according to claim 1, characterized in that The method further comprises: After forming the third through hole, the second mask is removed.

7. A three-dimensional memory, characterized in that: The three-dimensional memory is prepared by the preparation method described in any one of claims 1 to 6.

8. The three-dimensional memory according to claim 7, characterized in that: The materials of the top selection gate layer and the plug in the channel structure both include polysilicon.

9. The three-dimensional memory according to claim 8, characterized in that: The material of the top selection gate layer includes doped polysilicon.

10. The three-dimensional memory according to claim 7, characterized in that: The thickness of the top selection gate layer in the top selection gate layer stack structure is greater than the thickness of the conductive gate layer in the conductive gate layer stack structure.

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