Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate including a memory area, wherein a lower metal interconnection structure is formed in the substrate; forming a plurality of resistive memory cell structures and a first dielectric layer covering the sidewalls of the resistive memory cell structures on the substrate in the memory area, wherein the bottom of the resistive memory cell structures is connected to the lower metal interconnection structure; forming an etching barrier layer on the first dielectric layer between adjacent resistive memory cell structures in the memory area; forming a second dielectric layer covering the resistive memory cell structures, the etching barrier layer and the first dielectric layer; etching the second dielectric layer in the memory area to form an interconnection groove with a plurality of resistive memory cell structures and the etching barrier exposed at the bottom; and forming an upper metal interconnection structure in the interconnection groove. The present invention utilizes the etching barrier layer to protect the first dielectric layer located thereunder, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Semiconductor memory is an indispensable component of various electronic equipment systems, and non-volatile memory has the characteristic of being able to save data even when power is off. Therefore, it is widely used in various mobile and portable devices, such as mobile phones, notebooks, and PDAs.

[0003] Resistive random access memory (RRAM) has the advantages of simple preparation process, fast read and write speed, high storage density, non-volatility and good compatibility with traditional silicon integrated circuit processes. Therefore, it has great application potential in the field of semiconductor memory.

[0004] A typical RRAM includes a bottom electrode, a top electrode, and a variable resistance material layer located therebetween, wherein the variable resistance material layer changes between a high resistance state and a low resistance state according to the voltage applied to the variable resistance material layer, thereby opening or blocking the current flow channel, and using this property to store various information. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, including a memory area, wherein a lower metal interconnection structure is formed in the substrate, and the lower metal interconnection structure is exposed on the surface of the substrate; forming a plurality of resistive memory cell structures and a first dielectric layer covering the sidewalls of the resistive memory cell structures on the substrate in the memory area, wherein the bottom of the resistive memory cell structure is connected to the lower metal interconnection structure; forming an etch barrier layer on the first dielectric layer between adjacent resistive memory cell structures in the memory area; forming a second dielectric layer covering the resistive memory cell structure, the etch barrier layer and the first dielectric layer; etching the second dielectric layer in the memory area to form an interconnection groove with the bottom exposing the plurality of resistive memory cell structures and the etch barrier layer; and forming an upper metal interconnection structure connected to the resistive memory cell structure in the interconnection groove.

[0007] Accordingly, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, comprising a memory area, a lower metal interconnection structure formed in the substrate, and the lower metal interconnection structure exposed on the surface of the substrate; a plurality of resistive memory cell structures, located on the substrate in the memory area, and the bottom of the resistive memory cell structure is connected to the lower metal interconnection structure; a first dielectric layer, located on the substrate and covering the sidewalls of the resistive memory cell structure; an etch barrier layer, located on the first dielectric layer between adjacent resistive memory cell structures in the memory area; an upper metal interconnection structure, located on the top of the resistive memory cell structure and on the top of the etch barrier layer between adjacent resistive memory cell structures; and a second dielectric layer, located on the first dielectric layer exposed by the upper metal interconnection structure.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the embodiment of the present invention, an etching barrier layer is formed on the first dielectric layer between adjacent resistive memory cell structures in a memory area. Therefore, in the process of subsequently etching the second dielectric layer of the memory area to form an interconnection groove with multiple resistive memory cell structures and the etching barrier layer exposed at the bottom, the etching barrier layer can protect the first dielectric layer located thereunder, and accordingly can reduce the probability that the first dielectric layer between adjacent resistive memory cell structures is mistakenly etched or even the sidewall of the adjacent resistive memory cell structure or the lower metal interconnection structure is exposed at the bottom of the interconnection groove, thereby reducing the probability that the upper metal interconnection structure and the lower metal interconnection structure are short-circuited, or the upper metal interconnection structure contacts the sidewall of the adjacent resistive memory cell structure, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 3 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figures 4 to 9 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0012] At present, the performance of semiconductor structures is not good. Now, combined with a method for forming a semiconductor structure, the reasons for the poor performance of the semiconductor structure are analyzed.

[0013] Figures 1 to 3 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1, providing a substrate (not shown), including a memory area 10b and a non-memory area 10a, wherein a lower metal interconnection structure 11 is formed in the substrate, and the lower metal interconnection structure 11 is exposed on the surface of the substrate.

[0015] Specifically, the substrate includes a lower dielectric layer 10 , and the lower metal interconnection structure 11 is located in the lower dielectric layer 10 of the memory area 10 b and the non-memory area 10 a .

[0016] Continue to refer Figure 1 A plurality of resistive memory cell structures 30 and an upper dielectric layer 20 covering the sidewalls of the resistive memory cell structures 30 are formed on the substrate of the memory area 10 b , and the bottom of the resistive memory cell structures 30 is connected to the lower metal interconnection structure 11 .

[0017] The upper dielectric layer 20 includes a first sub-dielectric layer 21 and a second sub-dielectric layer 22 located on the first sub-dielectric layer 21 .

[0018] The resistive memory cell structure 30 includes a bottom electrode layer 31, a resistive material layer 32 and a top electrode layer 33 stacked in sequence from bottom to top, and in the formation process of the semiconductor structure, a groove is first formed in the first sub-dielectric layer 21, and the groove is filled to form the bottom electrode layer 31, and then a stacked resistive material layer 32 and a top electrode layer 33 are formed on the bottom electrode layer 31, and then a second sub-dielectric layer 22 covering the top electrode layer 33, the resistive material layer 32 and the first sub-dielectric layer 21 is formed.

[0019] refer to Figure 2 , the upper dielectric layer 20 of the memory area 10b is etched to form an interconnection groove 42 with the bottom exposing multiple resistive memory cell structures 30 and the remaining upper dielectric layer 20 located between adjacent resistive memory cell structures 30; the upper dielectric layer 20 of the non-memory area 10a is etched to form an interconnection opening 41 with the bottom exposing the lower metal interconnection structure 11.

[0020] refer to Figure 3 , forming an upper metal interconnection structure 50 filled in the interconnection groove 42 and the interconnection opening 41.

[0021] In order to ensure that the interconnection groove 42 can expose the top surface of the corresponding resistive memory cell structure 30, in the process of etching the upper dielectric layer 20, after the main etching is completed, an over-etch is usually performed. In the process of over-etching, the remaining upper dielectric layer 20 between the adjacent resistive memory cell structures 30 is easily etched by mistake, thereby easily causing the remaining upper dielectric layer 20 between the adjacent resistive memory cell structures 30 to be concave (such as Figure 2 (shown by the dotted circle in the middle).

[0022] When the problem of mis-etching is serious, it is easy to cause the interconnection groove 42 to expose the side wall of the adjacent resistive memory cell structure 30, or even expose the underlying metal interconnection structure 11. Correspondingly, the upper metal interconnection structure 50 filled in the interconnection groove 42 will also be recessed, thereby causing a short circuit between the resistive memory cell structures 30, or a short circuit between the upper metal interconnection structure 50 and the underlying metal interconnection structure 11, thereby causing the performance of the semiconductor structure to deteriorate.

[0023] In particular, the second sub-dielectric layer 22 is formed after the top electrode layer 33 and the resistive material layer 32 are formed. The top electrode layer 33 and the resistive material layer 32 have a certain thickness. When the spacing between adjacent resistive memory cell structures 30 is small, it is easy to cause the material of the second sub-dielectric layer 22 to have a reduced gap filling ability between adjacent resistive memory cell structures 30, thereby easily causing void defects to appear in the second sub-dielectric layer 22 between adjacent resistive memory cell structures 30. The presence of void defects will increase the probability that the interconnection groove 42 exposes the side wall of the adjacent resistive memory cell structure 30 or the underlying metal interconnection structure 11.

[0024] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, including a memory area, wherein a lower metal interconnection structure is formed in the substrate, and the lower metal interconnection structure is exposed on the surface of the substrate; forming a plurality of resistive memory cell structures and a first dielectric layer covering the side walls of the resistive memory cell structures on the substrate in the memory area, wherein the bottom of the resistive memory cell structure is connected to the lower metal interconnection structure; in the memory area, forming an etch barrier layer on the first dielectric layer between adjacent resistive memory cell structures; forming a second dielectric layer covering the resistive memory cell structure, the etch barrier layer and the first dielectric layer; etching the second dielectric layer in the memory area to form an interconnection groove with the bottom exposing the plurality of resistive memory cell structures and the etch barrier layer; and forming an upper metal interconnection structure connected to the resistive memory cell structure in the interconnection groove.

[0025] In the embodiment of the present invention, during the process of etching the second dielectric layer of the memory area to form an interconnection groove with multiple resistive memory cell structures and an etching barrier layer exposed at the bottom, the etching barrier layer can protect the first dielectric layer located thereunder, and accordingly can reduce the probability of the first dielectric layer between adjacent resistive memory cell structures being mistakenly etched or even the sidewalls of adjacent resistive memory cell structures or the underlying metal interconnection structure being exposed at the bottom of the interconnection groove, thereby reducing the probability of short circuit between the upper metal interconnection structure and the lower metal interconnection structure, or contact between the upper metal interconnection structure and the sidewalls of the adjacent resistive memory cell structure, thereby improving the performance of the semiconductor structure.

[0026] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] Figures 4 to 9 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0028] refer to Figure 4 , providing a substrate (not shown), including a memory area 100b, wherein a lower metal interconnection structure 110 is formed in the substrate, and the lower metal interconnection structure 110 is exposed on the surface of the substrate.

[0029] The substrate provides a process operation basis for subsequent processes.

[0030] According to actual process conditions, the base includes a substrate and a functional structure formed on the substrate. For example, the functional structure may include semiconductor devices such as MOS field effect transistors, resistor structures, and the like.

[0031] In this embodiment, the substrate includes a lower dielectric layer 100, and the lower metal interconnection structure 110 is located in the lower dielectric layer 100. As an example, the top surface of the lower dielectric layer 100 is flush with the top surface of the lower metal interconnection structure 110.

[0032] In this embodiment, the lower dielectric layer 100 is an intermetal dielectric (IMD) layer, and the lower dielectric layer 100 is used to achieve electrical isolation between lower metal interconnect structures 110 .

[0033] The material of the lower dielectric layer 100 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), silicon oxide, silicon nitride or silicon oxynitride, etc. In this embodiment, the material of the lower dielectric layer 100 is an ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the back-end metal interconnect structures, thereby reducing the back-end RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0034] In this embodiment, the lower metal interconnection structure 110 is a metal interconnection line in a back-end process. Specifically, the lower metal interconnection structure 110 is a second metal interconnection line (ie, M2layer).

[0035] In this embodiment, the material of the lower metal interconnect structure 110 is Cu. Cu has a low resistivity, which is beneficial to reducing the RC delay (resistance-capacitance delay) of the device, and Cu has excellent anti-electromigration capability. In other embodiments, the material of the lower metal interconnect structure can also be Al or W.

[0036] In this embodiment, the substrate includes a memory area 100b, and the memory area 100b is used to form a RRAM device. Subsequently, a resistive memory cell structure is formed on the lower metal interconnect structure 110 of the memory area 100b, so that the formation process of the RRAM device is compatible with the back-end process.

[0037] Therefore, in this embodiment, the substrate further includes a non-memory area 100a, and the non-memory area 100a is used to form other semiconductor devices besides the RRAM device, and the semiconductor device includes a MOS device. For example, the non-memory area 100a is a logic device area. The formation process of the RRAM device is compatible with the formation process of the traditional semiconductor device.

[0038] Continue to refer Figure 4 A plurality of resistive memory cell structures 300 and a first dielectric layer 220 covering the sidewalls of the resistive memory cell structures 300 are formed on a substrate (not shown) of the memory area 100b, and the bottom of the resistive memory cell structure 300 is connected to the underlying metal interconnect structure 110.

[0039] The resistive memory cell structure 300 is used to form a RRAM cell device.

[0040] Therefore, in this embodiment, the resistive memory cell structure 300 includes a bottom electrode layer 310 , a resistive material layer 320 , and a top electrode layer 330 stacked in sequence from bottom to top.

[0041] The bottom electrode layer 310 serves as the bottom electrode in the RRAM cell device. The material of the bottom electrode layer 310 includes one or more of TiN, TaN, Pt, AlCu, Au, Ti, Ta, W, WN and Cu. As an example, the material of the bottom electrode layer 310 is TiN. In other embodiments, the material of the bottom electrode layer is TaN.

[0042] The top electrode layer 330 is used as the top electrode in the RRAM cell device. As an example, the material of the top electrode layer 330 is TiN. For the specific description of the material of the top electrode layer 330, reference may be made to the corresponding description of the bottom electrode layer 310, which will not be repeated here.

[0043] According to the different voltages applied to the variable resistance material layer 320, the variable resistance material layer 320 changes between the high resistance state and the low resistance state, thereby opening or blocking the current flow channel, and using this property to store various information. In this embodiment, the variable resistance material layer 320 is a metal oxide layer. Specifically, the material of the variable resistance material layer 320 includes one or more of hafnium oxide, tantalum oxide and titanium oxide.

[0044] In this embodiment, according to device design requirements, the projection of the bottom electrode layer 310 on the substrate is located within the projection of the variable resistance material layer 320 on the substrate, and the projection of the variable resistance material layer 320 on the substrate coincides with the projection of the top electrode layer 330 on the substrate.

[0045] As an example, the plurality of resistive memory cell structures 300 are arranged in a matrix to form a memory array.

[0046] The first dielectric layer 220 is used to achieve electrical isolation between the resistive memory cell structures 300. The description of the first dielectric layer 220 can be combined with the corresponding description of the lower dielectric layer 100, which will not be repeated here.

[0047] In this embodiment, the resistive memory cell structure 300 is a stacked structure. In order to reduce the process difficulty of forming the resistive memory cell structure 300 , the first dielectric layer 220 is formed after the resistive memory cell structure 300 is formed.

[0048] Specifically, the steps of forming the resistive memory cell structure 300 include: forming a third dielectric layer 210 on a substrate; forming a groove (not shown) in the third dielectric layer 210 to expose the top of the underlying metal interconnect structure 110; forming the bottom electrode layer 310 in the groove; forming a stacked resistive material layer 320 and a top electrode layer 330 on the bottom electrode layer 310, and the stacked top electrode layer 330, the resistive material layer 320 and the bottom electrode layer 310 constitute the resistive memory cell structure 300.

[0049] Since the projection of the bottom electrode layer 310 on the substrate is within the projection of the resistive material layer 320 on the substrate, first forming the bottom electrode layer 310 in the third dielectric layer 210 is beneficial to reducing the process complexity of forming the resistive memory cell structure 300 .

[0050] The third dielectric layer 210 is used to provide a process basis for forming the bottom electrode layer 310 and to achieve electrical isolation between the bottom electrode layers 310. The description of the third dielectric layer 210 can be combined with the corresponding description of the lower dielectric layer 100, which will not be repeated here.

[0051] Therefore, in this embodiment, after the resistive memory cell structure 300 is formed, a first dielectric layer 220 is formed on the third dielectric layer 210 where the resistive material layer 320 and the top electrode layer 330 are exposed.

[0052] As an example, the first dielectric layer 220 is formed by a deposition process and a planarization process (e.g., a chemical mechanical polishing process) performed successively, and during the planarization process, the top surface of the top electrode layer 330 is used as a stopping position, so that the top surfaces of the top electrode layer 330 and the first dielectric layer 220 are flush.

[0053] In this embodiment, the third dielectric layer 210 and the first dielectric layer 220 constitute a dielectric stack 200 .

[0054] In other embodiments, when the projection of the bottom electrode layer on the substrate coincides with the projection of the resistive material layer on the substrate, or the projection of the resistive material layer on the substrate is located within the projection of the bottom electrode layer on the substrate, the first dielectric layer may be formed on the substrate where the resistive memory cell structure is exposed after forming the resistive memory cell structure of the stacked structure. Accordingly, there is no need to form the third dielectric layer.

[0055] In this embodiment, the dielectric stack 200 also covers the substrate of the non-memory area 100a. The dielectric stack 200 of the non-memory area 100a is used to provide a process basis for the subsequent formation of an upper metal interconnect structure electrically connected to the lower metal interconnect structure 110, and is used to achieve electrical isolation between the upper metal interconnect structures of the non-memory area 100a.

[0056] Combined with reference Figure 5 and Figure 6 In the memory area 100b, an etching stop layer 350 (eg, Figure 6 shown).

[0057] Subsequently, a second dielectric layer covering the resistive memory cell structure 300, the etching barrier layer 350 and the first dielectric layer 220 will be formed, and the second dielectric layer of the memory area 100b will be etched to form an interconnection groove with multiple resistive memory cell structures 300 and the etching barrier layer 350 exposed at the bottom, and the interconnection groove is used to provide a spatial position for the formation of an upper metal interconnection structure. In the present embodiment, in the process of forming the interconnection groove, the etching barrier layer 350 can protect the first dielectric layer 220 located thereunder, and accordingly can reduce the probability of the first dielectric layer 220 between adjacent resistive memory cell structures 300 being mistakenly etched, or even the probability of the sidewall of the adjacent resistive memory cell structure 300 or the underlying metal interconnection structure 110 being exposed at the bottom of the interconnection groove, thereby reducing the probability of a short circuit between the upper metal interconnection structure and the lower metal interconnection structure 110, or reducing the probability of the upper metal interconnection structure contacting the sidewall of the adjacent resistive memory cell structure 300, thereby reducing the probability of a short circuit between adjacent resistive memory cell structures 300, and thereby improving the performance of the semiconductor structure.

[0058] Specifically, the steps of forming the etching stop layer 350 include: Figure 5 As shown, an etching stop material layer 340 covering the first dielectric layer 220 and the resistive memory cell structure 300 is formed; as shown Figure 6 As shown, the etch barrier material layer 340 is etched to expose the top of the resistive memory cell structure 300 , and the remaining etch barrier material layer 340 in the memory area 100 b serves as an etch barrier layer 350 .

[0059] According to the material of the etch stop layer 350, the etch stop material layer 340 may be formed by chemical vapor deposition or atomic layer deposition, wherein the chemical vapor deposition process has a lower process cost, and the atomic layer deposition process has a better film quality.

[0060] In this embodiment, during the process of etching the etch stop material layer 340 , the etch stop material layer 340 in the non-memory area 100 a is also removed to expose the first dielectric layer 220 in the non-memory area 100 a .

[0061] In this embodiment, the etching stop material layer 340 is etched using an anisotropic dry etching process.

[0062] The anisotropic dry etching process has anisotropic etching characteristics, which is conducive to accurately controlling the formation position of the etch barrier layer 350, correspondingly reducing the possibility of the first dielectric layer 220 between adjacent resistive memory cell structures 300 being exposed, and is conducive to ensuring that the etch barrier layer 350 can expose the top of the resistive memory cell structure 300.

[0063] Moreover, the dry etching process has high process controllability, which is beneficial to reducing the probability of damage to the resistive memory cell structure 300 and the first dielectric layer 220 in the non-memory area 100 a.

[0064] Therefore, the etching selectivity between the etch barrier layer 350 and the resistive memory cell structure 300 is relatively large, and the etching selectivity between the etch barrier layer 350 and the first dielectric layer 220 is relatively large, thereby reducing the probability of damage to the resistive memory cell structure 300 and the first dielectric layer 220 during the process of etching the etch barrier material layer 340 to form the etch barrier layer 350.

[0065] In this embodiment, the etching selectivity ratio between the etching stop layer 350 and the resistive memory cell structure 300 is greater than 2, and the etching selectivity ratio between the etching stop layer and the first dielectric layer 220 is greater than 5.

[0066] In this embodiment, the material of the top electrode layer 330 includes metal, so the process of etching the etching barrier material layer 340 causes less damage to the top electrode layer 330 .

[0067] In this embodiment, during the etching of the etch stop material layer 340 , the etching selectivity between the etch stop layer and the first dielectric layer 220 is relatively large, thereby significantly reducing the probability of damage to the first dielectric layer 220 .

[0068] Similarly, in the subsequent etching process of the second dielectric layer of the memory area 100b, in order to enable the etch stop layer 350 to protect the first dielectric layer 220 located thereunder, the etch selectivity ratio between the second dielectric layer and the etch stop layer 350 is also large. In this embodiment, the etch selectivity ratio between the second dielectric layer and the etch stop layer 350 is greater than 5.

[0069] To this end, in this embodiment, the material of the etch stop layer 350 includes one or more of tetraethyl orthosilicate (TEOS), silicon carbide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon oxide.

[0070] As an example, the material of the etch stop layer 350 is TEOS. TEOS is a commonly used material in the back-end process and has high process compatibility. Accordingly, the etch stop material layer 340 is formed by a chemical vapor deposition process.

[0071] It should be noted that the thickness of the etching stop layer 350 should not be too small or too large. If the thickness of the etching stop layer 350 is too small, in the subsequent process of forming the interconnection groove, it is easy to expose the first dielectric layer 220 due to the etching stop layer 350 being mistakenly etched, resulting in the poor protection of the first dielectric layer 220 located thereunder by the etching stop layer 350. The first dielectric layer 220 may still be mistakenly etched, which leads to poor effect in reducing the probability of short circuit between the upper metal interconnection structure and the lower metal interconnection structure 110 or short circuit between adjacent resistive memory cell structures 300; if the thickness of the etching stop layer 350 is too large, the first dielectric layer 220 may be exposed due to the etching stop layer 350 being mistakenly etched. The thickness of the etching barrier material layer 340 is too large, which not only leads to an increase in process cost, but also increases the process difficulty of etching the blocking material layer 340. Moreover, when the second dielectric layer is subsequently formed, it is easy to cause the gap filling ability of the material of the second dielectric layer between adjacent etching barrier layers 350 to decrease, thereby easily forming hole defects in the second dielectric layer. In addition, when the upper metal interconnection structure is subsequently formed in the interconnection groove, if the thickness of the second dielectric layer is constant, it will also cause the thickness of the upper metal interconnection structure located above the etching barrier layer 350 to be too small, thereby easily causing adverse effects on the performance of the upper metal interconnection structure. For this reason, in this embodiment, the thickness of the etching barrier layer 350 is to For example, the thickness of the etching stop layer 350 is or

[0072] refer to Figure 7 , forming a second dielectric layer 230 covering the resistive memory cell structure 300 , the etching stop layer 350 and the first dielectric layer 220 .

[0073] The second dielectric layer 230 is used to provide a process basis for the subsequent formation of an upper metal interconnection structure, and is also used to achieve electrical isolation between upper metal interconnection structures.

[0074] The description of the second dielectric layer 230 may be combined with reference to the corresponding description of the lower dielectric layer 100 , which will not be repeated here.

[0075] In this embodiment, the dielectric stack 200 and the second dielectric layer 230 constitute an upper dielectric layer 240 , that is, the upper dielectric layer 240 includes a third dielectric layer 210 , a first dielectric layer 220 , and a second dielectric layer 230 stacked in sequence from bottom to top.

[0076] refer to Figure 8 , the second dielectric layer 230 of the memory area 100 b is etched to form an interconnection groove 430 with the bottom exposing the multiple resistive memory cell structures 300 and the etching stop layer 350 .

[0077] The interconnection groove 430 is used to provide a space for subsequently forming an upper metal interconnection structure electrically connected to the resistive memory cell structure 300 .

[0078] In this embodiment, the multiple resistive memory cell structures 300 are arranged in a matrix to form a storage array, and the interconnection groove 430 extends along the row direction or column direction of the matrix. Therefore, the interconnection groove 430 spans across the multiple resistive memory cell structures 300, and the interconnection groove 430 correspondingly exposes the etching barrier layer 350 between adjacent resistive memory cell structures 300.

[0079] Moreover, since the etching selectivity between the second dielectric layer 230 and the etching barrier layer 350 is relatively high during the etching of the second dielectric layer 230, the etching rate of the etching barrier layer 350 in the process of etching the second dielectric layer 230 is relatively low. Therefore, the etching barrier layer 350 can protect the first dielectric layer 220 located thereunder. Accordingly, the probability of damage to the first dielectric layer 220 of the memory area 100b is relatively low.

[0080] In this embodiment, an anisotropic dry etching process is used to etch the second dielectric layer 230 of the memory area 100b. The anisotropic dry etching process is used to improve the morphology quality and dimensional accuracy of the interconnection groove 430.

[0081] In this embodiment, the formation method further includes: etching the second dielectric layer 230 , the first dielectric layer 220 and the third dielectric layer 210 of the non-memory area 100 a to form an interconnection opening 400 with the bottom exposing the underlying metal interconnection structure 110 .

[0082] The interconnection opening 400 is used to provide a space for subsequently forming an upper metal interconnection structure in the non-memory area 100 a .

[0083] In this embodiment, the interconnection groove 430 formed in the memory area 100 b is used as the first interconnection groove 430 , and the interconnection opening 400 includes an interconnection through-hole 420 and a second interconnection groove 410 connected to the top of the interconnection through-hole 420 .

[0084] As an example, the interconnection opening 400 is formed by forming a via first, that is, the interconnection via 420 is formed first, and then the second interconnection groove 410 is formed.

[0085] By forming the interconnection through hole 420 first, the first interconnection groove 430 and the second interconnection groove 410 can be formed in the same step, so that the formation process of the RRAM device is compatible with the back-end process of the traditional semiconductor process.

[0086] Specifically, the upper dielectric layer 240 of the non-memory area 100a is first etched to form an interconnection through hole 420 with the bottom exposing the lower metal interconnection structure 110; after the interconnection through hole 420 is formed, a protective layer is filled in the interconnection through hole 420 to protect the lower metal interconnection structure 110 at the bottom of the interconnection through hole 420; after the protective layer is formed, the upper dielectric layer 240 with a partial thickness around the interconnection through hole 420 and the second dielectric layer 230 of the memory area 100b are etched to form a second interconnection groove 410 in the non-memory area 100a and a first interconnection groove 430 in the memory area 100b; and the protective layer is removed.

[0087] refer to Fig. 9 In the interconnection groove 430 (such as Figure 8 An upper metal interconnection structure 500 connected to the resistive memory cell structure 300 is formed.

[0088] The upper metal interconnect structure 500 is used to realize the electrical connection between the resistive memory cell structure 300 and other circuits.

[0089] In this embodiment, the upper metal interconnection structure 500 is a metal interconnection line in a back-end process. Specifically, the upper metal interconnection structure 500 is a third metal interconnection line (ie, M3layer).

[0090] As an example, the upper metal interconnect structure 500 of the memory area 100 b is used as a word line (BL) of a memory array.

[0091] Specifically, after the interconnection groove 430 is filled with a conductive material, the conductive material is planarized to form an upper metal interconnection structure 500 whose top surface is flush with the second dielectric layer 230 .

[0092] In this embodiment, the material of the upper metal interconnection structure 500 is Cu. The specific description of the upper metal interconnection structure 500 can be combined with the corresponding description of the lower metal interconnection structure 110, which will not be repeated here.

[0093] In this embodiment, in the step of forming the upper metal interconnection structure 500 in the interconnection groove 430 , the upper metal interconnection structure 500 is also formed in the interconnection opening 400 .

[0094] Accordingly, the present invention also provides a semiconductor structure. Fig. 9 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0095] The semiconductor structure includes: a substrate (not marked), including a memory area 100b, a lower metal interconnection structure 110 is formed in the substrate, and the lower metal interconnection structure 110 is exposed on the surface of the substrate; a plurality of resistive memory cell structures 300 are located on the substrate in the memory area 100b, and the bottom of the resistive memory cell structure 300 is connected to the lower metal interconnection structure 110; a first dielectric layer 220 is located on the substrate and covers the sidewalls of the resistive memory cell structure 300; an etch barrier layer 350 is located on the first dielectric layer 220 between adjacent resistive memory cell structures 300 in the memory area 100b; an upper metal interconnection structure 500 is located on the top of the resistive memory cell structure 300 and on the top of the etch barrier layer 350 between adjacent resistive memory cell structures 300; and a second dielectric layer 230 is located on the first dielectric layer 220 exposed by the upper metal interconnection structure 500.

[0096] In the process of forming the semiconductor structure, the second dielectric layer 230 of the memory area 100b is first etched to form an interconnection groove with a plurality of resistive memory cell structures 300 and an etching barrier layer 350 exposed at the bottom, and the upper metal interconnection structure 500 is formed in the interconnection groove. In this embodiment, in the process of forming the interconnection groove in the memory area 100b, the etching barrier layer 350 can protect the first dielectric layer 220 located thereunder, and accordingly can reduce the probability of the first dielectric layer 220 between adjacent resistive memory cell structures 300 being mistakenly etched, or even the probability of the sidewall of the adjacent resistive memory cell structure 300 or the lower metal interconnection structure 110 being exposed at the bottom of the interconnection groove, thereby reducing the probability of the upper metal interconnection structure 500 short-circuiting with the lower metal interconnection structure 110, or reducing the probability of the upper metal interconnection structure 500 contacting with the sidewall of the adjacent resistive memory cell structure 300, thereby reducing the probability of the adjacent resistive memory cell structures 300 short-circuiting, thereby improving the performance of the semiconductor structure.

[0097] According to actual process conditions, the base includes a substrate and a functional structure formed on the substrate. For example, the functional structure may include semiconductor devices such as MOS field effect transistors, resistor structures, and the like.

[0098] In this embodiment, the substrate includes a lower dielectric layer 100, and the lower metal interconnection structure 110 is located in the lower dielectric layer 100. As an example, the top surface of the lower dielectric layer 100 is flush with the top surface of the lower metal interconnection structure 110.

[0099] In this embodiment, the lower dielectric layer 100 is an intermetal dielectric (IMD) layer, and the lower dielectric layer 100 is used to achieve electrical isolation between lower metal interconnect structures 110 .

[0100] The material of the lower dielectric layer 100 is a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride or silicon oxynitride, etc. In this embodiment, the material of the lower dielectric layer 100 is an ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the back-end metal interconnection structures, thereby reducing the back-end RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.

[0101] In this embodiment, the lower metal interconnection structure 110 is a metal interconnection line in a back-end process. Specifically, the lower metal interconnection structure 110 is a second metal interconnection line (ie, M2layer).

[0102] In this embodiment, the material of the lower metal interconnection structure 110 is Cu. Cu has a low resistivity, which is beneficial to reducing the RC delay of the device, and Cu has excellent anti-electromigration capability. In other embodiments, the material of the lower metal interconnection structure can also be Al or W.

[0103] In this embodiment, the substrate includes a memory area 100 b , and the memory area 100 b is used to form a RRAM device, so that the formation process of the RRAM device is compatible with the back-end process.

[0104] Therefore, in this embodiment, the substrate further includes a non-memory area 100a, and the non-memory area 100a is used to form other semiconductor devices besides the RRAM device, and the semiconductor device includes a MOS device. For example, the non-memory area 100a is a logic device area. The formation process of the RRAM device is compatible with the formation process of the traditional semiconductor device.

[0105] The resistive memory cell structure 300 is used to form a RRAM cell device.

[0106] Therefore, in this embodiment, the resistive memory cell structure 300 includes a bottom electrode layer 310 , a resistive material layer 320 , and a top electrode layer 330 stacked in sequence from bottom to top.

[0107] The bottom electrode layer 310 serves as the bottom electrode in the RRAM cell device. The material of the bottom electrode layer 310 includes one or more of TiN, TaN, Pt, AlCu, Au, Ti, Ta, W, WN and Cu. As an example, the material of the bottom electrode layer 310 is TiN. In other embodiments, the material of the bottom electrode layer is TaN.

[0108] The top electrode layer 330 is used as the top electrode in the RRAM cell device. As an example, the material of the top electrode layer 330 is TiN. For the specific description of the material of the top electrode layer 330, reference may be made to the corresponding description of the bottom electrode layer 310, which will not be repeated here.

[0109] According to the different voltages applied to the variable resistance material layer 320, the variable resistance material layer 320 changes between the high resistance state and the low resistance state, thereby opening or blocking the current flow channel, and using this property to store various information. In this embodiment, the variable resistance material layer 320 is a metal oxide layer. Specifically, the material of the variable resistance material layer 320 includes one or more of hafnium oxide, tantalum oxide and titanium oxide.

[0110] In this embodiment, according to device design requirements, the projection of the bottom electrode layer 310 on the substrate is located within the projection of the variable resistance material layer 320 on the substrate, and the projection of the variable resistance material layer 320 on the substrate coincides with the projection of the top electrode layer 330 on the substrate.

[0111] As an example, the plurality of resistive memory cell structures 300 are arranged in a matrix to form a memory array.

[0112] The first dielectric layer 220 is used to achieve electrical isolation between the resistive memory cell structures 300. The description of the first dielectric layer 220 can be combined with the corresponding description of the lower dielectric layer 100, which will not be repeated here.

[0113] As an example, the top surface of the top electrode layer 330 is flush with the top surface of the first dielectric layer 220 .

[0114] In this embodiment, the resistive memory cell structure 300 is a stacked structure. In order to reduce the process difficulty of forming the resistive memory cell structure 300, during the formation of the semiconductor structure, the first dielectric layer 220 is formed after the resistive memory cell structure 300 is formed.

[0115] Therefore, the semiconductor structure further includes: a third dielectric layer 210 located on the substrate at the side of the bottom electrode layer 310. During the formation of the semiconductor structure, the bottom electrode layer 310 is formed in the third dielectric layer 210.

[0116] Since the projection of the bottom electrode layer 310 on the substrate is within the projection of the resistive material layer 320 on the substrate, first forming the bottom electrode layer 310 in the third dielectric layer 210 is beneficial to reducing the process complexity of forming the resistive memory cell structure 300 .

[0117] The third dielectric layer 210 is used to provide a process basis for forming the bottom electrode layer 310 and to achieve electrical isolation between the bottom electrode layers 310. The description of the third dielectric layer 210 can be combined with the corresponding description of the lower dielectric layer 100, which will not be repeated here.

[0118] Therefore, in this embodiment, the first dielectric layer 220 is located on the third dielectric layer 210 where the varistor material layer 320 and the top electrode layer 330 are exposed.

[0119] In this embodiment, the third dielectric layer 210 and the first dielectric layer 220 constitute a dielectric stack 200 .

[0120] In other embodiments, when the projection of the bottom electrode layer on the substrate coincides with the projection of the variable resistance material layer on the substrate, or the projection of the variable resistance material layer on the substrate is located within the projection of the bottom electrode layer on the substrate, after forming the resistive memory cell structure of the stacked structure, a first dielectric layer may be formed on the substrate where the resistive memory cell structure is exposed. Accordingly, the semiconductor structure is not provided with a third dielectric layer.

[0121] In this embodiment, the dielectric stack 200 also covers the substrate of the non-memory area 100a. The dielectric stack 200 of the non-memory area 100a is used to achieve electrical isolation between the upper metal interconnection structures 500 of the non-memory area 100a.

[0122] In this embodiment, the etch stop layer 350 is formed by a deposition and etching process of an etch stop material layer. Therefore, the etch stop layer 350 is located on the first dielectric layer 220 exposed by the resistive memory cell structure 300 .

[0123] The etching selectivity between the etch barrier layer 350 and the resistive memory cell structure 300 is relatively large, and the etching selectivity between the etch barrier layer 350 and the first dielectric layer 220 is relatively large, thereby reducing the probability of damage to the resistive memory cell structure 300 and the first dielectric layer 220 during the process of etching the etch barrier material layer to form the etch barrier layer 350.

[0124] In this embodiment, the etching selectivity ratio between the etching stop layer 350 and the resistive memory cell structure 300 is greater than 2, and the etching selectivity ratio between the etching stop layer and the first dielectric layer 220 is greater than 5.

[0125] Similarly, in the process of etching the second dielectric layer 230 of the memory area 100b, in order to enable the etch stop layer 350 to protect the first dielectric layer 220 located thereunder, the etch selectivity ratio between the second dielectric layer 230 and the etch stop layer 350 is also relatively large. In this embodiment, the etch selectivity ratio between the second dielectric layer 230 and the etch stop layer 350 is greater than 5.

[0126] To this end, in this embodiment, the material of the etch stop layer 350 includes one or more of tetraethyl orthosilicate (TEOS), silicon carbide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon oxide. As an example, the material of the etch stop layer 350 is TEOS. TEOS is a commonly used material in the back-end process and has high process compatibility.

[0127] It should be noted that the thickness of the etching stop layer 350 should not be too small or too large. If the thickness of the etching stop layer 350 is too small, in the process of etching the second dielectric layer 230 of the memory area 100b to form the interconnection groove, it is easy for the etching stop layer 350 to be mistakenly etched and the first dielectric layer 220 to be exposed, resulting in the poor protection of the etching stop layer 350 on the first dielectric layer 220 located thereunder, and the first dielectric layer 220 may still be mistakenly etched, thereby resulting in poor effect in reducing the probability of short circuit between the upper metal interconnect structure 500 and the lower metal interconnect structure 110 or short circuit between adjacent resistive memory cell structures 300; if If the thickness of the etching stop layer 350 is too large, it will not only increase the process cost, but also increase the process difficulty of etching the stop material layer. Moreover, when forming the second dielectric layer 230, it is easy to cause the gap filling ability of the material of the second dielectric layer 230 between adjacent etching stop layers 350 to decrease, so that it is easy to form hole defects in the second dielectric layer 230. In addition, when the thickness of the second dielectric layer 230 is constant, it will also cause the thickness of the upper metal interconnection structure 500 located above the etching stop layer 350 to be too small, which is easy to cause adverse effects on the performance of the upper metal interconnection structure 500. For this reason, in this embodiment, the thickness of the etching stop layer 350 is to For example, the thickness of the etching stop layer 350 is or

[0128] The upper metal interconnect structure 500 is used to realize the electrical connection between the resistive memory cell structure 300 and other circuits.

[0129] In this embodiment, the upper metal interconnection structure 500 is a metal interconnection line in a back-end process. Specifically, the upper metal interconnection structure 500 is a third metal interconnection line (ie, M3layer).

[0130] As an example, the upper metal interconnect structure 500 of the memory area 100 b is used as a word line (BL) of a memory array.

[0131] In this embodiment, the material of the upper metal interconnection structure 500 is Cu. The specific description of the upper metal interconnection structure 500 can be combined with the corresponding description of the lower metal interconnection structure 110, which will not be repeated here.

[0132] In this embodiment, the multiple resistive memory cell structures 300 are arranged in a matrix to form a memory array, and the upper metal interconnection structure 500 of the memory area 100b extends along the row direction or the column direction of the matrix. Therefore, the upper metal interconnection structure 500 of the memory area 100b spans across the multiple resistive memory cell structures 300, and the upper metal interconnection structure 500 is also located on the top of the etching barrier layer 250 between adjacent resistive memory cell structures 300.

[0133] In this embodiment, the upper metal interconnect structure 500 also penetrates the first dielectric layer 220 and the third dielectric layer 210 of the non-memory area 100 a , and the bottom is connected to the lower metal interconnect structure 110 of the non-memory area 100 a .

[0134] Specifically, the top surfaces of the upper metal interconnection structures 500 of the non-memory region 100 a and the memory region 100 b are flush with each other.

[0135] The second dielectric layer 230 is used to achieve electrical isolation between upper metal interconnect structures 500 .

[0136] The description of the second dielectric layer 230 may be combined with reference to the corresponding description of the lower dielectric layer 100 , which will not be repeated here.

[0137] In this embodiment, the dielectric stack 200 and the second dielectric layer 230 constitute an upper dielectric layer 240 , that is, the upper dielectric layer 240 includes a third dielectric layer 210 , a first dielectric layer 220 , and a second dielectric layer 230 stacked in sequence from bottom to top.

[0138] The semiconductor structure described in this embodiment can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0139] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, including a memory area, wherein a lower metal interconnection structure is formed in the substrate, and the lower metal interconnection structure is exposed on a surface of the substrate; Forming a plurality of resistive memory cell structures on the substrate of the memory area, and a first dielectric layer covering the sidewalls of the resistive memory cell structures, wherein the bottom of the resistive memory cell structures is connected to the underlying metal interconnection structure, and the top of the first dielectric layer is flush with the top of the resistive memory cell structures; In the memory area, an etch stop layer is formed on the first dielectric layer between adjacent resistive memory cell structures, wherein the etch stop layer exposes the top of the resistive memory cell structure; forming a second dielectric layer covering the resistive memory cell structure, the etching stop layer and the first dielectric layer; Etching the second dielectric layer of the memory area to form interconnection grooves with the bottom exposing the multiple resistive memory cell structures and the etching stop layer; An upper metal interconnection structure connected to the resistive memory cell structure is formed in the interconnection groove, and the upper metal interconnection structure fills the space at the side of the etching stop layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the etching stop layer includes: forming an etching stop material layer covering the first dielectric layer and the resistive memory cell structure; The etch barrier material layer is etched to expose the top of the resistive memory cell structure, and the remaining etch barrier material layer in the memory area serves as an etch barrier layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The etching selectivity ratio between the etching barrier layer and the resistive memory cell structure is greater than 2; The etching selectivity ratio between the etching stop layer and the first dielectric layer is greater than 5; The etching selectivity ratio between the second dielectric layer and the etching stop layer is greater than 5.

4. The method for forming a semiconductor structure according to claim 1, wherein: The material of the etching stop layer includes one or more of tetraethyl orthosilicate, silicon carbide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon oxide.

5. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the etching stop layer is to 6. The method for forming a semiconductor structure according to claim 1, wherein: The etching stop layer is formed by using a chemical vapor deposition process or an atomic layer deposition process.

7. The method for forming a semiconductor structure according to claim 2, wherein: The etching stop material layer is etched by adopting an anisotropic dry etching process.

8. The method for forming a semiconductor structure according to claim 1, wherein: After forming the resistive memory cell structure, the first dielectric layer is formed.

9. The method for forming a semiconductor structure according to claim 8, wherein: The steps of forming the resistive memory cell structure include: forming a third dielectric layer on the substrate; forming a trench in the third dielectric layer to expose a top portion of the underlying metal interconnect structure; forming a bottom electrode layer in the trench; Forming a stacked resistance material layer and a top electrode layer on the bottom electrode layer, wherein the stacked top electrode layer, the resistance material layer and the bottom electrode layer constitute a resistive memory cell structure; In the step of forming the first dielectric layer, the first dielectric layer is located on the third dielectric layer where the resistance material layer and the top electrode layer are exposed.

10. The method for forming a semiconductor structure according to claim 1, wherein: The substrate also includes a non-memory region; The formation method further comprises: etching the second dielectric layer and the first dielectric layer of the non-memory area to form an interconnect opening with the bottom exposing the underlying metal interconnect structure; In the step of forming an upper metal interconnection structure in the interconnection groove, the upper metal interconnection structure is also formed in the interconnection opening.

11. A semiconductor structure, characterized in that: include: A substrate, including a memory area, wherein a lower metal interconnection structure is formed in the substrate, and the lower metal interconnection structure is exposed on a surface of the substrate; A plurality of resistive memory cell structures are located on the substrate of the memory area, and the bottom of the resistive memory cell structure is connected to the underlying metal interconnect structure; A first dielectric layer, located on the substrate and covering the sidewalls of the resistive memory unit structure, wherein the top of the first dielectric layer is flush with the top of the resistive memory unit structure; An etch stop layer, located on the first dielectric layer between adjacent resistive memory cell structures in the memory area, wherein the etch stop layer exposes the top of the resistive memory cell structure; An upper metal interconnect structure is located on the top of the resistive memory cell structure and on the top of the etching barrier layer between adjacent resistive memory cell structures, and the upper metal interconnect structure fills the space on the side of the etching barrier layer; The second dielectric layer is located on the first dielectric layer exposed by the upper metal interconnection structure.

12. The semiconductor structure according to claim 11, wherein: The etching selectivity ratio between the etching barrier layer and the resistive memory cell structure is greater than 2; The etching selectivity ratio between the etching stop layer and the first dielectric layer is greater than 5; The etching selectivity ratio between the second dielectric layer and the etching stop layer is greater than 5.

13. The semiconductor structure according to claim 11, wherein: The material of the etching stop layer includes one or more of tetraethyl orthosilicate, silicon carbide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon oxide.

14. The semiconductor structure according to claim 11, wherein: The thickness of the etching stop layer is to 15. The semiconductor structure according to claim 11, wherein: The resistive memory cell structure comprises a bottom electrode layer, a resistive material layer and a top electrode layer stacked in sequence from bottom to top; The semiconductor structure further includes: a third dielectric layer located on the substrate at the side of the bottom electrode layer; and the first dielectric layer is located on the third dielectric layer exposed by the variable resistance material layer and the top electrode layer.

16. The semiconductor structure according to claim 11, wherein: The substrate also includes a non-memory region; The upper metal interconnection structure also penetrates the first dielectric layer of the non-memory area, and the bottom is connected to the lower metal interconnection structure of the non-memory area.

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