Semiconductor structure

Abstract

A semiconductor structure includes a memory cell stack and a complementary metal oxide semiconductor structure. The complementary metal oxide semiconductor structure is located below the memory cell stack and includes a source line transistor and a bit line transistor.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor storage technology, relates to a semiconductor structure, and particularly to a three-dimensional semiconductor structure. Background Art

[0002] With the development of semiconductor technology, various semiconductor components are constantly being innovated. Semiconductor components can realize various electrical functions after being properly arranged. Nowadays, various electronic products have been widely used in various semiconductor components.

[0003] As electronic products pursue the trend of "light, thin, short and small", how to reduce the size of semiconductor components and improve the chip performance of semiconductor components has become an important research and development direction of the semiconductor industry. Summary of the invention

[0004] The present invention relates to a semiconductor structure. By arranging a complementary metal oxide semiconductor structure (including a ladder decoder) under a memory cell stack, the size of the memory device can be effectively reduced, and the manufacturing cost can be further reduced, thereby improving chip performance. Furthermore, by arranging local bit lines and local source lines alternately and connecting them to bit line transistors and source line transistors respectively, the RC delay time of the local bit lines and the local source lines can be effectively reduced.

[0005] According to one aspect of the present invention, a semiconductor structure is provided. The semiconductor structure includes a memory cell stack and a complementary metal oxide semiconductor structure. The complementary metal oxide semiconductor structure is located below the memory cell stack and includes a source line transistor and a bit line transistor.

[0006] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A A partial top view of a semiconductor structure according to a first embodiment of the present invention is shown;

[0008] Figure 1B Draw Figure 1A A three-dimensional schematic diagram of a semiconductor structure;

[0009] Figure 1C Draw Figure 1A A layout view of a staircase decoder and a memory cell stack of a semiconductor structure;

[0010] Figure 2A A partial top view of a semiconductor structure according to a second embodiment of the present invention is shown;

[0011] Figure 2B Draw Figure 2A A local magnified view of a semiconductor structure;

[0012] Figure 2C Draw Figure 2A A three-dimensional schematic diagram of a semiconductor structure;

[0013] Figure 3 A layout diagram of local bit lines, local source lines, global bit lines and global source lines of a semiconductor structure according to a third embodiment of the present invention is shown;

[0014] Figure 4 A layout diagram of local bit lines, local source lines, global bit lines and global source lines of a semiconductor structure according to a fourth embodiment of the present invention is shown;

[0015] Figure 5 A layout diagram of local bit lines, local source lines, and global bit lines of a semiconductor structure according to a fifth embodiment of the present invention is shown.

[0016]

Explanation of symbols

[0017] 10, 20, 30, 40, 50: semiconductor structure

[0018] 100: Ladder decoder

[0019] 110: Local drive

[0020] 120: Level Shifter

[0021] 130: Other circuits

[0022] 200: Source line transistor

[0023] 300: Bit line transistor

[0024] 400: Staircase area

[0025] 500, 500_1, 500_2...~500_K-1, 500_K: Memory cell stack

[0026] 600: Insulation laminate

[0027] 700: Overall position line

[0028] 800: Overall source line

[0029] 910: First column element

[0030] 920: Second column element

[0031] 930: Third column element

[0032] 940: Fourth column element

[0033] 1000: Sense amplifier

[0034] 1100: Through hole

[0035] 1200: First metal layer

[0036] 1300: Second metal layer

[0037] 1400: Local bit line

[0038] 1500: Local source line

[0039] 1600: Storage unit

[0040] WL0, WL1, ... WL j-1 , W.L. j : Word line DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0042] In the detailed description below, various specific details are provided to provide an overall understanding of the embodiments of the present disclosure for ease of explanation. However, it should be understood that one or more embodiments can be implemented without adopting these specific details. In other cases, in order to simplify the drawings, known structures and elements are represented by schematic diagrams.

[0043] In addition, the ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., to modify the elements of the claims, do not themselves mean or represent any previous ordinal number of the element, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name.

[0044] <First Embodiment>

[0045] Figure 1A A partial top view of a semiconductor structure 10 according to a first embodiment of the present invention is shown. Figure 1B Draw Figure 1A A three-dimensional schematic diagram of a semiconductor structure 10 is shown.

[0046] Please also refer to Figure 1A and Figure 1B The semiconductor structure 10 includes a complementary metal oxide semiconductor structure (including a source line transistor 200 , a bit line transistor 300 and a ladder decoder 100 ), a memory cell stack 500 and an insulating stack 600 .

[0047] In one embodiment, the CMOS structure is located below the memory cell stack 500. The memory cell stack 500 overlaps a portion of the CMOS structure in the longitudinal direction (eg, Z direction) and is offset from another portion of the CMOS structure.

[0048] In one embodiment, the source line transistor 200 and the bit line transistor 300 are disposed on opposite sides of the memory cell stack 500. In other words, in the longitudinal direction (e.g., the Z direction), the memory cell stack 500 does not overlap the source line transistor 200 and the bit line transistor 300. The source line transistor 200 and the bit line transistor 300 may extend along the X direction. For example, the source line transistor 200 and the bit line transistor 300 may be back-to-back MOSFET transistors, but the present invention is not limited thereto.

[0049] In one embodiment, the ladder decoder 100 is located below the memory cell stack 500. In other words, in the longitudinal direction (e.g., the Z direction), the ladder decoder 100 at least partially overlaps the memory cell stack 500. Generally speaking, the ladder decoder 100 occupies a larger space than other components in the complementary metal oxide semiconductor structure. Therefore, by arranging the ladder decoder 100 below the memory cell stack 500, it will be beneficial to manufacture a semiconductor structure 10 of small size. In addition, the memory cell stack 500 may include a plurality of array blocks, and the plurality of array blocks may form an array tile, and each array tile may have a ladder decoder 100 arranged below and may independently operate and control each array block. Since each array block is a smaller unit, it has a light resistance and capacitance delay time, so it can be operated at a high speed.

[0050] Compared to the comparative example in which the complementary metal oxide semiconductor structure is located in the peripheral area of ​​the memory cell stack rather than under the memory cell stack, in the semiconductor structure 10 of the present invention, the complementary metal oxide semiconductor structure is arranged under the memory cell stack 500, so it can effectively reduce the size of the memory device, further reduce the manufacturing cost, and thus improve the chip performance.

[0051] In one embodiment, the insulating stack 600 is located above the source line transistor 200 and the bit line transistor 300. In other words, in the longitudinal direction (eg, the Z direction), the source line transistor 200 and the bit line transistor 300 at least partially overlap the insulating stack 600.

[0052] In one embodiment, the memory cell stack 500 may include alternating conductive layers and insulating layers. The memory cell stack 500 is, for example, a 3D-AND type memory array, but the present invention is not limited thereto.

[0053] In one embodiment, the memory cell stack 500 includes a staircase region 400. In the longitudinal direction (eg, the Z direction), the staircase decoder 100 at least partially overlaps the staircase region 400.

[0054] Please refer to Figure 1B The semiconductor structure 10 may further include a global bit line 700, a global source line (also referred to as a common source line) 800, a first column element 910, a second column element 920, a third column element 930, a fourth column element 940, a local bit line 1400 and a local source line 1500.

[0055] In one embodiment, the insulating stack 600 is adjacent to the memory cell stack 500. The memory cell stack 500 and the insulating stack 600 may be arranged alternately, but the present invention is not limited thereto. For example, the memory cell stack 500 and the insulating stack 600 may be arranged along the Y direction.

[0056] In one embodiment, the insulating layer stack 600 may include two dielectric layers alternately stacked, such as an oxide layer and a nitride layer. For example, the insulating layer stack 600 may include alternately stacked silicon dioxide (SiO2) layers and silicon nitride (Si3N4) layers, but the present invention is not limited thereto.

[0057] In one embodiment, the local bit lines 1400 and the local source lines 1500 are located above the memory cell stack 500 and the insulating stack 600, and are electrically connected to the source or drain of the memory cell string in the memory cell stack 500, respectively. The extension direction of the local bit lines 1400 and the local source lines 1500 may be parallel to the extension direction of the memory cell stack 500 and the insulating stack 600. The local bit lines 1400 and the local source lines 1500 extend along the Y direction. For example, the local bit lines 1400 and the local source lines 1500 may be arranged alternately, but the present invention is not limited thereto. The local bit lines 1400 and the local source lines 1500 may include suitable conductive materials, such as copper (Cu) or tungsten (W).

[0058] In one embodiment, the global bit line 700 and the global source line 800 are located above the memory cell stack 500 and the insulation stack 600. For example, the global bit line 700 and the global source line 800 may be located above the local bit line 1400 and the local source line 1500. The extension direction of the global bit line 700 and the global source line 800 may be parallel to the extension direction of the memory cell stack 500 and the insulation stack 600. The global bit line 700 and the global source line 800 extend along the Y direction. The global bit line 700 and the global source line 800 may include a suitable conductive material, such as an aluminum copper alloy (AlCu alloy).

[0059] In one embodiment, the first column element 910, the second column element 920, the third column element 930 and the fourth column element 940 pass through the insulating stack 600. The first column element 910, the second column element 920, the third column element 930 and the fourth column element 940 extend in a longitudinal direction (e.g., Z direction). The first column element 910, the second column element 920, the third column element 930 and the fourth column element 940 may include a suitable conductive material, such as tungsten (W).

[0060] In one embodiment, the local bit line 1400 is electrically connected to the bit line transistor 300 through the first pillar element 910, and the bit line transistor 300 is electrically connected to the global bit line 700 through the second pillar element 920. According to this embodiment, the local bit line 1400 is connected to the first pillar element 910, the first pillar element 910 is connected to the bit line transistor 300, the bit line transistor 300 is connected to the second pillar element 920, and the second pillar element 920 is connected to the global bit line 700.

[0061] In one embodiment, the local source line 1500 is electrically connected to the source line transistor 200 through the third pillar element 930, and the source line transistor 200 is electrically connected to the global source line 800 through the fourth pillar element 940. According to this embodiment, the local source line 1500 is connected to the third pillar element 930, the third pillar element 930 is connected to the source line transistor 200, the source line transistor 200 is connected to the fourth pillar element 940, and the fourth pillar element 940 is connected to the global source line 800.

[0062] By arranging the local bit lines 1400 and the local source lines 1500 alternately and connecting them to the bit line transistors 300 and the source line transistors 200 respectively, the resistance and capacitance delay time of the local bit lines 1400 and the local source lines 1500 can be effectively reduced.

[0063] Figure 1C Draw Figure 1A FIG. 1 is a layout view of a ladder decoder 100 and memory cell stacks 500_1, 500_2, . . . 500_K-1, 500_K of a semiconductor structure 10. FIG.

[0064] Please refer to Figure 1C The semiconductor structure 10 further includes a plurality of ladder decoders 100 and memory cell stacks 500_1, 500_2, . . . 500_K-1, 500_K.

[0065] In one embodiment, a plurality of ladder decoders 100 are respectively located below the memory cell stack 500_1, the memory cell stack 500_2, ..., the memory cell stack 500_K-1, and the memory cell stack 500_K. In other words, in the vertical direction, the plurality of ladder decoders 100 may respectively at least partially overlap the memory cell stack 500_1, the memory cell stack 500_2, ..., the memory cell stack 500_K-1, and the memory cell stack 500_K.

[0066] In one embodiment, the staircase decoder 100 includes a local driver 110 , a level shifter 120 , and other circuits 130 .

[0067] For example, the local driver 110 may include an NMOS, a PMOS, a complementary metal oxide semiconductor inverter (CMOS inverter), a diode, or a bipolar junction transistor (BJT).

[0068] For example, the other circuits 130 may include a pumping circuit, a decoding circuit, or a control circuit.

[0069] <Second Embodiment>

[0070] Figure 2A A partial top view of a semiconductor structure 20 according to a second embodiment of the present invention is shown. Figure 2B Draw Figure 2A A local enlarged view of the semiconductor structure 20 is shown. Figure 2C Draw Figure 2A A three-dimensional schematic diagram of a semiconductor structure 20 is shown.

[0071] Please also refer to Figure 2A , Figure 2B and Figure 2C The semiconductor structure 20 includes a complementary metal oxide semiconductor structure (including a source line transistor 200 and a bit line transistor 300), a memory cell stack 500, an insulating stack 600, an overall bit line 700, an overall source line 800, a first column element 910, a second column element 920, a third column element 930, a fourth column element 940, a through hole 1100, a first metal layer 1200 and a second metal layer 1300.

[0072] The semiconductor structure 20 of the second embodiment is similar to the semiconductor structure 10 of the first embodiment, and the main difference between them is that the source line transistor 200 is adjacent to the bit line transistor 300 .

[0073] In one embodiment, the source line transistor 200 and the bit line transistor 300 extend along a first direction, and the first metal layer 1200 extends along a second direction, and the first direction is different from the second direction. In another embodiment, the first direction can be defined as being substantially parallel to the extension direction of the memory cell stack 500, and the second direction can be defined as being substantially perpendicular to the extension direction of the memory cell stack 500. In other words, the first direction can be substantially perpendicular to the second direction.

[0074] In one embodiment, the memory cell stack 500 extends along a first direction, and the overall bit line 700, the overall source line 800 and the first metal layer 1200 extend along a second direction, and the first direction is different from the second direction. In another embodiment, the second direction can be defined as being substantially perpendicular to the extension direction of the memory cell stack 500. In other words, the first direction can be substantially perpendicular to the second direction.

[0075] In one embodiment, the first column element 910 , the second column element 920 , the third column element 930 and the fourth column element 940 extend in a longitudinal direction, which can be defined as a normal direction of a top surface of the source line transistor 200 , and can also be defined as a normal direction of a top surface of the bit line transistor 300 .

[0076] In one embodiment, the first pillar element 910, the second pillar element 920, the third pillar element 930 and the fourth pillar element 940 are located above the first metal layer 1200. In another embodiment, the first pillar element 910, the second pillar element 920, the third pillar element 930 and the fourth pillar element 940 are located above the first metal layer 1200 and the second metal layer 1300. In yet another embodiment, the first pillar element 910, the second pillar element 920, the third pillar element 930 and the fourth pillar element 940 are located between the local bit line 1400 and the bit line transistor 300, and the first pillar element 910, the second pillar element 920, the third pillar element 930 and the fourth pillar element 940 are located between the local source line 1500 and the source line transistor 200.

[0077] In one embodiment, the first metal layer 1200 is located above the source line transistor 200 and the bit line transistor 300. The first metal layer 1200 may include a suitable conductive material, such as tungsten (W).

[0078] In one embodiment, the second metal layer 1300 is located above the first metal layer 1200. In another embodiment, the second metal layer 1300 is located between the first metal layer 1200 and the second pillar element 920, or between the first metal layer 1200 and the fourth pillar element 940. The second metal layer 1300 may include a suitable conductive material, such as tungsten (W).

[0079] In one embodiment, the via 1100 is located between the global bit line 700 and the second pillar element 920. In another embodiment, the via 1100 is located between the global source line 800 and the fourth pillar element 940. The via 1100 may include a suitable conductive material, such as tungsten (W).

[0080] In one embodiment, the local bit line 1400 is electrically connected to the bit line transistor 300 through the first pillar element 910. That is, the first pillar element 910 can transmit the signal in the local bit line 1400 to the bit line transistor 300. In another embodiment, the first pillar element 910 can directly contact one of the local bit line 1400 or the bit line transistor 300. In another embodiment, the first pillar element 910 can directly contact the local bit line 1400 and the bit line transistor 300. In other words, the first pillar element 910 can serve as a connecting conductor between the local bit line 1400 and the bit line transistor 300, but the present invention is not limited thereto.

[0081] In one embodiment, the bit line transistor 300 is electrically connected to the overall bit line 700 through the first metal layer 1200, the second metal layer 1300, the second pillar element 920 and the through hole 1100. That is, the signal flowing into the bit line transistor 300 can be transmitted to the overall bit line 700 through the first metal layer 1200, the second metal layer 1300, the second pillar element 920 and the through hole 1100 in sequence.

[0082] In one embodiment, the local source line 1500 is electrically connected to the source line transistor 200 through the third pillar element 930. That is, the third pillar element 930 can transmit the signal in the local source line 1500 to the source line transistor 200. In another embodiment, the third pillar element 930 can directly contact one of the local source line 1500 or the source line transistor 200. In another embodiment, the third pillar element 930 can directly contact the local source line 1500 and the source line transistor 200. In other words, the third pillar element 930 can serve as a connecting conductor between the local source line 1500 and the source line transistor 200, but the present invention is not limited thereto.

[0083] In one embodiment, the source line transistor 200 is electrically connected to the overall source line 800 through the first metal layer 1200, the second metal layer 1300, the fourth pillar element 940 and the through hole 1100. That is, the signal flowing into the source line transistor 200 can be transmitted to the overall source line 800 through the first metal layer 1200, the second metal layer 1300, the fourth pillar element 940 and the through hole 1100 in sequence.

[0084] Please refer to Figure 2C , the global bit lines 700 and the global source lines 800 may be arranged alternately, but the present invention is not limited thereto.

[0085] <Third Embodiment>

[0086] Figure 3 Schematic diagram showing the layout of the local bit lines 1400 , the local source lines 1500 , the global bit lines 700 , and the global source lines 800 of the semiconductor structure 30 according to the third embodiment of the present invention.

[0087] Please refer to Figure 3 The semiconductor structure 30 includes a plurality of local bit lines 1400, a plurality of local source lines 1500, a complementary metal oxide semiconductor structure (including a source line transistor 200, a bit line transistor 300 and a ladder decoder 100), a global bit line 700, a global source line 800 and a sense amplifier 1000.

[0088] In one embodiment, the staircase decoder 100 is located below the memory cell stack 500 (not shown). In other words, in the vertical direction, the staircase decoder 100 at least partially overlaps the memory cell stack 500.

[0089] In one embodiment, multiple local bit lines 1400 , multiple local source lines 1500 , global bit lines 700 and global source lines 800 are located above the memory cell stack 500 (not shown), and the global bit lines 700 and global source lines 800 are located above the multiple local bit lines 1400 and the multiple local source lines 1500 .

[0090] In one embodiment, a plurality of local source lines 1500 are electrically connected to a plurality of source line transistors 200, which are electrically connected to the global source line 800. A plurality of local bit lines 1400 are electrically connected to a plurality of bit line transistors 300, which are electrically connected to the global bit line 700. In another embodiment, the number of local source lines 1500 electrically connected to the global source line 800 is greater than the number of local bit lines 1400 electrically connected to the global bit line 700. For example, the number of local source lines 1500 electrically connected to the global source line 800 is twice the number of local bit lines 1400 electrically connected to the global bit line 700, but the present invention is not limited thereto.

[0091] In one embodiment, the global bit line 700 is electrically connected to the sense amplifier 1000 .

[0092] According to this embodiment, since the number of local source lines electrically connected to the global source line is greater than the number of local bit lines electrically connected to the global bit line, it can have the advantages of reducing resistance, reducing the probability of short circuit, and reducing the use of wiring.

[0093] <Fourth Embodiment>

[0094] Figure 4 Schematic diagram showing the layout of the local bit lines 1400 , the local source lines 1500 , the global bit lines 700 , and the global source lines 800 of the semiconductor structure 40 according to the fourth embodiment of the present invention.

[0095] Please refer to Figure 4 The semiconductor structure 40 includes a plurality of local bit lines 1400, a plurality of local source lines 1500, a complementary metal oxide semiconductor structure (including a source line transistor 200, a bit line transistor 300 and a ladder decoder 100), a global bit line 700, a global source line 800 and a sense amplifier 1000.

[0096] The semiconductor structure 40 of the fourth embodiment is similar to the semiconductor structure 30 of the third embodiment, with the main difference being that the number of local source lines 1500 electrically connected to the global source line 800 is equal to the number of local bit lines 1400 electrically connected to the global bit line 700 .

[0097] In one embodiment, the global source line 800 is connected to a page buffer circuit.

[0098] According to this embodiment, since the number of local source lines electrically connected to the global source line is equal to the number of local bit lines electrically connected to the global bit line, array operation flexibility can be improved and current crowding effect can be avoided.

[0099] <Fifth Embodiment>

[0100] Figure 5 FIG. 1 is a layout diagram of a local bit line 1400 , a local source line 1500 , and a global bit line 700 of a semiconductor structure 50 according to a fifth embodiment of the present invention.

[0101] Please refer to Figure 5The semiconductor structure 50 includes a complementary metal oxide semiconductor structure (including a source line transistor 200 and a bit line transistor 300), a global bit line 700, a local bit line 1400, a local source line 1500 and a memory cell stack 500. The memory cell stack 500 includes a plurality of memory cell strings and a plurality of word lines WL0, WL1, ... WL j-1 , W.L. j The memory cell series is connected to the word lines WL0, WL1, ...WL j-1 , W.L. j Each intersection of the local bit lines 1400 and the local source lines 1500 may be electrically connected to the source or drain of the memory cell 1600, respectively.

[0102] In one embodiment, the plurality of local bit lines 1400 are respectively electrically connected to the plurality of bit line transistors 300 , and the bit line transistors 300 are electrically connected to the global bit line 700 .

[0103] In one embodiment, the plurality of local source lines 1500 are electrically connected to the plurality of source line transistors 200 , respectively, and the source line transistors 200 are grounded via local routing.

[0104] According to the above embodiments, the present invention provides a semiconductor structure. The semiconductor structure includes a memory cell stack and a complementary metal oxide semiconductor structure. The complementary metal oxide semiconductor structure is located below the memory cell stack and includes a source line transistor and a bit line transistor.

[0105] Compared to the comparative example in which the complementary metal oxide semiconductor structure is located in the peripheral area of ​​the memory cell stack rather than under the memory cell stack, the semiconductor structure of the present invention can effectively reduce the size of the memory device by arranging the complementary metal oxide semiconductor structure under the memory cell stack, further reducing the manufacturing cost, thereby improving the chip performance. Furthermore, by arranging the local bit lines and the local source lines alternately and connecting them to the bit line transistor and the source line transistor respectively, the resistance and capacitance delay time of the local bit lines and the local source lines can be effectively reduced.

[0106] In summary, although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. A person skilled in the art with common knowledge in the technical field to which the present invention belongs may make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

[0107] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: a memory cell stack; a complementary metal oxide semiconductor structure located below the memory cell stack; wherein the complementary metal oxide semiconductor structure includes a source line transistor, a bit line transistor and a ladder decoder, and the ladder decoder at least partially overlaps the memory cell stack in the vertical direction; a local source line located above the memory cell stack; and A third column element is located between the local source line and the source line transistor, wherein the local source line is electrically connected to the source line transistor through the third column element. 2 . The semiconductor structure according to claim 1 , wherein the source line transistor is adjacent to the bit line transistor.

3. The semiconductor structure according to claim 1, further comprising: a local bit line located above the memory cell stack; as well as a first pillar element located between the local bit line and the bit line transistor; The local bit line is electrically connected to the bit line transistor through the first pillar element.

4. The semiconductor structure according to claim 1, further comprising: a first metal layer located above the bit line transistor; a second pillar element located above the first metal layer; as well as a global bit line located above the memory cell stack; The bit line transistor is electrically connected to the overall bit line through the first metal layer and the second pillar element.

5. The semiconductor structure according to claim 4, wherein: The bit line transistor extends along a first direction, the first metal layer extends along a second direction, and the first direction is different from the second direction.

6. The semiconductor structure according to claim 1, further comprising: a first metal layer located above the source line transistor; a fourth pillar element, located above the first metal layer; as well as a global source line located above the memory cell stack; The source line transistor is electrically connected to the overall source line through the first metal layer and the fourth pillar element.

7. The semiconductor structure according to claim 6, wherein: The source line transistor extends along a first direction, the first metal layer extends along a second direction, and the first direction is different from the second direction.

8. The semiconductor structure according to claim 1, further comprising: A plurality of local source lines are located above the memory cell stack; A global source line located above the memory cell stack; wherein the local source lines are electrically connected to a plurality of the source line transistors, and the source line transistors are electrically connected to the global source line; A plurality of local bit lines located above the memory cell stack; and A global bit line located above the memory cell stack; wherein the local bit lines are electrically connected to a plurality of the bit line transistors, and the bit line transistors are electrically connected to the global bit line; The number of the local source lines electrically connected to the global source line is greater than or equal to the number of the local bit lines electrically connected to the global bit line.

9. The semiconductor structure according to claim 1, wherein: The source line transistor and the bit line transistor are arranged on opposite sides of the memory cell stack.

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