Chip packaging structure and preparation method thereof

Abstract

The present application provides a chip packaging structure and a method for preparing the same. The method for preparing the chip packaging structure includes: arranging a first semiconductor chip and a second semiconductor chip on a first side of a substrate, filling the first side with a plastic packaging material covering the first semiconductor chip and the second semiconductor chip; and forming a groove on a side of the plastic packaging material away from the substrate.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit packaging, and more specifically, to a chip packaging structure and a preparation method thereof. Background Art

[0002] With the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease, and people's performance requirements for three-dimensional memory are also increasing accordingly. However, three-dimensional memory (3D NAND) generates a lot of heat during operation. In order to avoid device burnout due to high temperature, the three-dimensional memory must be cooled.

[0003] The junction-to-case thermal resistance is the thermal resistance between the chip heat source junction in the package structure and the package shell. Its value mainly depends on the size of the heat dissipation path from the chip to the shell and the thermal conductivity of the material. The junction-to-case thermal resistance is one of the key parameters for evaluating the heat dissipation status.

[0004] It should be understood that the contents described in this background technology section are only used to help understand the technical solutions disclosed in this application, and do not necessarily belong to the prior art before the filing date of this application. Summary of the invention

[0005] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the related technology.

[0006] On one hand, the present application provides a method for preparing a chip packaging structure. The method comprises: arranging a first semiconductor chip and a second semiconductor chip on a first side of a substrate, filling the first side with a plastic encapsulation material covering the first semiconductor chip and the second semiconductor chip; and forming a groove on a side of the plastic encapsulation material away from the substrate.

[0007] In one embodiment, projections of the first semiconductor chip and the second semiconductor chip on the substrate are both located within the projection of the groove on the substrate.

[0008] In one embodiment, a depth of a portion of the groove located above the first semiconductor chip is greater than a depth of a portion of the groove located above the second semiconductor chip.

[0009] In one embodiment, the method further includes filling a second metal filler in a portion of the groove above the first semiconductor chip; and sintering the second metal filler to a molten state to fill the portion of the groove above the first semiconductor chip; and cooling and curing the second metal filler, wherein a side of the second metal filler away from the substrate after curing is coplanar with a bottom of the groove above the second semiconductor chip.

[0010] In one embodiment, the method further includes: filling the remaining portion of the groove with the first metal filler; sintering the first metal filler to a molten state to fill the groove; and cooling and solidifying the first metal filler.

[0011] In one embodiment, the method also includes: filling a second metal filler into a portion of the groove above the first semiconductor chip, wherein a side of the second metal filler away from the substrate is coplanar with a bottom of the groove above the second semiconductor chip; filling the remaining portion of the groove with the first metal filler; and sintering the second metal filler and the first metal filler to a molten state, respectively, to fill the groove, and cooling and solidifying.

[0012] In one embodiment, each of the first metal filler and the second metal filler includes at least one of metal powder, metal bulk, and metal slurry.

[0013] In one embodiment, the first metal filler and the second metal filler are the same.

[0014] In one embodiment, the first metal filler and the second metal filler are different.

[0015] In one embodiment, the first semiconductor chip includes a controller chip, and the second semiconductor chip includes a memory chip.

[0016] In one embodiment, the memory chip is a 3D NAND chip.

[0017] In one embodiment, the molding material includes epoxy molding compound.

[0018] In one embodiment, the step of forming a groove on a side of the molding material away from the substrate comprises forming a groove on a side of the molding material away from the substrate by at least one of photolithography, plasma etching and wet etching.

[0019] In one embodiment, the method further comprises providing a heat sink on a side of the molding material away from the substrate.

[0020] On the other hand, the present application provides a chip packaging structure, which includes: a substrate, and a first semiconductor chip and a second semiconductor chip arranged on a first side of the substrate. The chip packaging structure also includes: a plastic packaging material, which is coated on the outer side of the first semiconductor chip and the second semiconductor chip, and a groove filled with a metal filler is formed on a side of the plastic packaging material away from the substrate.

[0021] In one embodiment, projections of the first semiconductor chip and the second semiconductor chip on the substrate are both located within the projection of the groove on the substrate.

[0022] In one embodiment, a depth of a portion of the groove located above the first semiconductor chip is greater than a depth of a portion of the groove located above the second semiconductor chip.

[0023] In one embodiment, a portion of the groove located above the first semiconductor chip has a configuration including at least one of a rectangular parallelepiped and a rib-shaped configuration.

[0024] In one embodiment, a portion of the groove above the first semiconductor chip is filled with a second metal filling, wherein a side of the second metal filling away from the substrate is coplanar with a bottom of the groove above the second semiconductor chip.

[0025] In one embodiment, the remaining portion of the groove after the groove is filled with the second metal filler is filled with the first metal filler.

[0026] In one embodiment, the first semiconductor chip includes a controller chip, and the second semiconductor chip includes a memory chip.

[0027] In one embodiment, the memory chip is a 3D NAND chip.

[0028] In one embodiment, the chip packaging structure further includes a heat sink disposed on a side of the plastic packaging material away from the substrate.

[0029] The chip packaging structure and the method for preparing the chip packaging structure provided by the present application may have at least one of the following advantages:

[0030] 1) The preparation method of the chip packaging structure provided in the present application can improve the heat dissipation capacity of the entire packaging structure by replacing part of the packaging material with a metal having better thermal conductivity than the packaging material; and

[0031] 2) The method for preparing the chip packaging structure provided in the present application can achieve the effect of buffering the stress of the plastic packaging structure by retaining the plastic packaging material area outside the groove area. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other advantages of the embodiments of the present application will become apparent through the detailed description made with reference to the following drawings, which are intended to illustrate exemplary embodiments of the present application rather than to limit them. In the drawings:

[0033] Figure 1 is a flow chart of a method for preparing a chip packaging structure according to an exemplary embodiment of the present application;

[0034] Figure 2 Schematically shows a chip packaging structure according to an exemplary embodiment of the present application;

[0035] FIG. 3A to FIG. 3C is a schematic diagram of a process for forming a groove in a chip packaging structure according to an exemplary embodiment of the present application;

[0036] Figure 4 and Figure 5 is a schematic diagram of a process of filling a metal filler in a groove of a chip packaging structure according to an exemplary embodiment of the present application;

[0037] Figure 6 is a schematic diagram of a chip packaging structure according to an exemplary embodiment of the present application; and

[0038] Figures 7 to 9 It is a temperature simulation comparison diagram of chip packaging structures according to different embodiments under the same working conditions. DETAILED DESCRIPTION

[0039] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] Throughout the drawings and detailed description, the same reference numerals refer to the same elements. For purposes of clarity, illustration, and convenience, the drawings may not be drawn to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated.

[0041] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first metal filler discussed in this application may also be referred to as the second metal filler, the first groove may also be referred to as the second groove, and vice versa.

[0042] As used herein, "substantially," "approximately," and similar terms are used as terms of approximation, not degree, and are intended to account for the inherent variations in measurements or calculations that would be recognized by those of ordinary skill in the art.

[0043] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0044] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0045] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0046] The features, principles and other aspects of the present application are described in detail below.

[0047] Figure 1 FIG. 1 is a flow chart of a method 1000 for preparing a chip packaging structure according to an embodiment of the present application. Figure 1 As shown, the present application provides a method 1000 for preparing a chip packaging structure, comprising:

[0048] S1, arranging a first semiconductor chip and a second semiconductor chip on a first side of a substrate, and filling the first side of the substrate with a plastic encapsulation material covering the first semiconductor chip and the second semiconductor chip; and

[0049] S2, forming a groove on a side of the molding material away from the substrate.

[0050] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. In addition, some of the steps shown may be performed simultaneously or in different steps. Figure 1 The following will be combined with Figures 2 to 6 The specific process of each step of the above-mentioned preparation method 1000 is described in detail.

[0051] Figure 2The semiconductor chip package structure 100 according to an exemplary embodiment of the present application is schematically shown. For example, the semiconductor chip package structure 100 may be an intermediate structure in a three-dimensional memory (3D NAND) manufacturing process.

[0052] like Figure 2 As shown, the semiconductor chip package structure 100 includes a substrate 110 and a first side ( Figure 1 The first semiconductor chip 120 and the second semiconductor chip 130 are provided on the upper side of the substrate 110 in the substrate 110. The first side of the substrate 110 may be filled with a molding material 140, so that the first semiconductor chip 120 and the second semiconductor chip 130 are covered by the molding material 140. In an exemplary embodiment, the molding material 140 may include an epoxy molding material. The first semiconductor chip 120 may be bonded and fixed to the first side of the substrate 110 by a first adhesive layer 150. In addition, the first semiconductor chip 120 may be bonded to the substrate 110 by a lead 170 to achieve electrical connection. Exemplarily, the material of the lead 170 may be selected such as at least one of gold, aluminum, tin and copper. A second adhesive layer 160 may be provided between the second semiconductor chip 130 and the substrate 110, and the second semiconductor chip 130 may be bonded to the substrate 110 by a lead 180. In an exemplary embodiment, the material of the lead 180 may be the same as that of the lead 170.

[0053] In some embodiments, the first semiconductor chip 120 may include, for example, a controller chip, and the second semiconductor chip 130 may include, for example, a memory chip. Exemplarily, the memory chip may be a 3D NAND chip.

[0054] In other embodiments, the first semiconductor chip 120 and the second semiconductor chip 130 may include, for example, a controller chip, a memory chip, a FR chip, a positioning chip, a Bluetooth chip, a sensor chip, or any combination thereof. For example, the memory chip may be a chip such as 3D NAND or DRAM.

[0055] The inventor of the present application has found that in products such as universal flash memory (UFS) and embedded multimedia memory (EMMC), a variety of heat-generating chips are generally included, such as controller chips and memory chips. Among them, the surface area of ​​the controller chip is small and the power is high, which is easy to form a local heat flux concentration, resulting in a high junction-to-shell thermal resistance of the entire packaged product. The current related technology usually uses a plastic shell end to conduct heat to an external frame or an external radiator for heat dissipation. This heat dissipation method cannot solve the problem of high junction-to-shell thermal resistance caused by chip heating.

[0056] The present application proposes a chip packaging structure and a manufacturing method thereof, which can at least partially improve or solve the above-mentioned problems and achieve the effect of reducing the junction-to-shell thermal resistance of the chip packaging structure 100 .

[0057] FIG. 3A to FIG. 3C FIG. 1 is a schematic diagram of a process for forming a groove 190 in a semiconductor chip package structure 100 according to an exemplary embodiment of the present application. Figure 3A As shown, the side of the molding material 140 away from the substrate 110 is etched to form a groove 190, wherein the projections of the first semiconductor chip 120 and the second semiconductor chip 140 on the substrate 110 are both located within the projection of the groove 190 on the substrate, and the depth of the portion of the groove 190 located above the first semiconductor chip 120 is greater than the depth of the portion located above the second semiconductor chip 130. Exemplarily, the groove 190 can be formed on the side of the molding material 140 away from the substrate 110 by at least one of photolithography, plasma etching, and wet etching.

[0058] In some embodiments, the method of forming the groove 190 may include etching a region above the first semiconductor chip 110 and the second semiconductor chip 120 from a side away from the substrate 110 to form a first groove 191 (eg, Figure 3B As shown), and the area in the first sub-recess 191 corresponding to the first semiconductor chip 120 is further etched to form a second sub-recess 192 (as shown Figure 3B shown).

[0059] In some other embodiments, the method of forming the groove 190 may include etching the area above the first semiconductor chip 110 from a side away from the substrate 110 to form a third sub-groove 193 (eg, Figure 3C ), and etching the area above the second semiconductor chip 120 from the side away from the substrate 110 to form a fourth sub-recess 194 (as shown in Figure 3C As shown), wherein the third sub-groove 193 and the fourth sub-groove 194 are Figure 3A The third sub-groove 193 is tightly fitted in the x direction shown in FIG. Figure 3A The depth in the y-direction shown is greater than the fourth sub-groove 194 .

[0060] Figure 4 and Figure 5 FIG. 1 is a schematic diagram of a process for filling a metal filler in the groove 190 of the semiconductor chip package structure 100 according to an exemplary embodiment of the present application. In some embodiments, as Figure 4As shown, the second metal filler 200 is filled in the groove portion located above the first semiconductor chip 120, and the second metal filler 200 is sintered to a molten state to fill the portion of the groove 190 located above the first semiconductor chip, and then the temperature is lowered to solidify the second metal filler 200. The side of the second metal filler 200 away from the substrate 110 after solidification is coplanar with the bottom of the groove 190 located above the second semiconductor chip 130. It should be noted that the material of the bottom surface of the groove 190 is a plastic encapsulation material 140, and the plastic encapsulation material 140 is pre-treated so as to meet the high temperature of the second metal filler 200 when it is in a molten state. Exemplarily, the second metal filler 200 can be selected from at least one of metal powder, metal block and metal slurry. Specifically, the second metal filler 200 can be selected from copper, aluminum, copper alloy, aluminum alloy and any combination thereof.

[0061] In some exemplary embodiments, after the second metal filler 200 is solidified, the remaining portion of the groove 190 may be filled with the first metal filler 210 (eg, Figure 5 As shown), to fill the groove 190. Specifically, the first metal filler 210 can be filled into the remaining part of the groove 190 that is not filled by the second metal filler 200, and then the first metal filler 210 can be sintered to a molten state to fill the groove 190. Exemplarily, the side of the first metal filler 210 away from the substrate 110 can be coplanar with the side of the molding material 140 away from the substrate. In an exemplary embodiment, the first metal filler 210 can be selected from at least one of metal powder, metal block and metal slurry. Specifically, the first metal filler 210 can be selected from copper, aluminum, copper alloy, aluminum alloy and any combination thereof. In some embodiments, the material of the first metal filler 210 and the second metal filler 200 can be the same. In other embodiments, the material of the first metal filler 210 and the second metal filler 200 can also be different.

[0062] Figure 6 is a schematic diagram of a semiconductor chip package structure 100 according to an exemplary embodiment of the present application.

[0063] In some embodiments, the configuration of the portion of the groove 190 located above the first semiconductor chip 120 may include at least one of a rectangular parallelepiped and a rib-shaped structure (see Figure 6 ).

[0064] In some embodiments, a heat sink 220 may be provided on the side of the molding material 140 away from the substrate 110 (see Figure 6 ) to increase the heat dissipation of the device.

[0065] Another aspect of the present application further provides a chip packaging structure. The chip packaging structure can be prepared by any preparation method in the above-mentioned embodiments.

[0066] Continue to refer Figure 6 , the chip package structure 100 may include a substrate 110, a first semiconductor chip 120 and a second semiconductor chip 130 located on the substrate 110 (along the y direction), and a molding material 140. In some embodiments, the molding material 140 is located on the substrate 110 and covers the first semiconductor chip 120 and the second semiconductor chip 130. A second metal filler 200 is filled on one side of the molding material 140 away from the substrate 110 to increase the heat dissipation performance of the chip package structure 100. Exemplarily, the cross-sectional shape (along the z direction) of the second metal filler 200 may include, for example, a rectangle, a rib shape, or any combination thereof.

[0067] In some embodiments, a projection of the first semiconductor chip 120 on the substrate 110 is located within a projection of the second metal filler 200 on the substrate 110 .

[0068] In some embodiments, a first metal filler 210 located on the second metal filler 200 is further provided on a side of the molding material 140 away from the substrate 110 .

[0069] In some embodiments, projections of the first semiconductor chip 120 and the second semiconductor chip 130 on the substrate 110 are both located within a projection of the first metal filler 210 on the substrate 110 .

[0070] In some embodiments, the first metal filler 210 and the second metal filler 220 may be made of the same material, such as copper, aluminum, iron, tungsten, nickel, silver, copper alloy, aluminum alloy, iron alloy, tungsten alloy, nickel alloy, silver alloy or any combination thereof, which have good thermal conductivity. In other embodiments, the first metal filler 210 and the second metal filler 220 may be made of different materials.

[0071] In some embodiments, the first semiconductor chip 120 may include, for example, a controller chip, and the second semiconductor chip 130 may include, for example, a memory chip. Exemplarily, the memory chip may be a 3D NAND chip.

[0072] In other embodiments, the first semiconductor chip 120 and the second semiconductor chip 130 may include, for example, a controller chip, a memory chip, a FR chip, a positioning chip, a Bluetooth chip, a sensor chip, or any combination thereof. For example, the memory chip may be a chip such as 3D NAND or DRAM.

[0073] In some embodiments, a heat sink 220 may be provided on the side of the molding material 140 away from the substrate 110 (see Figure 6 ) to increase the heat dissipation of the device.

[0074] Figures 7 to 9 1 is a temperature simulation comparison diagram of the chip packaging structure 100 under the same working conditions according to different embodiments. Figure 7 (B) for Figure 7 (A) an example of a corresponding chip package structure 100, Figure 8 (B) for Figure 8 (A) an example of a corresponding chip package structure 100, Fig. 9 (B) for Figure 8 (A) An example of a corresponding chip package structure 100 .

[0075] Combination Figures 7 to 9 It can be seen that Figure 7 The junction temperature θ of the chip package structure 100 shown in (B) JC =12.9℃ / W, Figure 8 The junction temperature θ of the chip package structure 100 shown in (B) JC =12.0℃ / W, Fig. 9 The junction temperature θ of the chip package structure 100 shown in (B) JC =12.1°C / W. This indicates that in some embodiments of the present application, the chip package structure 100 with the groove 190 and the chip package structure 100 filled with the first metal material 200 and the second metal material 210 have reduced junction-to-shell thermal resistance and improved heat dissipation performance.

[0076] Since the contents and structures involved in the above description of the preparation method 1000 may be fully or partially applicable to the chip packaging structure 100 described herein, the contents related or similar thereto will not be described in detail.

[0077] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for preparing a chip packaging structure, characterized in that: The method comprises: Arranging a first semiconductor chip and a second semiconductor chip on a first side of the substrate, and filling the first side with a molding material covering the first semiconductor chip and the second semiconductor chip; and forming a groove on a side of the molding material away from the substrate; The projections of the first semiconductor chip and the second semiconductor chip on the substrate are both located within the projection of the same groove on the substrate; the depth of a portion of the groove located above the first semiconductor chip is greater than the depth of a portion of the groove located above the second semiconductor chip; forming a solidified second metal filler at a portion of the groove located above the first semiconductor chip, wherein a surface of the second metal filler facing the substrate is in a rib shape; After forming the solidified second metal filler, the solidified first metal filler is shaped in the remaining portion of the groove; A heat sink is arranged on a side of the first metal filler away from the substrate.

2. The method according to claim 1, characterized in that The method further comprises: Filling a second metal filler in a portion of the groove located above the first semiconductor chip; and sintering the second metal filler to a molten state to fill a portion of the groove located above the first semiconductor chip; The second metal filling is cured by cooling, wherein a side of the second metal filling away from the substrate after curing is coplanar with a bottom of the groove located above the second semiconductor chip.

3. The method according to claim 2, characterized in that The method further comprises: filling the remaining portion of the groove with the first metal filler; sintering the first metal filler to a molten state to fill the groove; and The first metal filler is cured by cooling.

4. The method according to claim 1, characterized in that: The method further comprises: Filling a second metal filler in a portion of the groove above the first semiconductor chip, wherein a side of the second metal filler away from the substrate is coplanar with a bottom of the groove above the second semiconductor chip; filling the remaining portion of the groove with the first metal filler; and The second metal filler and the first metal filler are sintered to a molten state to fill the groove, and then cooled to solidify.

5. The method according to claim 3, characterized in that: Each of the first metal filler and the second metal filler includes at least one of metal powder, metal bulk, and metal slurry.

6. The method according to claim 5, characterized in that The first metal filler and the second metal filler are the same.

7. The method according to claim 5, characterized in that The first metal filler and the second metal filler are different.

8. The method according to claim 1, characterized in that The first semiconductor chip includes a controller chip, and the second semiconductor chip includes a memory chip.

9. The method according to claim 8, characterized in that The memory chip is a 3D NAND chip.

10. The method according to claim 1, characterized in that The molding material comprises epoxy molding material.

11. The method according to claim 1, characterized in that: The step of forming a groove on a side of the molding material away from the substrate comprises: A groove is formed on a side of the molding material away from the substrate by at least one of photoetching, plasma etching and wet etching.

12. A chip packaging structure, comprising a substrate, and a first semiconductor chip and a second semiconductor chip disposed on a first side of the substrate; It is characterized in that The chip packaging structure further includes: A plastic encapsulation material is coated on the outer sides of the first semiconductor chip and the second semiconductor chip, and a groove filled with a metal filler is formed on a side of the plastic encapsulation material away from the substrate; The projections of the first semiconductor chip and the second semiconductor chip on the substrate are both located within the projection of the same groove on the substrate; the depth of a portion of the groove located above the first semiconductor chip is greater than the depth of a portion of the groove located above the second semiconductor chip; a second metal filling located in a portion of the groove located above the first semiconductor chip; a first metal filler located in a remaining portion of the groove other than the second metal filler; The heat dissipation frame is arranged on a side of the plastic packaging material away from the substrate.

13. The chip packaging structure according to claim 12, characterized in that: A portion of the groove located above the first semiconductor chip may have a rib-like configuration.

14. The chip packaging structure according to claim 12, characterized in that A side of the second metal filling away from the substrate is coplanar with a bottom of the groove located above the second semiconductor chip.

15. The chip packaging structure according to claim 12, characterized in that: The first semiconductor chip includes a controller chip, and the second semiconductor chip includes a memory chip.

16. The chip packaging structure according to claim 15, characterized in that: The memory chip is a 3D NAND chip.

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