Bit line structure manufacturing method, semiconductor structure manufacturing method and semiconductor structure

Abstract

The present invention provides a method for manufacturing a bit line structure, a method for manufacturing a semiconductor structure, and a semiconductor structure. The method for manufacturing a bit line structure includes the following steps: forming a bit line conductive layer on the surface of a semiconductor substrate, wherein a portion of the bit line conductive layer is located in a groove on the surface of the semiconductor substrate; forming a first protective layer on the surface of the bit line conductive layer and the semiconductor substrate; forming a first barrier layer on the surface of the first protective layer; performing a passivation treatment on the surface of the first barrier layer; forming a sacrificial layer on the surface of the first barrier layer, wherein the sacrificial layer has a filling portion filled in the groove; and removing the portion of the sacrificial layer other than the filling portion by cleaning with an etching liquid. The present invention performs a passivation treatment on the first barrier layer, thereby increasing the etching selectivity of the etching liquid to the sacrificial layer and the first barrier layer, so that when the sacrificial layer is cleaned and removed with the etching liquid, the conductive layer in the first barrier layer will not be damaged.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a bit line structure, a method for manufacturing a semiconductor structure, and a semiconductor structure. Background Art

[0002] With the rapid development of nano devices in the semiconductor industry in recent years, the feature size in chip production has continued to shrink, and the entire technology continues to develop in the direction of further miniaturization of key dimensions. For example, in the process technology of advanced dynamic random access memory (DRAM), the process technology level of the bit line will seriously affect the electrical properties, yield and reliability of the subsequent chip. In particular, as the key dimensions continue to shrink, the requirements for the miniaturization and stability of the sacrificial layer are becoming higher and higher. Among them, the removal method of the sacrificial layer of the bit line is becoming more and more important.

[0003] like Figure 1 and Figure 2 As shown, in the existing process, since the etching selectivity ratio (i.e., the ratio of the etching rate of the sacrificial layer 150 by the etching solution to the etching rate of the blocking layer 140 by the etching solution) of the etching solution (e.g., phosphoric acid solution, H3PO4) to the sacrificial layer 150 (e.g., silicon nitride, Si3N4) and to the blocking layer 140 (e.g., silicon oxide, SiO2) is relatively small, the etching solution is likely to etch away the blocking layer 140 when cleaning and removing (stripping) the sacrificial layer 150, thereby partially removing the protective layer 130 and causing etching damage 121 (W Missing, W is tungsten) to the conductive layer 120 in the blocking layer 140.

[0004] In view of the above problems, it is necessary to optimize the manufacturing method of the bit line structure. Summary of the invention

[0005] A main purpose of the present invention is to overcome at least one defect of the above-mentioned prior art and provide a method for manufacturing a bit line structure capable of preventing the conductive layer from being damaged by etching solution.

[0006] Another main purpose of the present invention is to overcome at least one of the defects of the prior art mentioned above and provide a semiconductor structure manufacturing method using the above bit line structure manufacturing method.

[0007] Another main object of the present invention is to overcome at least one of the above-mentioned defects of the prior art and provide a semiconductor structure manufactured by the above-mentioned semiconductor structure manufacturing method.

[0008] To achieve the above object, the present invention adopts the following technical solution:

[0009] According to one aspect of the present invention, a method for manufacturing a bit line structure is provided; wherein the method for manufacturing a bit line structure comprises the following steps:

[0010] Forming a bit line conductive layer on the surface of the semiconductor substrate, wherein a portion of the bit line conductive layer is located in a groove on the surface of the semiconductor substrate;

[0011] forming a first protective layer on the surface of the bit line conductive layer and the semiconductor substrate;

[0012] forming a first barrier layer on a surface of the first protective layer;

[0013] Passivating the surface of the first barrier layer;

[0014] forming a sacrificial layer on a surface of the first barrier layer, the sacrificial layer having a filling portion filled in the groove; and

[0015] The sacrificial layer is cleaned and removed with an etching solution except for the filling portion.

[0016] According to one embodiment of the present invention, the passivation treatment includes plasma treatment, ion implantation or thermal oxidation treatment.

[0017] According to one embodiment of the present invention, the first barrier layer after passivation treatment includes a two-layer thin film structure, namely a first thin film layer adjacent to the first protective layer and a second thin film layer away from the first protective layer; wherein the etching selectivity ratio of the sacrificial layer to the second thin film layer is greater than the etching selectivity ratio of the sacrificial layer to the first thin film layer.

[0018] According to one embodiment of the present invention, the material of the first barrier layer includes silicon oxide; wherein the passivation treatment includes nitrogen plasma treatment, and the material of the second thin film layer includes silicon oxynitride.

[0019] According to one embodiment of the present invention, the thickness of the first protective layer is 1 nm to 3 nm; and / or the thickness of the first barrier layer is 2 nm to 8 nm.

[0020] According to one embodiment of the present invention, the material of the first protective layer includes silicon nitride; and / or the material of the first barrier layer includes silicon oxide; and / or the material of the sacrificial layer includes silicon nitride.

[0021] According to one embodiment of the present invention, the etching solution comprises a phosphoric acid solution; wherein the temperature of the etching solution is 100° C. to 120° C.; and / or the concentration of the etching solution is 40% to 60%.

[0022] According to one embodiment of the present invention, after the etching solution is used to clean and remove the portion of the sacrificial layer other than the filling portion, the method further comprises the following steps:

[0023] removing the exposed first barrier layer;

[0024] forming a second barrier layer on the surface of the bit line conductive layer and the semiconductor substrate;

[0025] A second protective layer is formed on a surface of the second barrier layer.

[0026] According to one embodiment of the present invention, when the sacrificial layer is removed by cleaning with the etching solution, the following steps are included:

[0027] Pre-cleaning the surface of the sacrificial layer using a diluted hydrofluoric acid solution to remove the oxide layer on the surface of the sacrificial layer; and

[0028] The sacrificial layer is cleaned with a phosphoric acid solution to remove a portion of the sacrificial layer except the filling portion.

[0029] According to another aspect of the present invention, a method for manufacturing a semiconductor structure is provided; wherein the method for manufacturing a semiconductor structure comprises the following steps:

[0030] Providing a semiconductor substrate, wherein a surface of the semiconductor substrate has a groove;

[0031] By using the method for manufacturing a bit line structure proposed by the present invention and described in the above embodiment, a bit line structure is formed on the semiconductor substrate.

[0032] According to one embodiment of the present invention, the passivation treatment comprises plasma treatment; wherein the passivation treatment of the first barrier layer comprises the following steps:

[0033] preheating a processing chamber of a processing device;

[0034] placing the semiconductor structure having the first barrier layer formed thereon into a processing chamber;

[0035] Inputting a reaction medium and performing plasma treatment on the surface of the first barrier layer;

[0036] cooling the processing chamber; and

[0037] The semiconductor structure is removed.

[0038] According to another aspect of the present invention, a semiconductor structure is provided; wherein the semiconductor structure comprises a semiconductor substrate, a bit line conductive layer and a bit line plug spacer; the surface of the semiconductor substrate has a groove; the bit line conductive layer is partially located in the groove on the surface of the semiconductor substrate; the bit line plug spacer is filled in the groove, and the bit line plug spacer comprises a first protective layer, a first barrier layer after passivation treatment, and a filling portion.

[0039] According to one embodiment of the present invention, the thickness of the first protective layer is 1 nm to 3 nm; and / or the thickness of the first barrier layer is 2 nm to 8 nm.

[0040] According to one embodiment of the present invention, the material of the first protective layer includes silicon nitride; and / or the material of the first barrier layer includes silicon oxide; and / or the material of the filling portion includes silicon nitride.

[0041] According to one embodiment of the present invention, the first barrier layer after passivation treatment includes a two-layer thin film structure, namely a first thin film layer adjacent to the first protective layer and a second thin film layer away from the first protective layer; wherein the etching selectivity ratio of the filling part to the second thin film layer is greater than the etching selectivity ratio of the filling part to the first thin film layer.

[0042] According to one embodiment of the present invention, the material of the first thin film layer includes silicon oxide, and the material of the second thin film layer includes silicon oxynitride.

[0043] It can be seen from the above technical solutions that the advantages and positive effects of the method for manufacturing a bit line structure proposed by the present invention are:

[0044] The present invention performs a passivation treatment on the first barrier layer, so that the etching selectivity ratio of the etching solution to the sacrificial layer and the first barrier layer is increased, so that when the etching solution is used to clean and remove the sacrificial layer, the conductive layer in the first barrier layer will not be damaged. Moreover, on the basis of achieving the above-mentioned effects, compared with the existing process, the present invention does not need to add an active agent to the etching solution, so the cleaning process of the present invention is relatively simple and will not affect the product yield. In addition, the present invention does not need to increase the thickness of the first barrier layer, and can ensure the filling quality of the groove, further meeting the design requirements of the miniaturization and thinning of the key dimensions of semiconductor products. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Various objects, features and advantages of the present invention will become more apparent by considering the following detailed description of preferred embodiments of the present invention in conjunction with the accompanying drawings. The accompanying drawings are merely exemplary illustrations of the present invention and are not necessarily drawn to scale. In the accompanying drawings, the same reference numerals always refer to the same or similar parts. Among them:

[0046] Figure 1 It is a schematic diagram of a semiconductor structure of a step in an existing method for manufacturing a bit line structure;

[0047] Figure 2 yes Figure 1 An enlarged comparison diagram of a portion of the bit line structure before and after etching to remove the sacrificial layer is shown;

[0048] Figure 3 is a schematic diagram of a semiconductor structure in one step of a method for manufacturing a bit line structure according to an exemplary embodiment;

[0049] Figure 4 is an enlarged schematic diagram of a bit line structure of a semiconductor structure during one step of a method for manufacturing a bit line structure according to an exemplary embodiment;

[0050] Figure 5 is an enlarged schematic diagram of a bit line structure of a semiconductor structure during one step of a method for manufacturing a bit line structure according to an exemplary embodiment;

[0051] Figure 6 is an enlarged schematic diagram of a bit line structure of a semiconductor structure during one step of a method for manufacturing a bit line structure according to an exemplary embodiment;

[0052] Figure 7 is an enlarged schematic diagram of a bit line structure of a semiconductor structure during one step of a method for manufacturing a bit line structure according to an exemplary embodiment;

[0053] Figure 8 is an enlarged schematic diagram of a bit line structure of a semiconductor structure during one step of a method for manufacturing a bit line structure according to an exemplary embodiment;

[0054] The following are the descriptions of the reference numerals:

[0055] 111. Groove;

[0056] 120. Conductive layer;

[0057] 121. Etching damage;

[0058] 130. Protective layer;

[0059] 140. Barrier layer;

[0060] 150. Sacrificial layer;

[0061] 210.Semiconductor substrate;

[0062] 211. Groove;

[0063] 220. Bit line conductive layer;

[0064] 221.Metal layer;

[0065] 222. Bit line plug;

[0066] 223. Titanium nitride;

[0067] 230. First protective layer;

[0068] 240. First barrier layer;

[0069] 241. first film layer;

[0070] 242. Second film layer;

[0071] 250. Sacrificial layer;

[0072] 251. Filling part;

[0073] 260.Bit line plug spacer layer. DETAILED DESCRIPTION

[0074] Typical embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various changes in different embodiments without departing from the scope of the present invention, and the descriptions and drawings therein are essentially for illustrative purposes rather than for limiting the present invention.

[0075] In the following description of different exemplary embodiments of the present invention, reference is made to the accompanying drawings, which form a part of the present invention and in which different exemplary structures, systems and steps that can implement multiple aspects of the present invention are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present invention. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present invention, these terms are used herein only for convenience, such as according to the direction of the examples described in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present invention.

[0076] See also Figures 3 to 8, which respectively and representatively show the schematic diagrams of semiconductor structures in each step of the method for manufacturing a bit line structure proposed in the present invention. In this exemplary embodiment, the method for manufacturing a bit line structure proposed in the present invention is described by taking the preparation of a bit line applied to a dynamic random access memory as an example. It is easy for those skilled in the art to understand that in order to apply the relevant design of the present invention to the manufacturing method of other types of semiconductor structures, various modifications, additions, substitutions, deletions or other changes are made to the specific embodiments described below, and these changes are still within the scope of the principle of the method for manufacturing a bit line structure proposed in the present invention.

[0077] like Figures 3 to 8 As shown, in this embodiment, the method for manufacturing a bit line structure provided by the present invention comprises the following steps:

[0078] A bit line conductive layer 220 is formed on the surface of the semiconductor substrate 210 , and a portion of the bit line conductive layer 220 is located in a groove 211 on the surface of the semiconductor substrate 210 ;

[0079] forming a first protection layer 230 on the surface of the bit line conductive layer 220 and the semiconductor substrate 210;

[0080] forming a first barrier layer 240 on a surface of the first protective layer 230;

[0081] Passivating the surface of the first barrier layer 240;

[0082] A sacrificial layer 250 is formed on the surface of the first barrier layer 240 . The sacrificial layer 250 has a filling portion 251 filled in the groove 211 . The sacrificial layer 250 is removed by cleaning with an etching solution except for the filling portion 251 .

[0083] At this point, the semiconductor bit line is basically prepared.

[0084] Through the above design, the present invention performs a passivation treatment on the first barrier layer 240, so that the etching liquid increases the etching selectivity ratio between the sacrificial layer 250 and the first barrier layer 240, so that when the sacrificial layer 250 is removed by the etching liquid, the bit line conductive layer 220 in the first barrier layer 240 will not be damaged. In addition, compared with the existing process, the present invention does not need to add an active agent to the etching liquid, nor does it need to increase the thickness of the first barrier layer 240.

[0085] Specifically, Figure 3As shown, it specifically shows a semiconductor layered structure, which can be used as a representative example of the semiconductor structure in the step of "forming a bit line conductive layer 220" in this embodiment. The surface of the semiconductor substrate 210 has a groove 211. The bit line conductive layer 220 is formed at the groove 211 on the surface of the semiconductor substrate 210, and the bit line conductive layer 220 includes a metal layer 221, a bit line plug 222, and may also include titanium nitride 223 (TiN) and a silicon nitride cap layer. The bit line plug 222 is formed in the groove 211 on the surface of the semiconductor substrate 210, a layer of titanium nitride 223 is formed on the bit line plug 222, a metal layer 221 is formed on the layer of titanium nitride 223, and a layer of silicon nitride is also formed on the metal layer 221.

[0086] Specifically, Figure 4 , which specifically shows an enlarged layered structure of a semiconductor bit line, which can be used as a representative example of the bit line in the step of "forming the first protection layer 230" in this embodiment. The first protection layer 230 is formed on the surface of the bit line conductive layer 220 and the surface of the semiconductor substrate 210 (the portion where the bit line conductive layer 220 is not provided), that is, the groove wall of the groove 211 and the groove bottom where the bit line conductive layer 220 (bit line plug 222) is not provided are both formed with the first protection layer 230.

[0087] Preferably, in the present embodiment, for the step of “forming the first protective layer 230”, the thickness of the first protective layer 230 may be preferably 1 nm to 3 nm, such as 1 nm, 1.5 nm, 2 nm, 3 nm, etc. In other embodiments, the thickness of the first protective layer 230 may also be less than 1 nm, or may be greater than 3 nm, such as 0.8 nm, 4 nm, 5 nm, etc., and is not limited to the present embodiment.

[0088] Preferably, in this embodiment, for the step of “forming the first protective layer 230”, the material of the first protective layer 230 may preferably include silicon nitride. In the step of “forming the sacrificial layer 250”, the material of the sacrificial layer 250 may also preferably include silicon nitride. For the sake of distinction, when the silicon nitride layer is used as the first protective layer 230, it may be referred to as InnerSiN, and when the silicon nitride layer is used as the sacrificial layer 250, it may be referred to as Outer SiN.

[0089] Specifically, Figure 5As shown, it specifically shows an enlarged layered structure of a semiconductor bit line, which can be used as a representative example of the bit line in the step of "forming the first barrier layer 240" in this embodiment. The first barrier layer 240 is formed on the surface of the first protective layer 230, that is, the groove wall of the groove 211 and the part of the groove bottom where the bit line conductive layer 220 (bit line plug 222) is not provided are sequentially formed with the first protective layer 230 and the first barrier layer 240. In this embodiment, the material of the first barrier layer 240 can be but is not limited to silicon oxide.

[0090] Specifically, Figure 6 , which specifically shows an enlarged layered structure of a semiconductor bit line, which can be used as a representative example of a bit line structure in the "passivation treatment" step in this embodiment. In this step, after forming the first barrier layer 240 on the surface of the first protection layer 230, the surface of the first barrier layer 240 is passivated.

[0091] Preferably, in this embodiment, for the step of "passivation treatment", the passivation treatment performed on the first barrier layer 240 may preferably include plasma treatment. Further, the plasma treatment may preferably be nitrogen (N2) plasma treatment. In other embodiments, the passivation treatment performed on the first barrier layer 240 may also adopt other passivation processes or combinations, such as ion implantation, thermal oxidation treatment, etc., and is not limited to this embodiment.

[0092] Preferably, if Figure 6As shown, in this embodiment, for the step of "passivation treatment", the surface of the first barrier layer 240 roughly includes two thin film structures after passivation treatment. For ease of understanding and explanation, these two thin film structures are defined as the first thin film layer 241 and the second thin film layer 242 in this specification. Among them, the first thin film layer 241 is adjacent to the first protective layer 230, and the second thin film layer 242 is away from the first protective layer 230 (that is, adjacent to the sacrificial layer 250 formed in the subsequent process). On this basis, the first thin film layer 241 can also be understood as a layered structure that roughly maintains the same property state as the first barrier layer 240 when it is not passivated, and the second thin film layer 242 is a layer whose property state is changed compared to the first barrier layer 240 when it is not passivated. The above-mentioned changes of the second film layer 242 include: the etching selectivity ratio of the sacrificial layer 250 to the second film layer 242 is greater than the etching selectivity ratio of the sacrificial layer 250 to the first film layer 241, that is, after the first barrier layer 240 is passivated, the etching selectivity ratio of the sacrificial layer 250 to the first barrier layer 240 increases. In other embodiments, based on different types of passivation treatments, the first barrier layer 240 may also form a two-layer or more thin film structure, and the etching selectivity ratio of the sacrificial layer 250 to at least one of the thin film structures of the first barrier layer 240 is greater than the etching selectivity ratio of the sacrificial layer 250 to the other thin film structures. Alternatively, the first barrier layer 240 after the passivation treatment may also maintain a single-layer thin film structure, and the etching selectivity ratio of the sacrificial layer 250 to the first barrier layer 240 after the treatment is greater than the etching selectivity ratio of the sacrificial layer 250 to the first barrier layer 240 before the treatment. That is, after the passivation treatment, the first barrier layer 240 can form various possible layered thin film structures, and the etching selectivity ratio of the sacrificial layer 250 to the first barrier layer 240 is increased after the first barrier layer 240 is passivated.

[0093] For example, based on the design that the material of the first barrier layer 240 includes silicon oxide and the passivation treatment includes nitrogen plasma treatment, in this embodiment, after the silicon oxide is treated with nitrogen plasma, the material of the second film layer 242 includes silicon oxynitride (SiON). Accordingly, taking the example that the material of the sacrificial layer 250 includes silicon nitride, the etching selectivity ratio of silicon nitride to silicon oxynitride is greater than the etching selectivity ratio of silicon nitride to silicon oxide, that is, after the first barrier layer 240 is treated with nitrogen plasma, the etching selectivity ratio of the sacrificial layer 250 to the first barrier layer 240 increases.

[0094] Preferably, in the present embodiment, for the step of "forming the first barrier layer 240", the thickness of the first barrier layer 240 may be preferably 2nm to 8nm, such as 2nm, 3nm, 4nm, 5nm, etc. In other embodiments, the thickness of the first barrier layer 240 may also be less than 2nm, such as 1nm, 1.5nm, etc., and is not limited to the present embodiment. It should be noted that, since the present invention adopts the process step of passivating the first barrier layer 240, the etching selectivity ratio of the sacrificial layer 250 formed in the subsequent process to the first barrier layer 240 is increased. Therefore, under the same etching conditions (such as the temperature and concentration of the etching solution, the cleaning time are the same), if the same etching removal effect is to be achieved, the required thickness of the first barrier layer 240 formed in the present invention is less than the required thickness of the barrier layer formed in the existing process. That is, the preferred range of the thickness of the first barrier layer 240 in the present embodiment is actually not achievable by the existing process, rather than a simple selection of the data range.

[0095] Preferably, based on the design that the passivation treatment includes plasma treatment, in this embodiment, for the step of "passivation treatment", the passivation treatment of the first barrier layer 240 may preferably include the following specific steps:

[0096] preheating a processing chamber of a processing device;

[0097] placing the semiconductor structure formed with the first barrier layer 240 into a processing chamber;

[0098] Inputting a reaction medium and performing plasma treatment on the surface of the first barrier layer 240;

[0099] Cooling the processing chamber;

[0100] The semiconductor structure is removed.

[0101] As mentioned above, the plasma treatment of the first barrier layer 240 can preferably be performed using a plasma surface treatment apparatus or other processing equipment. On this basis, the semiconductor structure is placed in the processing chamber of the plasma surface treatment apparatus, and the processing chamber is preheated before the semiconductor structure is placed in the processing chamber. After the semiconductor structure is placed in the preheated processing chamber, a reaction medium (such as nitrogen, etc.) is input into the processing chamber, and the surface of the first barrier layer 240 of the semiconductor structure is plasma treated using the reaction medium. After the treatment is completed, the processing chamber in which the semiconductor structure is placed is cooled, and finally the cooled semiconductor structure is taken out of the processing chamber. In other embodiments, for the step of "passivation treatment", when other types of plasma treatment processes or other types of passivation processes are used, the specific steps and processes of the passivation treatment can also be flexibly selected, and are not limited to this embodiment.

[0102] Specifically, Figure 7 As shown, it specifically shows an enlarged layered structure of a semiconductor bit line, which can be used as a representative example of the bit line structure in the step of "forming a sacrificial layer 250" in this embodiment. The sacrificial layer 250 is formed on the surface of the first barrier layer 240 after passivation treatment. In addition, the filling portion 251 of the sacrificial layer 250 is filled in the groove 211 (the portion where the first protective layer 230 and the first barrier layer 240 are not formed). That is, in the portion of the groove cavity of the groove 211 where the bit line conductive layer 220 (bit line plug 222) is not provided, the groove wall and part of the groove bottom are sequentially formed with the first protective layer 230 and the first barrier layer 240, and the rest of the groove cavity of this part is filled with the sacrificial layer 250 (filling portion 251). On this basis, the bit line plug spacer 260 is formed in the groove 211 on both sides of the bit line plug 222 of the semiconductor structure. The bit line plug spacer 260 includes a first protection layer 230, a first barrier layer 240 and an unremoved sacrificial layer 250 (filling portion 251). In this embodiment, the material of the sacrificial layer 250 may be, but is not limited to, silicon nitride (when the material of the first protection layer 230 also includes silicon nitride, the silicon nitride of the sacrificial layer 250 is Outer SiN).

[0103] As mentioned above, since the present invention performs a passivation treatment on the first barrier layer 240 before forming the sacrificial layer 250, the etching selectivity ratio between the sacrificial layer 250 and the first barrier layer 240 is increased. Specifically, the specific meaning of the above etching selectivity ratio includes: the ratio of the etching rate of the etching liquid on the former to the etching rate of the etching liquid on the latter under the same etching conditions. Accordingly, the "etching selectivity ratio between the sacrificial layer 250 and the first barrier layer 240" is the etching rate of the etching liquid on the sacrificial layer 250 and the etching rate of the etching liquid on the first barrier layer 240, and the increase in this ratio is equivalent to a faster etching rate of the etching liquid on the sacrificial layer 250 under the same etching conditions. Therefore, in a subsequent etching and cleaning step of "cleaning and removing the sacrificial layer 250", the present invention can achieve the cleaning and removal of the sacrificial layer 250, and can reduce or avoid the etching of the first barrier layer 240, thereby protecting the first protective layer 230 (usually comprising the same material as the sacrificial layer 250, such as silicon nitride) inside the first barrier layer 240 from being etched away, thereby protecting the bit line conductive layer 220 inside the first protective layer 230 from being etched away.

[0104] Specifically, Figure 8As shown, it specifically shows an enlarged layered structure of a semiconductor bit line, which can be used as a representative example of the bit line structure in the step of "cleaning and removing the sacrificial layer 250" in this embodiment. Among them, this step is to use an etching solution to wet clean the semiconductor structure after the sacrificial layer 250 is formed, so that the remaining parts of the sacrificial layer 250 except the filling part 251 are etched away by the etching solution. Accordingly, after the sacrificial layer 250 is cleaned and removed, the groove 211 of the semiconductor structure is still fully filled with the first protective layer 230, the first barrier layer 240 and the filling part 251 of the sacrificial layer 250, which has the effect of preventing the occurrence of defects such as short circuits to the greatest extent. At this point, the semiconductor bit line is basically prepared.

[0105] Preferably, in this embodiment, for the step of "cleaning and removing the sacrificial layer 250", the etching liquid may preferably include a phosphoric acid solution. In other embodiments, the etching liquid may also be other types of etching liquids or solutions, and is not limited to this embodiment.

[0106] Preferably, in the present embodiment, for the step of "cleaning and removing the sacrificial layer 250", taking the etching solution including phosphoric acid solution as an example, the temperature of the etching solution can be preferably 100°C to 120°C, such as 100°C, 105°C, 110°C, 120°C, etc. In other embodiments, the temperature of the etching solution can also be less than 100°C, or can be greater than 120°C, such as 95°C, 125°C, 150°C, 160°C, etc., and is not limited to the present embodiment. It should be noted that since the present invention adopts the process step of passivating the first barrier layer 240, the etching selectivity ratio of the sacrificial layer 250 formed by the subsequent process to the first barrier layer 240 is increased, and the temperature of the etching solution used in the present invention is lower than the temperature of the etching solution in the existing process to achieve a greater etching selectivity ratio. Of course, in other embodiments, the present invention can also adopt the temperature of the etching solution similar to the existing process. That is, the preferred range of the temperature of the etching solution in the present embodiment is actually not achievable by the existing process, rather than a simple selection of the data range.

[0107] Preferably, in the present embodiment, for the step of "cleaning and removing the sacrificial layer 250", taking the etching solution including phosphoric acid solution as an example, the concentration of the etching solution can be preferably 40% to 60% °C, such as 40%, 45%, 50%, 60%, etc. In other embodiments, the concentration of the etching solution can also be less than 40%, or can be greater than 60%, such as 38%, 65%, 70%, 85%, etc., and is not limited to the present embodiment. It should be noted that since the present invention adopts the process step of passivating the first barrier layer 240, the etching selectivity ratio of the sacrificial layer 250 formed by the subsequent process to the first barrier layer 240 is increased, and the concentration of the etching solution used in the present invention can be less than the concentration of the etching solution in the existing process to achieve a greater etching selectivity ratio. Of course, in other embodiments, the present invention can also adopt an etching solution concentration similar to that of the existing process. That is, the preferred range of the concentration of the etching solution in the present embodiment is actually not achievable by the existing process, rather than a simple selection of the data range.

[0108] Preferably, in this embodiment, for the step of “cleaning and removing the sacrificial layer 250”, etching and cleaning the sacrificial layer 250 may preferably include the following specific steps:

[0109] Pre-cleaning the surface of the sacrificial layer 250 using a diluted hydrofluoric acid solution to remove the oxide layer on the surface of the sacrificial layer 250; and

[0110] The sacrificial layer 250 is cleaned with a phosphoric acid solution, and the portion of the sacrificial layer 250 other than the filling portion 251 is removed.

[0111] As mentioned above, in a specific process, after the sacrificial layer 250 is formed on the surface of the first barrier layer 240, since the sacrificial layer 250 is exposed and in contact with the air, a native oxide layer may be formed on the surface of the sacrificial layer 250. In this regard, the present invention can effectively remove the native oxide layer formed on the surface of the sacrificial layer 250 by adding a pre-cleaning step before cleaning the sacrificial layer 250 with an etching solution, so that the cleaning and removal of the sacrificial layer 250 with an etching solution is more effective, and the stability and controllability of the process are better.

[0112] Furthermore, for the specific step of etching and cleaning the sacrificial layer 250, a tank wet process machine can be preferably used. Specifically, the surface of the sacrificial layer 250 can be pre-cleaned for 5s to 15s using a hydrofluoric acid solution diluted at 200:1. Then, the pre-cleaned semiconductor structure is placed in a tank wet process machine and tank wet-cleaned using a low-temperature, low-concentration (e.g., a temperature of 100°C to 120°C, a concentration of 40% to 60%) phosphoric acid solution, and then the dried semiconductor structure is taken out of the tank wet process machine after washing with water and drying with isopropanol.

[0113] As mentioned above, in order to demonstrate the efficacy of the bit line structure manufacturing method proposed in the present invention, the applicant has conducted a large number of experiments and simulation calculations, and the experimental and calculation results can undoubtedly prove the existence of the relevant efficacy of the present invention. The following will combine the comparison between two specific embodiments of the present invention and the existing process to illustrate the relevant efficacy of the present invention.

[0114] Referring to the following Appendix 1, the comparison between the present invention and the existing process is based on the process conditions of "whether to perform pre-cleaning", "concentration of etching solution using phosphoric acid as an example", "temperature of etching solution using phosphoric acid as an example", and "passivation treatment using nitrogen plasma treatment as an example", and the "etching selectivity ratio" of the sacrificial layer and the barrier layer (the first barrier layer in the present invention) of the semiconductor bit line structure obtained by each process is used as the comparison result. On this basis, the existing process: the process of nitrogen plasma treatment of the barrier layer is not adopted, the phosphoric acid concentration is a relatively high 75% to 88%, the phosphoric acid temperature is a relatively high 150°C to 165°C, and the process of pre-cleaning the sacrificial layer is not adopted, and the etching selectivity ratio of the sacrificial layer to the barrier layer obtained is about 5:1. Embodiment 1 of the present invention: the process of nitrogen plasma treatment of the first barrier layer is adopted, the phosphoric acid concentration and phosphoric acid temperature are the same as the existing process, and the process of pre-cleaning the sacrificial layer is also not adopted, and the etching selectivity ratio of the sacrificial layer to the barrier layer obtained is about 16:1. Embodiment 2 of the present invention: A process of nitrogen plasma treatment of the first barrier layer is adopted, the phosphoric acid concentration is a relatively low 40% to 60%, the phosphoric acid temperature is a relatively low 100°C to 120°C, and ultrapure water is used to pre-clean the sacrificial layer, for example, H2O:HF (49%) = 200:1, the time is 10s, and the etching selectivity ratio of the sacrificial layer to the barrier layer obtained is about 32:1. Therefore, it can be clearly known that the semiconductor bit line structure prepared by the bit line structure manufacturing method proposed in the present invention can indeed increase the etching selectivity ratio of the sacrificial layer to the first barrier layer, so that when the thickness of the first barrier layer is small, it can be ensured that the etching solution cleaning and removing the sacrificial layer will not damage the conductive layer in the first barrier layer.

[0115] Existing process Embodiment 1 of the present invention Embodiment 2 of the present invention Pre-cleaning no no DHF 200:1; 10s Phosphoric acid concentration 75％～88％ 75％～88％ 40％～60％ Phosphoric acid temperature 150℃～165℃ 150℃～165℃ 100℃～120℃ <![CDATA[N2 plasma treatment]]> no yes yes Etching selectivity 5:1 16:1 32:1

[0116] Table 1 Comparison of etching selectivity between existing process and embodiment of the present invention

[0117] It should be noted that the bit line structure manufacturing method shown in the drawings and described in this specification is only a few examples of many manufacturing methods that can adopt the principles of the present invention. It should be clearly understood that the principles of the present invention are by no means limited to any details or any steps of the bit line structure manufacturing method shown in the drawings or described in this specification.

[0118] Based on the above detailed description of an exemplary embodiment of the method for manufacturing a bit line structure proposed in the present invention, an exemplary embodiment of the method for manufacturing a semiconductor structure proposed in the present invention will be described below.

[0119] In this embodiment, the semiconductor structure manufacturing method provided by the present invention comprises the following steps:

[0120] Providing a semiconductor substrate, wherein a surface of the semiconductor substrate has a groove;

[0121] By using the method for manufacturing a bit line structure proposed by the present invention and described in the above embodiments, a bit line structure is formed on a semiconductor substrate.

[0122] It should be noted that the method for manufacturing the bit line structure proposed in the present invention, in its respective implementation manners that conform to the inventive concept, can adopt various possible process steps before and after forming the bit line structure to further form the functional structures or process structures required for various semiconductor structures, and is not limited to this implementation manner.

[0123] For example, after forming the bit line structure through the above steps of the semiconductor structure manufacturing method proposed by the present invention, the first barrier layer can be removed, and then functional structures such as the second barrier layer and the second protective layer can be formed in sequence. Moreover, in the steps of forming the above functional structures, it can still be achieved through processes such as deposition (Dep) and etching (Etch), and in the process of performing the above processes, patterning and other processes can still be achieved through process layered structures such as silicon oxide and silicon nitride, which are not limited to this embodiment. By removing the first barrier layer and then forming the second barrier layer and the second protective layer again, it is possible to avoid the adverse effects on the semiconductor structure caused by the surface damage formed on the first barrier layer when removing the sacrificial layer.

[0124] It should be noted that the semiconductor structure manufacturing methods shown in the drawings and described in this specification are only a few examples of many manufacturing methods that can adopt the principles of the present invention. It should be clearly understood that the principles of the present invention are by no means limited to any details or any steps of the semiconductor structure manufacturing methods shown in the drawings or described in this specification.

[0125] Based on the above detailed description of an exemplary embodiment of the method for manufacturing a bit line structure and a method for manufacturing a semiconductor structure proposed by the present invention, the following will be referred to in conjunction with Figure 8 , an exemplary implementation of the semiconductor structure proposed by the present invention is described.

[0126] In this embodiment, the semiconductor structure proposed by the present invention is manufactured by the semiconductor structure manufacturing method proposed by the present invention and described in the above embodiments.

[0127] like Figure 8As shown, the semiconductor structure proposed by the present invention includes a semiconductor substrate 210, a bit line conductive layer 220, and a bit line plug spacer 260. The surface of the semiconductor substrate 210 has a groove 211. The bit line conductive layer 220 is partially located in the groove 211 on the surface of the semiconductor substrate. The bit line plug spacer 260 is filled in the groove, and the bit line plug spacer includes a first protection layer 230, a first barrier layer 240 after passivation treatment, and a filling portion 251.

[0128] Preferably, in this embodiment, the thickness of the first protection layer 230 may be 1 nm to 3 nm.

[0129] Preferably, in this embodiment, the thickness of the first barrier layer 240 may be preferably 2 nm to 8 nm.

[0130] Preferably, in this embodiment, the material of the first protection layer 230 may preferably include silicon nitride.

[0131] Preferably, in this embodiment, the material of the first barrier layer 240 may preferably include silicon oxide.

[0132] Preferably, in this embodiment, the material of the filling portion 251 may preferably include silicon nitride.

[0133] Preferably, in this embodiment, the first barrier layer 240 after passivation treatment includes a two-layer thin film structure, namely a first thin film layer 241 adjacent to the first protective layer 230 and a second thin film layer 242 away from the first protective layer 230; wherein the etching selectivity ratio of the filling portion 251 to the second thin film layer 242 is greater than the etching selectivity ratio of the filling portion 251 to the first thin film layer 241.

[0134] Preferably, in this embodiment, the material of the first thin film layer 241 includes silicon oxide, and the material of the second thin film layer 242 includes silicon oxynitride.

[0135] It should be noted that the semiconductor structures shown in the drawings and described in this specification are only a few examples of the many types of semiconductor structures that can employ the principles of the present invention. It should be clearly understood that the principles of the present invention are by no means limited to any details or any components of the semiconductor structures shown in the drawings or described in this specification.

[0136] In summary, the present invention performs a passivation treatment on the first barrier layer, so that the etching selectivity ratio of the etching solution to the sacrificial layer and the first barrier layer is increased, so that when the etching solution is used to clean and remove the sacrificial layer, the conductive layer in the first barrier layer will not be damaged. Moreover, on the basis of achieving the above effects, compared with the existing process, the present invention does not need to add an active agent to the etching solution, so the cleaning process of the present invention is relatively simple and will not affect the product yield. In addition, the present invention does not need to increase the thickness of the first barrier layer, and can further meet the design requirements of miniaturization and thinning of the key dimensions of semiconductor products.

[0137] The above describes and / or illustrates in detail the exemplary embodiments of the method for manufacturing a bit line structure, a method for manufacturing a semiconductor structure, and a semiconductor structure proposed in the present invention. However, the embodiments of the present invention are not limited to the specific embodiments described herein. On the contrary, the components and / or steps of each embodiment can be used independently and separately from other components and / or steps described herein. Each component and / or each step of an embodiment can also be used in combination with other components and / or steps of other embodiments. When introducing the elements / components / etc. described and / or illustrated herein, the terms "one", "one" and "above" are used to indicate the presence of one or more elements / components / etc. The terms "comprising", "including" and "having" are used to indicate the meaning of open inclusion and mean that in addition to the listed elements / components / etc., there may be other elements / components / etc. In addition, the terms "first" and "second" in the claims and the specification are used only as marks and are not numerical restrictions on their objects.

[0138] Although the bit line structure manufacturing method, semiconductor structure manufacturing method and semiconductor structure proposed in the present invention have been described according to different specific embodiments, those skilled in the art will recognize that the implementation of the present invention can be modified within the spirit and scope of the claims.

Claims

1. A method for manufacturing a bit line structure, It is characterized in that The following steps are involved: Forming a bit line conductive layer on the surface of the semiconductor substrate, wherein a portion of the bit line conductive layer is located in a groove on the surface of the semiconductor substrate; forming a first protective layer on the surface of the bit line conductive layer and the semiconductor substrate; forming a first barrier layer on a surface of the first protective layer; Passivating the surface of the first barrier layer, wherein the first barrier layer after the passivation treatment comprises a first thin film layer and a second thin film layer, wherein the material of the first thin film layer comprises silicon oxide, and the material of the second thin film layer comprises silicon oxynitride; forming a sacrificial layer on a surface of the first barrier layer, the sacrificial layer having a filling portion filled in the groove; and The sacrificial layer is cleaned and removed with an etching solution except for the filling portion.

2. The method for manufacturing a bit line structure according to claim 1, It is characterized in that The passivation treatment includes plasma treatment, ion implantation or thermal oxidation treatment.

3. The method for manufacturing a bit line structure according to claim 1, It is characterized in that The first thin film layer is adjacent to the first protective layer, and the second thin film layer is far away from the first protective layer; wherein an etching selectivity ratio between the sacrificial layer and the second thin film layer is greater than an etching selectivity ratio between the sacrificial layer and the first thin film layer.

4. The method for manufacturing a bit line structure according to claim 3, It is characterized in that The material of the first barrier layer includes silicon oxide; wherein the passivation treatment includes nitrogen plasma treatment.

5. The method for manufacturing a bit line structure according to claim 1, It is characterized in that The thickness of the first protective layer is 1 nm to 3 nm; and / or the thickness of the first barrier layer is 2 nm to 8 nm.

6. The method for manufacturing a bit line structure according to claim 1, It is characterized in that The material of the first protection layer includes silicon nitride; and / or the material of the first barrier layer includes silicon oxide; and / or the material of the sacrificial layer includes silicon nitride.

7. The method for manufacturing a bit line structure according to claim 1, It is characterized in that The etching solution comprises a phosphoric acid solution; wherein the temperature of the etching solution is 100° C. to 120° C.; and / or the concentration of the etching solution is 40% to 60%.

8. The method for manufacturing a bit line structure according to claim 1, It is characterized in that After the etching solution is used to clean and remove the portion of the sacrificial layer other than the filling portion, the method further comprises the following steps: removing the exposed first barrier layer; forming a second barrier layer on the surface of the bit line conductive layer and the semiconductor substrate; A second protective layer is formed on a surface of the second barrier layer.

9. The method for manufacturing a bit line structure according to claim 1, It is characterized in that When the sacrificial layer is removed by cleaning with the etching solution, the following steps are included: Pre-cleaning the surface of the sacrificial layer using a diluted hydrofluoric acid solution to remove an oxide layer on the surface of the sacrificial layer; as well as The sacrificial layer is cleaned with a phosphoric acid solution to remove a portion of the sacrificial layer except the filling portion.

10. A method for manufacturing a semiconductor structure, It is characterized in that The following steps are involved: providing a semiconductor substrate, wherein a surface of the semiconductor substrate has a groove; and Using the method for manufacturing a bit line structure according to any one of claims 1 to 9, a bit line structure is formed on the semiconductor substrate.

11. The method for manufacturing a semiconductor structure according to claim 10, It is characterized in that The passivation treatment includes plasma treatment; wherein the passivation treatment of the first barrier layer includes the following steps: preheating a processing chamber of a processing device; placing the semiconductor structure having the first barrier layer formed thereon into a processing chamber; Inputting a reaction medium and performing plasma treatment on the surface of the first barrier layer; cooling the processing chamber; and The semiconductor structure is removed.

12. A semiconductor structure, It is characterized in that Include: A semiconductor substrate, wherein a surface of the semiconductor substrate has a groove; A bit line conductive layer, wherein a portion of the bit line conductive layer is located in a groove on the surface of the semiconductor substrate; A bit line plug spacer layer is filled in the groove, and the bit line plug spacer includes a first protective layer, a first barrier layer after passivation treatment, and a filling portion, wherein the first barrier layer after passivation treatment includes a first thin film layer and a second thin film layer, the material of the first thin film layer includes silicon oxide, and the material of the second thin film layer includes silicon oxynitride.

13. The semiconductor structure according to claim 12, It is characterized in that The thickness of the first protective layer is 1 nm to 3 nm; and / or the thickness of the first barrier layer is 2 nm to 8 nm.

14. The semiconductor structure according to claim 12, It is characterized in that The material of the first protective layer includes silicon nitride; and / or the material of the first barrier layer includes silicon oxide; and / or the material of the filling portion includes silicon nitride.

15. The semiconductor structure according to claim 12, It is characterized in that The first thin film layer is adjacent to the first protective layer, and the second thin film layer is far away from the first protective layer; wherein an etching selectivity ratio between the filling portion and the second thin film layer is greater than an etching selectivity ratio between the filling portion and the first thin film layer.

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