A CHI protocol anti-blocking interconnection method, system, device and storage medium

Abstract

The present invention proposes a CHI protocol anti-blocking interconnection method, including: establishing a request counter at the request end of the CHI protocol transmission link; in response to the request end sending a data transmission request, adding 1 to the value of the request counter, and judging whether the value of the request counter is equal to a predetermined value; in response to the counter value being equal to the predetermined value, prohibiting the request end from sending a data transmission request. Through the above method, a request counter and a buffer are respectively established on the hardware circuits of the request end and the response end of the CHI protocol transmission link, and the number of requests in the transmission link is controlled by the buffer and the counter. While keeping the chip circuit scale unchanged, the ratio of the cache congestion path of each level of components is reduced, and when the circuit continues to work effectively for a long time, the system access efficiency is greatly improved. The resources of circuit design are optimized, the circuit structure is simplified, the complexity of the chip back-end design is reduced, and the complexity of the entire chip system design is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of computers, and in particular relates to a CHI protocol anti-blocking interconnection method, system, device and storage medium. Background Art

[0002] With the rapid development of cloud computing in recent years, the scale of multi-way servers has been increasing, and the application of multi-way servers has become more and more extensive. With good stability, high security, and high computing efficiency, they have been widely used in almost all production and life fields. With the continuous development of server application fields, the application demand for high-end servers has entered an important stage. Complex architecture implementation supports high-performance indicators of high-end server systems, namely high security, high availability, and high reliability.

[0003] The network control chip controls the multi-channel processor system so that the message transmission inside the system can achieve the purpose of high efficiency, reliability, safety and stability. The present invention relates to the field of chip design, and specifically to a novel implementation method for non-blocking scheduling of access queues on a data path in a multi-ARM processor node network, in the process of implementing the access of a network control protocol chip to a processor cache. For the design of such control chips, efficient scheduling of multi-channel high-speed messages is very necessary. Based on the CHI protocol of the ARM processor, through efficient scheduling, requests need to be cached when passing through each component node, and then decide whether to forward the data to the next level according to the processing capacity of the next-level component, and finally transmit it to the request target node. For large-scale high-speed protocol processors, the amount of data processed per unit time is quite large, and there is no necessary correlation. The conventional method causes the cache of each component to reach the upper limit of the processing capacity, resulting in a very high rate of path congestion. The traditional method based on CHI protocol processing can no longer meet the requirements, which will have a greater negative impact on the overall performance of the system. Summary of the invention

[0004] To solve the above problems, the present invention proposes a CHI protocol anti-blocking interconnection method, comprising:

[0005] Establish a request counter at the requesting end of the CHI protocol transmission link;

[0006] In response to the request end sending a data transmission request, adding 1 to the value of the request counter, and determining whether the value of the request counter is equal to a predetermined value;

[0007] In response to the value of the counter being equal to a predetermined value, the requesting end is prohibited from sending a data transmission request.

[0008] In some embodiments of the invention, the method further comprises:

[0009] Establishing a first cache at a responding end of the CHI protocol transmission link;

[0010] Monitor the response status of the data transmission request received by the responder, and save the response status of the data transmission request in the first cache.

[0011] In some embodiments of the invention, the method further comprises:

[0012] Monitoring the data transmission completion confirmation information sent by the requesting end;

[0013] In response to the request end sending the data transmission completion confirmation information, reducing the value of the request counter of the request end by 1; and

[0014] Monitoring the data transmission completion confirmation information received by the responding end;

[0015] In response to the responding end receiving the data transmission completion confirmation information, releasing the response status record corresponding to the data transmission completion confirmation information from the first cache.

[0016] In some embodiments of the invention, the method further comprises:

[0017] The number of the data transmission requests that can be recorded by the first cache is obtained, and a predetermined value of the request counter is set according to the number of the data transmission requests that can be recorded by the first cache.

[0018] In some implementations of the present invention, setting the predetermined value of the request counter according to the number of the data transmission requests that can be recorded by the first cache includes:

[0019] The number of the data transmission requests that can be recorded by the first cache minus 1 is used as the predetermined value of the request counter.

[0020] In some implementations of the present invention, setting the predetermined value of the request counter according to the number of the data transmission requests that can be recorded by the first cache further includes:

[0021] The total number of the data transmission requests that can be recorded by the first cache of the plurality of responding ends is obtained, and the total number of the data transmission requests that can be recorded by the first cache is reduced by 1 as a predetermined value of the request counter of the requesting end.

[0022] In some embodiments of the present invention, obtaining the total number of the data transmission requests that can be recorded by the first cache of the plurality of responding ends, and subtracting 1 from the total number of the data transmission requests that can be recorded by the first cache as the predetermined value of the request counter of the requesting end includes:

[0023] In response to the fact that there are multiple requesting ends, the values ​​of the request counters of the multiple requesting ends are synchronized, and the predetermined values ​​of the multiple request counters are set to the total number of the data transmission requests that can be recorded by the multiple responding ends minus the number of the multiple requesting ends.

[0024] In some embodiments of the invention, the method further comprises:

[0025] A second cache is established at the request end, and in response to the request counter prohibiting the request end from sending a data transmission request, the data transmission request is cached in the second cache.

[0026] In response to the value of the request counter being lower than a predetermined value, obtaining a data transmission request from the second cache and issuing it.

[0027] Another aspect of the present invention further provides a computer device, comprising:

[0028] at least one processor; and

[0029] A memory, wherein the memory stores computer instructions that can be executed on the processor, and when the instructions are executed by the processor, the steps of the method described in any one of the above-mentioned embodiments are implemented.

[0030] Another aspect of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any one of the methods described in the above-mentioned embodiments are implemented.

[0031] The present invention provides a CHI protocol anti-blocking interconnection method, wherein a request counter and a buffer are respectively established on the hardware circuits of the request end and the response end of the transmission link of the CHI protocol, and the number of requests in the transmission link is controlled by the buffer and the counter. This helps to reduce the ratio of cache congestion paths of components at all levels while keeping the chip circuit scale unchanged, and greatly improves the system access efficiency when the circuit continues to work effectively for a long time. It optimizes the resources of circuit design, simplifies the circuit structure, reduces the complexity of chip back-end design, and reduces the complexity of the entire chip system design as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1A method flow chart of an embodiment of a CHI protocol anti-blocking interconnection method provided by an embodiment of the present invention;

[0034] Figure 2 A schematic diagram of the structure of a computer device provided by an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of the structure of a computer storage medium provided by an embodiment of the present invention.

[0036] Figure 4 It is an interactive diagram of the data transmission process of CHI link interconnection in the prior art;

[0037] Figure 5 It is an interactive diagram of the data transmission process of the CHI protocol anti-blocking interconnection method optimized by the present invention;

[0038] Figure 6 A structural diagram of a transmission link implemented by a CHI protocol anti-blocking interconnection method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0040] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two non-identical entities with the same name or non-identical parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. The subsequent embodiments will not explain this one by one.

[0041] The method disclosed in the present invention is applied to the CHI protocol link of the ARM platform. The CHI protocol is the fifth generation protocol of AMBA (AMBA bus is a special mechanism (Advanced Microcontroller Bus Architecture) developed by ARM, which can integrate RISC processors into other IP cores and peripherals. It is not an interface between chips and peripherals, but an interface for the ARM core (CPU) to communicate with other components on the chip.) It is an evolved version of the ACE protocol. All information transmission is completed in the form of packets. The packet is divided into different fields to transmit different information. In essence, it is still used to solve the data consistency problem between multiple CPUs (RN, Request Node, request node, in the present invention refers to the device or CPU core that initiates the data transmission request, that is, the CPU core on the CHI link accesses other devices (usually refers to storage devices)). That is, the CHI protocol realizes the access of multiple CPUs to memory data. In the prior art, a cache congestion response mechanism is usually adopted, such as Figure 4 As shown, when the cache resources of the (ICN, Information-Centric Networking, which can realize the response of data access to multiple RN nodes)) receiving the request are exhausted, when the (ICN) cache resources receive the request again, it will send a RetryAck message to the node (RN) that initiated the request as a response to the request. After receiving the response, the requesting node remains in a state of waiting to send the request again until the (ICN) sends a PCrdGrant message to the (RN), and then the (RN) can resend the request to the (ICN). This scheme adopts the most common implementation method, that is, when the receiving cache of the receiving end (ICN) is insufficient, a retransmission feedback method is adopted to ensure that the request sent by the (RN) will not be lost when it cannot be received by the (ICN), and the request remains in the retransmission state in the RN, waiting for the ICN cache to be able to receive the request, and then a message allowing the request to be sent is sent. After receiving the message, the (RN) can once again send the request that was not successfully sent from the (RN).

[0042] This design implementation method, when a retransmission scenario occurs, such as Figure 4 As shown, since the retransmission information RetryAck and the re-authorization information PCrdGrant must be sent from the (ICN) node to the (RN) node through the system bus, combined with Figure 5As shown, the process of retransmission and re-authorization of sending request is added in the process from (RN) initiating a request to (RN) receiving a response and returning CompAck. This process itself will cause additional delay on the system bus, and due to the increase in the number of requests and responses exchanged between RN and ICN, more system bus bandwidth will be occupied, thereby affecting the efficiency of other nodes using the system bus bandwidth. In addition, due to the addition of the mechanism of retransmission and re-authorization of sending request, in the circuit function design of RN and ICN nodes, more circuit resource overhead needs to be added to meet the implementation needs of the retransmission function in this special case, which greatly increases the complexity of the design and the demand for design resources.

[0043] To solve the above problems, Figure 1 As shown, the present invention proposes a CHI protocol anti-blocking interconnection method, comprising:

[0044] Step S1, establishing a request counter at the requesting end of the CHI protocol transmission link;

[0045] Step S2, in response to the request end sending a data transmission request, adding 1 to the value of the request counter, and determining whether the value of the request counter is equal to a predetermined value;

[0046] Step S3: In response to the value of the counter being equal to a predetermined value, prohibiting the requesting end from sending a data transmission request.

[0047] In the embodiment of the present invention, in step S1, a request counter is established at the requesting end of the CHI protocol transmission link, such as Figure 6 As shown, the request end is Figure 6 The RN node in the CHI protocol link generates a read-write protocol transmission message and sends it to the ICN of the CHI protocol transmission link. Therefore, the present invention implements a counter Tx Counter (Transport Counter, request end counter) at the sending port of the RN node through hardware logic.

[0048] In step S2, the sending of transmission requests on the RN node is monitored by the request counter Tx Counter established on the RN node. When the RN node sends a data transmission request, the value of Tx Counter is accumulated by 1, and it is determined whether the accumulated value is equal to a predetermined size.

[0049] In step S3, if the value of Tx Counter is equal to a predetermined value, Tx Counter will prohibit the sending port on the RN node from sending a data transmission request.

[0050] In some embodiments of the invention, the method further comprises:

[0051] Establishing a first cache at a responding end of the CHI protocol transmission link;

[0052] Monitor the response status of the data transmission request received by the responder, and save the response status of the data transmission request in the first cache.

[0053] In this embodiment, if Figure 6 As shown, in addition to establishing a request counter TxCounter at the RN node of the CHI protocol transmission link, at the responding end of the CHI protocol transmission link, that is, Figure 6 The ICN node in the figure also establishes a first buffer for caching the data transmission request received and being processed by the ICN node through hardware logic, namely, Rx ReqBuffer (Receive Request Buffer) in the figure. After processing the data transmission request received by the ICN node, a record is established in the Rx Req Buffer according to the unique identifier of the data transmission request. The content fields of the record include the following: Figure 5 The four status parameters shown are: Snoopable Read (exclusive access request of CHI protocol), ReadNoSnp (exclusive access request sent by ICN to SN node), CompData (Complete Data data transmission completion mark) and ComAck (Complete Acknowledge character, data transmission completion confirmation character). Among them, Snoopable Read indicates the status of the data transmission request sent from the corresponding RN node, ReadNoSnp indicates whether the ICN node has sent the data transmission request to other storage devices or other node devices at the back end; CompData indicates whether the data from other storage devices or other devices at the back end has been sent to the RN node; CompAck indicates the data transmission completion confirmation information sent by the RN node after verifying the completion of data transmission.

[0054] In some embodiments of the invention, the method further comprises:

[0055] Monitoring the data transmission completion confirmation information sent by the requesting end;

[0056] In response to the request end sending the data transmission completion confirmation information, reducing the value of the request counter of the request end by 1; and

[0057] Monitoring the data transmission completion confirmation information received by the responding end;

[0058] In response to the responding end receiving the data transmission completion confirmation information, releasing the response status record corresponding to the data transmission completion confirmation information from the first cache.

[0059] In this embodiment, in the implementation of the method of the present invention, the data transmission needs to be modified, that is, Figure 6 As shown, when transmitting data, the requesting end, that is, the RN node, sends a corresponding data transmission request Snoopable Read to the responding end ICN node. After receiving it, the ICN sends ReadNoSnp to the SN node (backend memory, or other devices). The SN node processes the request and reads the requested data and sends it to the RN node through the CHI protocol data link bus. After receiving the data content and verifying that it is correct, the RN node sends the transmission completion confirmation information CompAck to the ICN node. The transmission completion confirmation information CompAck is sent by the RN node, and when the request random number counter Tx Counter located in the RN node detects that the transmission completion confirmation information CompAck has been sent, it subtracts 1 from the value of Tx Counter, indicating that one transmission task has been completed in the current transmission task. If there is a restriction on the transmission request sending, the restriction is lifted and the RN node can continue to send requests.

[0060] In addition, at the ICN node, if the ICN node receives the corresponding transmission completion confirmation information CompAck, the corresponding record in the Rx Req Buffer is released according to the transmission completion confirmation information CompAck. At this point, a data transmission task is officially completed.

[0061] In some embodiments of the invention, the method further comprises:

[0062] The number of the data transmission requests that can be recorded by the first cache is obtained, and a predetermined value of the request counter is set according to the number of the data transmission requests that can be recorded by the first cache.

[0063] In this embodiment, as described above, the method provided by the present invention is to control the data transmission on the CHI protocol link in an orderly manner by establishing a request counter Tx Counter and a first buffer Rx Req Buffer at the RN node and the ICN node respectively. However, due to the characteristics of the CHI protocol, the transmission completion confirmation information CompAck and the SnoopableRead of the new transmission request are transmitted through two independent bus paths. Therefore, the order in which these two information messages sent to the ICN node arrive at the ICN node cannot be guaranteed. Therefore, in order to prevent Snoopable Read from arriving at the ICN node earlier than CompAck, the space of RxReq Buffer is not released, and the new Snoopable Read cannot be received, and the Retry phenomenon occurs, it is necessary to set a preset value for the number of data transmission requests that can be recorded according to Rx Req Buffer. Specifically, after the RN node is connected to the corresponding CHI protocol data link, the maximum number of records of its Rx Req Buffer is obtained from the corresponding ICN node that needs to be accessed, and the maximum count value of Tx Counter is set according to the maximum number of records.

[0064] In some implementations of the present invention, setting the predetermined value of the request counter according to the number of the data transmission requests that can be recorded by the first cache includes:

[0065] The number of the data transmission requests that can be recorded by the first cache minus 1 is used as the predetermined value of the request counter.

[0066] In this embodiment, as mentioned above, the maximum count value of the Tx Counter of the RN node is preferably set to the maximum number of records in the RxReq Buffer minus one. Specifically, if the maximum number of records in the Rx Req Buffer is N, that is, Figure 6As shown, the Rx Req Buffer has space for entry0-entryN (0-N records). Therefore, the Tx Counter control threshold is controlled by 1 less the ICN request processing capability, that is, the RN node is limited to send out a maximum of N-1 requests. In this way, even if the out-of-order situation described above occurs (Snoopable Read is earlier than CompAck), since the ICN cache has an extra free entry for the new request, the new data transmission request (Snoopable Read) will not be retried. After the new data transmission request is saved in the ICN for processing, CompAck arrives again, and the entry occupied by the completed data transmission request is released. The Rx Req Buffer of the ICN still maintains an entry free state, and also implements the caching of the new data transmission request, without causing the occurrence of the Retry (retry, in the present invention, refers to the resending of the data transmission request) scenario.

[0067] In some implementations of the present invention, setting the predetermined value of the request counter according to the number of the data transmission requests that can be recorded by the first cache further includes:

[0068] The total number of the data transmission requests that can be recorded by the first cache of the plurality of responding ends is obtained, and the total number of the data transmission requests that can be recorded by the first cache is reduced by 1 as a predetermined value of the request counter of the requesting end.

[0069] In this embodiment, if one RN node sends data requests to multiple ICN nodes, when setting the Tx Counter of the RN node, a request for obtaining the maximum number of records in the Rx Req Buffer is sent to multiple ICN nodes, and the maximum number of records in the Rx Req Buffer of the multiple ICN nodes is added and then subtracted by 1 to obtain the maximum value of the Tx Counter.

[0070] In some embodiments of the present invention, obtaining the total number of the data transmission requests that can be recorded by the first cache of the plurality of responding ends, and subtracting 1 from the total number of the data transmission requests that can be recorded by the first cache as the predetermined value of the request counter of the requesting end includes:

[0071] In response to the fact that there are multiple requesting ends, the values ​​of the request counters of the multiple requesting ends are synchronized, and the predetermined values ​​of the multiple request counters are set to the total number of the data transmission requests that can be recorded by the multiple responding ends minus the number of the multiple requesting ends.

[0072] In this embodiment, in a data transmission scenario where there are multiple RN nodes to multiple ICN nodes, when setting the maximum value of Tx Counter on multiple ICN nodes, it is necessary to consider the situation where multiple RN nodes send data transmission requests in parallel. In this embodiment, the values ​​of Tx Counter of multiple RN nodes are synchronized through the CHI protocol link, that is, the values ​​of Tx Counter of multiple RN nodes are kept the same, and each RN node sends a data transmission request, and the values ​​of Tx Counter of all RN nodes are accumulated by 1. At the same time, after each RN node sends the transmission completion confirmation information CompAck, the values ​​of Tx Counter on all RN nodes are reduced by 1. And when setting the maximum value of Tx Counter of multiple RN nodes, after obtaining the total number N' of the maximum number of records N of multiple ICN nodes, the maximum value of Tx Counter is set to the value after N' minus the number of RN nodes, that is, if the number of RN nodes is 5 and the maximum number of records of 5 ICN nodes is 100, the maximum value of TxCounter is 5*100-5=495.

[0073] In some embodiments of the present invention, if the synchronization method for Tx Counters of multiple RN nodes is to send potential changes to Tx Counters of other RN nodes through a hardware circuit when accumulating the value of each TX Counter, that is, a strong synchronization method, it is not necessary to subtract the number of RN nodes according to the above method to set the maximum value of Tx Counter. If synchronization is performed by sending corresponding data to increase the value of Tx Counter in the CHI link protocol, the number of RN nodes needs to be subtracted to set the maximum value of Tx Counter.

[0074] In some embodiments of the invention, the method further comprises:

[0075] Establishing a second cache at the requesting end, and caching the data transmission request in the second cache in response to the request counter prohibiting the requesting end from sending a data transmission request; and

[0076] In response to the value of the request counter being lower than a predetermined value, obtaining a data transmission request from the second cache and issuing it.

[0077] In this embodiment, if Figure 6As shown in the figure, in the RN node, there is also a Tx Req Buffer (Transport Request Buffer, transmitter request buffer) for caching the data transmission requests received by the RN node. When the value of the request counter TxCounter reaches the maximum value and the RN node is prohibited from sending data transmission requests, the data transmission requests received by the RN node can be cached in the Tx Req Buffer.

[0078] In some embodiments of the present invention, the Tx Counter control rules are as follows:

[0079] 1. The upper limit threshold of Tx Counter is N - 1, the number of ICN receive caches (except when there are multiple RN nodes).

[0080] 2. Tx Counter starts counting from 0. When Tx Counter < N - 1, if there is a Req request to be sent in the Tx Req Buffer, then Tx Counter will read the request from this Buffer cache and send the request to the ICN, and at the same time increment the count in Tx Counter by 1.

[0081] 3. When Tx Counter detects a CompAck sent from the RN to the ICN, it will decrement the count in Tx Counter by 1.

[0082] 4. If the two events of sending a Req request and detecting a CompAck occur simultaneously, the count in Tx Counter remains unchanged.

[0083] Through a CHI protocol anti-blocking interconnection method provided by the present invention, a request counter and a buffer are respectively established on the hardware circuits of the request end and the response end of the transmission link of the CHI protocol, and the request quantity in the transmission link is controlled through the buffer and the counter. This helps to reduce the ratio of the congested paths of the caches of each component while keeping the scale of the chip circuit unchanged, and greatly improves the system access efficiency when the circuit works effectively for a long time. It optimizes the resources of the circuit design, simplifies the circuit structure, reduces the complexity of the chip backend design, and overall reduces the complexity of the entire chip system design.

[0084] As Figure 2 shown, another aspect of the present invention also proposes a computer device, including:

[0085] At least one processor 21; and

[0086] A memory 22, wherein the memory 22 stores computer instructions 23 that can be run on the processor 21, and when the instructions 23 are executed by the processor 21, a CHI protocol anti-blocking interconnection method is implemented, including:

[0087] Establish a request counter at the requesting end of the CHI protocol transmission link;

[0088] In response to the request end sending a data transmission request, adding 1 to the value of the request counter, and determining whether the value of the request counter is equal to a predetermined value;

[0089] In response to the value of the counter being equal to a predetermined value, the requesting end is prohibited from sending a data transmission request.

[0090] In some embodiments of the invention, the method further comprises:

[0091] Establishing a first cache at a responding end of the CHI protocol transmission link;

[0092] Monitor the response status of the data transmission request received by the responder, and save the response status of the data transmission request in the first cache.

[0093] In some embodiments of the invention, the method further comprises:

[0094] Monitoring the data transmission completion confirmation information sent by the requesting end;

[0095] In response to the request end sending the data transmission completion confirmation information, reducing the value of the request counter of the request end by 1; and

[0096] Monitoring the data transmission completion confirmation information received by the responding end;

[0097] In response to the responding end receiving the data transmission completion confirmation information, releasing the response status record corresponding to the data transmission completion confirmation information from the first cache.

[0098] In some embodiments of the invention, the method further comprises:

[0099] The number of the data transmission requests that can be recorded by the first cache is obtained, and a predetermined value of the request counter is set according to the number of the data transmission requests that can be recorded by the first cache.

[0100] In some implementations of the present invention, setting the predetermined value of the request counter according to the number of the data transmission requests that can be recorded by the first cache includes:

[0101] The number of the data transmission requests that can be recorded by the first cache minus 1 is used as the predetermined value of the request counter.

[0102] In some implementations of the present invention, setting the predetermined value of the request counter according to the number of the data transmission requests that can be recorded by the first cache further includes:

[0103] The total number of the data transmission requests that can be recorded by the first cache of the plurality of responding ends is obtained, and the total number of the data transmission requests that can be recorded by the first cache is reduced by 1 as a predetermined value of the request counter of the requesting end.

[0104] In some embodiments of the present invention, obtaining the total number of the data transmission requests that can be recorded by the first cache of the plurality of responding ends, and subtracting 1 from the total number of the data transmission requests that can be recorded by the first cache as the predetermined value of the request counter of the requesting end includes:

[0105] In response to the fact that there are multiple requesting ends, the values ​​of the request counters of the multiple requesting ends are synchronized, and the predetermined values ​​of the multiple request counters are set to the total number of the data transmission requests that can be recorded by the multiple responding ends minus the number of the multiple requesting ends.

[0106] In some embodiments of the invention, the method further comprises:

[0107] A second cache is established at the request end, and in response to the request counter prohibiting the request end from sending a data transmission request, the data transmission request is cached in the second cache.

[0108] In response to the value of the request counter being lower than a predetermined value, obtaining a data transmission request from the second cache and issuing it.

[0109] Another aspect of the present invention further provides a computer readable storage medium 401, such as Figure 3 As shown, the computer-readable storage medium 401 stores a computer program 402, and when the computer program 402 is executed by the processor, a CHI protocol anti-blocking interconnection method is implemented, including:

[0110] Establish a request counter at the requesting end of the CHI protocol transmission link;

[0111] In response to the request end sending a data transmission request, adding 1 to the value of the request counter, and determining whether the value of the request counter is equal to a predetermined value;

[0112] In response to the value of the counter being equal to a predetermined value, the requesting end is prohibited from sending a data transmission request.

[0113] In some embodiments of the invention, the method further comprises:

[0114] Establishing a first cache at a responding end of the CHI protocol transmission link;

[0115] Monitor the response status of the data transmission request received by the responder, and save the response status of the data transmission request in the first cache.

[0116] In some embodiments of the invention, the method further comprises:

[0117] Monitoring the data transmission completion confirmation information sent by the requesting end;

[0118] In response to the request end sending the data transmission completion confirmation information, reducing the value of the request counter of the request end by 1; and

[0119] Monitoring the data transmission completion confirmation information received by the responding end;

[0120] In response to the responding end receiving the data transmission completion confirmation information, releasing the response status record corresponding to the data transmission completion confirmation information from the first cache.

[0121] In some embodiments of the invention, the method further comprises:

[0122] The number of the data transmission requests that can be recorded by the first cache is obtained, and a predetermined value of the request counter is set according to the number of the data transmission requests that can be recorded by the first cache.

[0123] In some implementations of the present invention, setting the predetermined value of the request counter according to the number of the data transmission requests that can be recorded by the first cache includes:

[0124] The number of the data transmission requests that can be recorded by the first cache minus 1 is used as the predetermined value of the request counter.

[0125] In some implementations of the present invention, setting the predetermined value of the request counter according to the number of the data transmission requests that can be recorded by the first cache further includes:

[0126] The total number of the data transmission requests that can be recorded by the first cache of the plurality of responding ends is obtained, and the total number of the data transmission requests that can be recorded by the first cache is reduced by 1 as a predetermined value of the request counter of the requesting end.

[0127] In some embodiments of the present invention, obtaining the total number of the data transmission requests that can be recorded by the first cache of the plurality of responding ends, and subtracting 1 from the total number of the data transmission requests that can be recorded by the first cache as the predetermined value of the request counter of the requesting end includes:

[0128] In response to the fact that there are multiple requesting ends, the values ​​of the request counters of the multiple requesting ends are synchronized, and the predetermined values ​​of the multiple request counters are set to the total number of the data transmission requests that can be recorded by the multiple responding ends minus the number of the multiple requesting ends.

[0129] In some embodiments of the invention, the method further comprises:

[0130] A second cache is established at the request end, and in response to the request counter prohibiting the request end from sending a data transmission request, the data transmission request is cached in the second cache.

[0131] In response to the value of the request counter being lower than a predetermined value, obtaining a data transmission request from the second cache and issuing it.

[0132] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0133] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.

[0134] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

Claims

1. A CHI protocol anti-blocking interconnection method, characterized in that: include: Establish a request counter at the requesting end of the CHI protocol transmission link; In response to the request end sending a data transmission request, adding 1 to the value of the request counter, and determining whether the value of the request counter is equal to a predetermined value; In response to the value of the counter being equal to a predetermined value, prohibiting the requesting end from sending a data transmission request; Establishing a first cache at a responding end of the CHI protocol transmission link; Monitoring the response status of the data transmission request received by the responder, and saving the response status of the data transmission request in the first cache; Acquire the number of the data transmission requests that can be recorded by the first cache, and set a predetermined value of the request counter according to the number of the data transmission requests that can be recorded by the first cache; wherein, monitoring the data transmission completion confirmation information sent by the requesting end; In response to the request end sending the data transmission completion confirmation information, reducing the value of the request counter of the request end by 1; and Monitoring the data transmission completion confirmation information received by the responding end; In response to the responding end receiving the data transmission completion confirmation information, releasing the response status record corresponding to the data transmission completion confirmation information from the first cache; The step of setting the predetermined value of the request counter according to the number of the data transmission requests that can be recorded by the first cache includes: The number of the data transmission requests that can be recorded by the first cache minus 1 is used as the predetermined value of the request counter.

2. The method according to claim 1, characterized in that The step of setting the predetermined value of the request counter according to the number of the data transmission requests that can be recorded by the first cache further includes: The total number of the data transmission requests that can be recorded by the first cache of the plurality of responding ends is obtained, and the total number of the data transmission requests that can be recorded by the first cache is reduced by 1 as a predetermined value of the request counter of the requesting end.

3. The method according to claim 2, characterized in that The acquiring the total number of the data transmission requests that can be recorded by the first cache of the plurality of responding ends, and subtracting 1 from the total number of the data transmission requests that can be recorded by the first cache as a predetermined value of the request counter of the requesting end, comprises: In response to the fact that there are multiple requesting ends, the values ​​of the request counters of the multiple requesting ends are synchronized, and the predetermined values ​​of the multiple request counters are set to the total number of the data transmission requests that can be recorded by the multiple responding ends minus the number of the multiple requesting ends.

4. The method according to claim 1, characterized in that Also includes: Establishing a second cache at the requesting end, and caching the data transmission request in the second cache in response to the request counter prohibiting the requesting end from sending a data transmission request; as well as In response to the value of the request counter being lower than a predetermined value, obtaining a data transmission request from the second cache and issuing it.

5. A computer device, characterized in that: include: at least one processor; as well as A memory storing computer instructions executable on the processor, wherein the instructions, when executed by the processor, implement the steps of the method according to any one of claims 1 to 4.

6. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

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