Three-dimensional memory and preparation method thereof

Abstract

The embodiment of the present application provides a three-dimensional memory and a method for preparing the same. The method for preparing the three-dimensional memory includes: forming a step structure having a gate layer on a substrate, and forming a step dielectric layer on the step structure, wherein the step structure includes at least two sub-step structures isolated from each other; forming word line contacts that respectively penetrate the step dielectric layer and extend to each of the sub-step structures, wherein the word line contacts are connected to the gate layer; removing a portion of the step dielectric layer to form a conductive portion, wherein the conductive portion connects the word line contacts in each of the sub-step structures; and forming a first contact on a side of the step dielectric layer away from the substrate, wherein the first contact is connected to the word line contacts in at most a portion of the sub-step structures.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and manufacturing, and more specifically, to a three-dimensional memory (3D NAND) structure and a preparation method thereof. Background Art

[0002] Three-dimensional memory (3D NAND) is a flash memory device with a three-dimensional stacked structure, which is widely used in integrated circuits. As the size of 3D NAND becomes smaller and smaller, the memory preparation process also faces huge challenges, among which the challenge of the step structure process of the storage area is particularly prominent. In the related technology, step areas are usually formed on both sides of the storage array. Each step in the step area is composed of a layer of word line (gate layer) and a layer of dielectric layer overlapping. The word line needs to be led out through the word line contact, so that a vertical word line contact is connected to the word line on each step surface to realize the addressing operation of each word line corresponding to the storage unit.

[0003] In the process of forming the step structure, in order to achieve mutual insulation between adjacent memory arrays, an isolation space is usually reserved between adjacent step structures. At the same time, the word line contacts located on two adjacent step structures are connected to each other by winding through the first contact, which will bring some problems, such as the increase of winding and the increase of masks caused by the increase of winding. In addition, the production cost and process difficulty will also increase. Summary of the invention

[0004] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0005] On the one hand, an embodiment of the present application provides a method for preparing a three-dimensional memory. The method includes: forming a step structure having a gate layer on a substrate, and forming a step dielectric layer on the step structure, wherein the step structure includes at least two sub-step structures isolated from each other; forming word line contacts that respectively penetrate the step dielectric layer and extend to each of the sub-step structures, wherein the word line contacts are connected to the gate layer; removing a portion of the step dielectric layer to form a conductive portion, wherein the conductive portion connects the word line contacts in each of the sub-step structures; and forming a first contact on a side of the step dielectric layer away from the substrate, wherein the first contact is connected to the word line contacts in at most a portion of the sub-step structures.

[0006] In one embodiment, the step structure includes a first sub-step structure and a second sub-step structure isolated from each other; the word line contact includes a first word line contact that penetrates the step dielectric layer and extends to the first sub-step structure, and a second word line contact that penetrates the step dielectric layer and extends to the second sub-step structure; and the conductive portion connects the first word line contact and the second word line contact.

[0007] In one embodiment, the first contact is connected to the first word line contact; or the first contact is connected to the second word line contact.

[0008] In one embodiment, the conductive portion is formed in the step dielectric layer and is in contact with a surface of the step dielectric layer on a side away from the substrate, and there is no contact between the plurality of conductive portions.

[0009] In one embodiment, the first word line contacts, the second word line contacts, and the conductive portions are of the same number.

[0010] In one embodiment, each step in the first sub-step structure is connected to at least one first word line contact, and each step in the second sub-step structure is connected to at least one second word line contact, wherein each step in the first sub-step structure and each step in the second sub-step structure includes the gate layer.

[0011] In one embodiment, the steps of forming the first word line contact and the second word line contact include: forming a first through hole that penetrates the step dielectric layer and extends to the first sub-step structure, and filling the first through hole with a first conductive material to form the first word line contact; and forming a second through hole that penetrates the step dielectric layer and extends to the second sub-step structure, and filling the second through hole with the first conductive material to form the second word line contact.

[0012] In one embodiment, the step of forming the conductive portion includes: removing a portion of the step dielectric layer away from the substrate to form a conductive hole connecting the first word line contact and the second word line contact; and filling a second conductive material in the conductive hole to form the conductive portion.

[0013] In one embodiment, the conductive portion connects the first word line contacts and the second word line contacts located at the same step height in pairs.

[0014] In one embodiment, the step of forming the first contacts includes: providing the same number of first contacts connected to the first word line contacts in pairs.

[0015] In one embodiment, the step of forming the step structure includes: forming a stacked structure having a dielectric layer and a sacrificial layer on the substrate; removing a portion of the stacked structure to form an initial step structure; and removing the sacrificial layer, and filling the gate layer in the space formed after removing the sacrificial layer to form the step structure, wherein a portion of the gate layer located in the first sub-step structure is in contact with and connected to the first word line, and a portion of the gate layer located in the second sub-step structure is in contact with and connected to the second word line.

[0016] In one embodiment, before forming the initial step structure, the method includes: forming a channel hole that penetrates the stacked structure; sequentially forming a blocking layer, a charge capture layer, a tunneling layer and a channel layer in the channel hole to form a channel structure; and after forming the step structure, the channel structure does not penetrate the step structure.

[0017] On the other hand, an embodiment of the present application provides a three-dimensional memory, characterized in that it includes: a step structure, having a gate layer, and including at least two sub-step structures isolated from each other; a step dielectric layer, located on the step structure; a plurality of word line contacts, respectively penetrating the step dielectric layer and extending into each of the sub-step structures; a conductive portion, located in the step dielectric layer, for connecting the word line contacts in each of the sub-step structures; and a first contact, located on a side of the step dielectric layer away from the step structure, and connected to the word line contacts in at most some of the sub-step structures.

[0018] In one embodiment, the step structure includes a first sub-step structure and a second sub-step structure isolated from each other; the word line contact includes a first word line contact that penetrates the step dielectric layer and extends to the first sub-step structure, and a second word line contact that penetrates the step dielectric layer and extends to the second sub-step structure; and the conductive portion connects the first word line contact and the second word line contact.

[0019] In one embodiment, the first contact is connected to the first word line contact; or, the first contact is connected to the second word line contact.

[0020] In one embodiment, the conductive portion is located in the step dielectric layer and is in contact with a surface of the step dielectric layer on a side away from the substrate, and there is no contact between the plurality of conductive portions.

[0021] In one embodiment, the first word line contacts, the second word line contacts, and the conductive portions are of the same number.

[0022] In one embodiment, each step in the first sub-step structure is connected to at least one first word line contact, and each step in the second sub-step structure is connected to at least one second word line contact, wherein each step in the first sub-step structure and each step in the second sub-step structure includes a gate layer.

[0023] In one embodiment, the conductive portion connects the first word line contacts and the second word line contacts located at the same step height in pairs.

[0024] In one embodiment, the memory is 3D NAND memory.

[0025] On the other hand, an embodiment of the present application provides a three-dimensional memory system, including: the memory described in any of the above embodiments; and a controller, electrically connected to the memory and controlling the memory to perform at least one of a read operation, a program operation and an erase operation.

[0026] The three-dimensional memory and the method for preparing the three-dimensional memory provided by the embodiments of the present application may have at least one of the following advantages:

[0027] 1) The method for preparing a three-dimensional memory provided in the embodiment of the present application can reduce the production cost of the device by reducing the metal windings between the conductive contact points without adding additional masks;

[0028] 2) The step structures of the three-dimensional memory provided in the embodiments of the present application do not need to be provided with a bridge structure for reducing delay resistance, and a low stress layer can be selected for filling; and

[0029] 3) The method for preparing the three-dimensional memory provided in the embodiment of the present application can select a lower-priced oxide to partially replace the high-density plasma filling layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other features, purposes and advantages of the embodiments of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0031] Figure 1 A flow chart schematically shows a method for preparing a three-dimensional memory according to an exemplary embodiment of the present application;

[0032] Figure 2 is a schematic diagram of a step structure formed by a three-dimensional memory according to an exemplary embodiment of the present application;

[0033] Figure 3 is a schematic diagram of forming a word line contact of a three-dimensional memory according to an exemplary embodiment of the present application;

[0034] Figure 4A is a schematic diagram of forming a conductive hole in a three-dimensional memory according to an exemplary embodiment of the present application;

[0035] Figure 4B yes Figure 4A A top view of the conductive hole in FIG.

[0036] Figure 5A is a schematic diagram of forming a conductive portion of a three-dimensional memory according to an exemplary embodiment of the present application;

[0037] Figure 5B yes Figure 5A A top view of the conductive hole in FIG.

[0038] Fig. 6A is a schematic diagram of forming a first contact of a three-dimensional memory according to an exemplary embodiment of the present application;

[0039] Figure 6B yes Fig. 6A A top view of the first contact in FIG.

[0040] Figure 7 is a process schematic diagram of a method for preparing a three-dimensional memory in some embodiments; and

[0041] Figure 8 is a schematic diagram of a three-dimensional memory system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to better understand the present application, a more detailed description will be made of various aspects of the embodiments of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first storage area discussed in the embodiments of this application may also be referred to as the second storage area, and the step dielectric layer may also be referred to as the second dielectric layer, and vice versa.

[0044] In the accompanying drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not strictly drawn to scale. For example, the thickness of the step dielectric layer drawn in the drawings in the embodiments of the present application is not in accordance with the proportions in actual production. As used herein, "roughly", "approximately" and similar terms are used as terms to indicate approximation, not as terms to indicate degree, and are intended to illustrate the inherent deviations in measured or calculated values ​​that will be recognized by those of ordinary skill in the art.

[0045] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing the implementation of the embodiments of the present application, "may" is used to mean "one or more implementations of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0046] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0047] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0048] The features, principles and other aspects of the embodiments of the present application are described in detail below.

[0049] Figure 1 The flowchart of the method 1000 for preparing a three-dimensional memory according to an exemplary embodiment of the present application is schematically shown. Figure 1 As shown, a method 1000 for preparing a three-dimensional memory according to some embodiments of the present application includes:

[0050] Step S1100, forming a step structure having a gate layer on a substrate, and forming a step dielectric layer on the step structure, wherein the step structure includes at least two sub-step structures isolated from each other;

[0051] Step S1200, forming word line contacts respectively penetrating the step dielectric layer and extending to each sub-step structure, wherein the word line contacts are connected to the gate layer;

[0052] Step S1300, removing a portion of the step dielectric layer to form a conductive portion, wherein the conductive portion contacts and connects the word lines in each sub-step structure; and

[0053] Step S1400 , forming a first contact on a side of the step dielectric layer away from the substrate, wherein the first contact is connected to a word line contact in at least a portion of the sub-step structures.

[0054] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. In addition, some of the steps shown may be performed simultaneously or in different steps. Figure 1 Executed in the order shown.

[0055] Figures 2 to 6B 1 is a process schematic diagram of a method 1000 for preparing a three-dimensional memory according to an embodiment of the present application. Figure 8 The following is a schematic diagram of a three-dimensional memory system according to an embodiment of the present application. The above steps S1100 to S1400 are further described below in conjunction with the accompanying drawings of the embodiment of the present application.

[0056] S1100, forming a step structure having a gate layer on a substrate, and forming a step dielectric layer on the step structure, The step structure includes at least two sub-step structures isolated from each other.

[0057] like Figure 2 As shown, a step structure 120 may be formed on a substrate 180, and the step structure 120 includes a first sub-step structure 121 and a second sub-step structure 122 isolated from each other. It should be noted that the step structure 120 may include at least two sub-step structures isolated from each other. Figure 2 The step structure 120 shown has two sub-step structures, which is only an exemplary description and the present application is not limited thereto.

[0058] In an exemplary embodiment, a plurality of dielectric layers 150 and sacrificial layers may be alternately deposited on a substrate 180 to form a stacked structure (the stacked structure will be replaced by a stacked structure 100 in a subsequent process), and then a portion of the stacked structure is removed in a direction perpendicular to the stacking by etching to form an initial step structure (not shown). During this process, the initial step structure is divided into two isolated parts that do not contact each other. Then, an insulating material is deposited on the initial step structure to form a first dielectric layer 210. After that, the sacrificial layer may be removed and a gate layer 160 may be filled in the space formed after the sacrificial layer is removed. The gate layer 160 and the dielectric layer 150 together constitute the stacked structure 100. Exemplarily, the step of forming the gate layer 160 includes first forming a channel hole (not shown) in the stacked structure that penetrates the stacked structure and a portion of the substrate 180. A wet etching process, for example, is performed through the channel hole to remove the sacrificial layer in the stacked structure, and a conductive material, such as metal tungsten, is filled in the gap left after the sacrificial layer is removed to form the gate layer 160. After the sacrificial layer is replaced by the gate layer 160, the stacked structure forms the stacked structure 100. Exemplarily, the material of the dielectric layer 150 includes silicon oxide, the material of the sacrificial layer includes silicon nitride, and the material of the gate layer 160 includes metal tungsten.

[0059] The first sub-step structure 121 may be located in the first storage area 110 of the stacked structure 100, and the second sub-step structure 122 may be located in the second storage area 130 of the stacked structure 100. There is a gap between the first sub-step structure 121 and the second sub-step structure 122, and the gap isolates the first sub-step structure 121 and the second sub-step structure 122 as mutually independent parts. It can be understood that each step in the first sub-step structure 121 and the second sub-step structure 122 is composed of a dielectric layer 150 and a gate layer 160 of the same length stacked.

[0060] The step dielectric layer 210 fills and covers the first sub-step structure 121 in the first storage area 110, the second sub-step structure 122 in the second storage area 130, and the gap between the first storage area 110 and the second storage area 130. The second dielectric layer 220 is deposited on the side of the channel structure 170 away from the substrate 180. It should be noted that the second dielectric layer 220 can be deposited in one step with the step dielectric layer 210. Exemplarily, the step dielectric layer 210 and the second dielectric layer 220 can be insulating materials such as silicon dioxide and silicon nitride.

[0061] In an exemplary embodiment, a channel structure 170 is provided inside the first storage area 110 and the second storage area 130. It should be noted that the preparation process of the channel structure 170 is performed before the step structure 120 is formed to provide mechanical support for the stacked structure during the removal of the sacrificial layer. The preparation method of the channel structure 170 includes forming a channel hole extending to the substrate 180 on the stacked structure, depositing a selective epitaxial layer 171 on the side of the channel hole close to the substrate, and sequentially depositing a blocking layer 172, a charge capture layer 173 and a tunneling layer 174 on the sidewall and bottom surface of the selective epitaxial layer 171. In an exemplary embodiment, the blocking layer 172, the charge capture layer 173 and the tunneling layer 174 can be a silicon oxide-silicon nitride-silicon oxide structure (ONO). Afterwards, a channel layer 175 is deposited on the side of the tunneling layer 174 away from the sidewall of the channel hole, and a channel dielectric layer 176 is filled on the side of the channel layer 175 away from the sidewall of the channel hole, wherein the channel layer 175 contacts the upper surface of the selective epitaxial layer. Exemplarily, the process of forming the blocking layer 172, the charge trapping layer 173, the tunneling layer 174 and the channel layer 175 can be selected from at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The material of the channel layer 175 can be selected from at least one of polysilicon and doped polysilicon.

[0062] S1200, forming word line contacts that penetrate the step dielectric layer and extend to each sub-step structure, wherein: A word line contact is connected to the gate layer.

[0063] like Figure 3 As shown, a first through hole 211 and a second through hole 212 are formed through the step dielectric layer 210 .

[0064] In an exemplary embodiment, the step dielectric layer 210 is etched to form a first through hole 211 and a second through hole 212, wherein the first through hole 211 and the second through hole 212 are respectively located on each step of the first sub-step structure 121 and the second sub-step structure 122, and extend to the inside of the step to connect with the gate layer 160. It should be noted that the gate layer 160 is formed by replacing the sacrificial layer in the stacked structure. One or more thin film deposition processes (such as CVD, PVD, ALD or any combination thereof) can be used to fill the first through hole 211 and the second through hole 212 with a first conductive material to form a first word line contact 213 and a second word line contact 214 (refer to FIG. 5), and exemplarily, the first conductive material includes metal tungsten, aluminum, copper, tungsten alloy or any combination thereof.

[0065] Step S1300, removing a portion of the step dielectric layer to form a conductive portion, wherein the conductive portion connects each sub-step. The word line contact connection in the structure.

[0066] The process of forming the conductive hole 240 is as follows: Figure 4AAs shown, the side of the step dielectric layer 210 away from the substrate 180 can be etched to form a conductive hole 240. In some examples, the conductive hole 240 is connected to the surface of the step dielectric layer 210 away from the substrate 180, and connects the first through hole 211 and the second through hole 212. Further, the number of the first through hole 211 and the second through hole is the same. Exemplarily, the first through hole 211 can extend to the N1th layer of the first sub-step structure 121, and the second through hole 212 can extend to the N2th layer of the second sub-step structure 122, and the conductive hole 240 connects the first through hole 211 with the second through hole 212. In some examples, N1 and N2 can be the same. In other examples, the values ​​of N1 and N2 are different.

[0067] Figure 4B for Figure 4A A top view of the conductive hole 240 in FIG. Figure 4B FIG. 2 shows the projection shape of the conductive hole 240 on the plane of the step dielectric layer 210 away from the substrate 180. Figure 4A and Figure 4B The connection method of the conductive via 240 can be more intuitively understood.

[0068] In an exemplary embodiment, if Figure 5A As shown, after forming the first word line contact 213 and the second word line contact 214, the first conductive material outside the first through hole 211 and the second through hole 212 is removed by chemical mechanical polishing (CMP). Then, the second conductive material is filled inside the conductive hole 240 to form a conductive portion 241 ( Figure 5B ) to electrically connect the first word line contact 213 and the second word line contact 214. Exemplarily, the number of the first word line contact 213, the second word line contact 214 and the conductive portion 241 is the same, and the second conductive material can be the same as or different from the first conductive material. Further, the interconnected first word line contact 213 and the second word line contact 214 can be located on the steps of the same level of different step structures. It should be noted that the first word line contact 213 and the second word line contact 214 extend to each step of the first sub-step structure 121 and the second sub-step structure 122, respectively, and are connected to the gate layer 160.

[0069] Figure 5B for Figure 5A A top view of the first word line contact 213 and the second word line contact 214 connected to each other. Figure 5B It can be seen that the first word line contact 213 and the second word line contact 214 form an electrical connection in the step dielectric layer 210 through the conductive portion 241, which can control the first storage area and the second storage area 130 at the same time, reduce the resistance when driving the storage block, and improve the driving time delay and other problems.

[0070] Step S1400, forming a first contact on a side of the step dielectric layer away from the substrate, wherein the first contact is connected to Word line contact connection in a multi-part sub-step structure.

[0071] Fig. 6A FIG. 2 is a schematic diagram of a process for connecting the first word line contact 213 and the first contact 250 according to an embodiment of the present application. In an exemplary embodiment, a third dielectric layer 250 is deposited on a side of the conductive hole 240 away from the substrate 180. The third dielectric layer 250 is deposited on the conductive hole 240. Fig. 6A The upper surface of the three-dimensional memory intermediate 200 is fully covered, and a first contact 260 is disposed on the three dielectric layers 250, wherein the first contact 260 is connected to the first word line contact 213. Specifically, the material of the first contact 260 may be, for example, a conductive metal. Figure 6B yes Fig. 6A A top view of the first word line contact and the first contact being connected, Figure 7 is a schematic diagram of the connection method of the word line contact 310 of the three-dimensional memory 300 in some embodiments, compared with Fig. 6A and Figure 7 It can be seen that the windings formed by the memory device according to the embodiment of the present application are significantly reduced, which can reduce the production cost.

[0072] In the subsequent process of the method for preparing a three-dimensional memory, steps such as forming a peripheral circuit in the three-dimensional memory are also included. The implementation method and process flow in the embodiment of the present application only show the intermediate of forming a three-dimensional memory with a gate gap.

[0073] Another aspect of the present application embodiment further provides a three-dimensional memory. The three-dimensional memory structure can be prepared by any preparation method in the above-mentioned embodiment. Fig. 6A As shown, the three-dimensional memory may include a substrate 180 and a stacked structure 100. The stacked structure 100 is located on the substrate 180 and includes a first sub-step structure 121 and a second sub-step structure 122 isolated from each other. As shown in the figure, the three-dimensional memory may also include a step dielectric layer 210, a first word line contact 213, a second word line contact 214, a conductive portion 241, and a first contact 260. The step dielectric layer 210 is located between the first storage area 110 and the second storage area 130. The first word line contact 213 penetrates the step dielectric layer 210 and contacts the gate layer 160 in the first sub-step structure 121. The second word line contact 214 penetrates the step dielectric layer 210 and contacts the gate layer 160 in the second sub-step structure 122. The conductive portion 241 is located in the step dielectric layer 210 and connects the first word line contact 213 to the second word line contact 214. The first contact 260 is located on the side of the step dielectric layer 210 away from the substrate 180 and connects the first word line contact 213 to the first contact 260.

[0074] In one embodiment, the stack structure 100 includes a plurality of dielectric layers on one side of the substrate 180 and a gate layer 160 between every two dielectric layers. The stack structure 100 is divided into a first storage area 110 and a second storage area 130 by a step dielectric layer 210 .

[0075] In one embodiment, the first sub-step structure 121 is located in the first storage area 110, and the second sub-step structure 122 is located in the second storage area 130. The portion of the gate layer 160 located in the first sub-step structure 121 is connected to the first word line contact 213, and the portion of the gate layer 160 located in the second sub-step structure 122 is connected to the second word line contact 214.

[0076] In one embodiment, the step structure includes a first sub-step structure 121 and a second sub-step structure 122 respectively located in the first storage area 110 and the second storage area 130, wherein each step in the first sub-step structure 121 is connected to at least one first word line contact 213, and each step in the second sub-step structure 122 is connected to at least one second word line contact 214.

[0077] In one embodiment, each first word line contact 213 is electrically connected to a second word line contact 214 located at the same step height through a conductive portion 241. Exemplarily, the number of first contacts 213, second word line contacts 214, and conductive portions 241 is the same. The three-dimensional memory in any embodiment of the present application can be a 3D NAND memory. The 3D NAND memory includes a plurality of memory cells arranged in a three-dimensional stacking manner.

[0078] Since the contents and structures involved in the preparation method described above can be fully or partially applicable to the memory packaging structure described here, the related or similar contents will not be repeated.

[0079] In another aspect, the present application further provides a three-dimensional memory system 400, such as Figure 8 As shown, the three-dimensional memory system 400 includes a three-dimensional memory 401 and a controller 402 in any embodiment of the present application. In one embodiment, the memory 401 is electrically connected to the controller 402 and is controlled by the controller 402. The controller 402 can, for example, control a storage unit (not shown) in the memory 401 to apply different voltage signals to achieve the effect of controlling the memory 401 to perform at least one of, for example, a read operation, a program operation, and an erase operation. The three-dimensional memory system 400 can also include a connector 403, which can be connected to a device such as a host to transmit and send data information.

[0080] In one embodiment, the controller 402 may be configured to control the operation of the memory 401, such as read, program and erase operations, etc. The controller 402 may also be configured to manage various functions related to data stored or to be stored in the memory 401, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc.

[0081] In one embodiment, the three-dimensional memory system 400 may be a solid state drive (SSD), a memory card, or any combination thereof. The controller 402 and the memory 401 may be integrated into the SSD to form a three-dimensional memory system. The storage capacity and / or operating speed of the SSD may be higher than the storage capacity and / or operating speed of the memory card. The three-dimensional memory 401 of any embodiment of the present application may be applied to storage devices or memory cards such as memory sticks, PC cards, compact flash (CF) cards, smart media (SM) cards, multimedia cards, SD cards, and universal flash storage cards (UFS).

[0082] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the embodiments of the present application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the technical concept. For example, the above-mentioned features are replaced with the technical features with similar functions disclosed in the embodiments of the present application (but not limited to) and the technical solutions formed.

Claims

1. A method for preparing a three-dimensional memory, characterized in that: The method comprises: Forming a step structure having a gate layer on a substrate, and forming a step dielectric layer on the step structure, wherein the step structure includes at least two sub-step structures isolated from each other; forming word line contacts respectively penetrating the step dielectric layer and extending to each of the sub-step structures, wherein the word line contacts are connected to the gate layer; removing a portion of the step dielectric layer to form a conductive portion, wherein the conductive portion contacts and connects word lines located on steps of the same level in different sub-step structures; and A first contact is formed on a side of the step dielectric layer away from the substrate, wherein the first contact is connected to a word line contact in at least a portion of the sub-step structure.

2. The method according to claim 1, characterized in that The step structure includes a first sub-step structure and a second sub-step structure isolated from each other; The word line contact comprises a first word line contact penetrating the step dielectric layer and extending to the first sub-step structure, and a second word line contact penetrating the step dielectric layer and extending to the second sub-step structure; and The conductive portion connects the first word line contact and the second word line contact.

3. The method according to claim 2, characterized in that The first contact is connected to the first word line contact; or The first contact is connected to the second word line contact.

4. The method according to claim 2, characterized in that: The conductive part is formed in the step dielectric layer and is in contact with a surface of the step dielectric layer that is away from the substrate, and there is no contact between the plurality of conductive parts.

5. The method according to claim 2, characterized in that: The numbers of the first word line contacts, the second word line contacts, and the conductive parts are the same.

6. The method according to claim 2, characterized in that Each step in the first sub-step structure is connected to at least one first word line contact, and each step in the second sub-step structure is connected to at least one second word line contact, Wherein, each step in the first sub-step structure and each step in the second sub-step structure includes the gate layer.

7. The method according to claim 2, characterized in that The steps of forming the first word line contact and the second word line contact include: forming a first through hole penetrating the step dielectric layer and extending to the first sub-step structure, and filling the first through hole with a first conductive material to form the first word line contact; and A second through hole is formed which penetrates the step dielectric layer and extends to the second sub-step structure, and the first conductive material is filled in the second through hole to form the second word line contact.

8. The method according to claim 2, characterized in that: The step of forming the conductive portion includes: removing a portion of the step dielectric layer away from the substrate to form a conductive hole connecting the first word line contact and the second word line contact; and The conductive hole is filled with a second conductive material to form the conductive portion.

9. The method according to claim 8, characterized in that The conductive portion connects the first word line contacts and the second word line contacts located at the same step height in pairs.

10. The method according to claim 5, characterized in that The step of forming the first contact comprises: The first contacts are connected to the first word line contacts in pairs and the same number thereof is provided.

11. The method according to claim 2, characterized in that The steps of forming the step structure include: forming a stacked structure having a dielectric layer and a sacrificial layer on the substrate; removing a portion of the stacked structure to form an initial step structure; and removing the sacrificial layer, and filling the gate layer in the space formed after removing the sacrificial layer to form the step structure, The portion of the gate layer located in the first sub-step structure is in contact with and connected to the first word line, and the portion of the gate layer located in the second sub-step structure is in contact with and connected to the second word line.

12. The method according to claim 11, characterized in that Before forming the initial step structure, the method comprises: forming a channel hole penetrating the stacked structure; forming a blocking layer, a charge trapping layer, a tunneling layer and a channel layer in sequence in the channel hole to form a channel structure; and After the stepped structure is formed, the channel structure does not penetrate the stepped structure.

13. A three-dimensional memory, characterized in that: include: A step structure having a gate layer and including at least two sub-step structures isolated from each other; A step dielectric layer, located on the step structure; A plurality of word line contacts respectively penetrate the step dielectric layer and extend into each of the sub-step structures; A conductive portion, located in the step dielectric layer, for contacting and connecting word lines located on steps of the same level in different sub-step structures; as well as The first contact is located at a side of the step dielectric layer away from the step structure and is connected to the word line contacts in at least a portion of the sub-step structure.

14. The memory according to claim 13, characterized in that: The step structure includes a first sub-step structure and a second sub-step structure isolated from each other; The word line contact comprises a first word line contact penetrating the step dielectric layer and extending to the first sub-step structure, and a second word line contact penetrating the step dielectric layer and extending to the second sub-step structure; and The conductive portion connects the first word line contact and the second word line contact.

15. The memory according to claim 14, characterized in that: The first contact is connected to the first word line contact; or, The first contact is connected to the second word line contact.

16. The memory according to claim 14, characterized in that: The conductive part is located in the step dielectric layer and is connected to a surface of the step dielectric layer which is away from the substrate, and there is no contact between the plurality of conductive parts.

17. The memory according to claim 14, characterized in that: The numbers of the first word line contacts, the second word line contacts, and the conductive parts are the same.

18. The memory according to claim 14, characterized in that: Each step in the first sub-step structure is connected to at least one of the first word line contacts, and each step in the second sub-step structure is connected to at least one of the second word line contacts, Wherein, each step in the first sub-step structure and each step in the second sub-step structure includes a gate layer.

19. The memory according to claim 14, characterized in that: The conductive portion connects the first word line contacts and the second word line contacts located at the same step height in pairs.

20. The memory according to claim 13, wherein: The memory is a 3D NAND memory.

21. A three-dimensional memory system, comprising: The memory as claimed in any one of claims 13 to 20; as well as The controller is electrically connected to the memory and controls the memory to perform at least one of a read operation, a program operation, and an erase operation.

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