Truncation process method of fin field effect transistor

Abstract

The present invention discloses a truncation process method of a fin field effect transistor, comprising the following steps: step 1, providing a semiconductor substrate having a plurality of fin bodies and a first spacer, forming a first material layer to completely fill the first spacer and extend it above the surface of the fin body and form a flattened surface; step 2, forming a first graphic structure including a plurality of first strip structures and a second spacer; step 3, forming a second sidewall on the side of the first strip structure to cover the top of the fin body on both sides of the first strip structure; step 4, removing the first strip structure to form a second graphic structure formed by the second sidewall; step 5, etching the first material layer and the fin body with the second sidewall as a mask to achieve truncation of the fin body; step 6, removing the second sidewall and the remaining first material layer. The present invention can reduce the requirements for the lithography capability of the lithography machine, and can still use the lithography machine used when the process node is larger for exposure when the process node is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a truncation process method of a fin field effect transistor (FinFET transistor). Background Art

[0002] Fin field effect transistors use fin bodies. By covering the gate structure of the transistor on the surface of the fin body, such as the side and top surface, the channel width can be increased, thereby improving the device performance. However, on the same semiconductor substrate, not all fin bodies need to form a gate structure, so the fin bodies that do not need to form a gate structure need to be truncated. The existing truncation process method of fin field effect transistors uses a photolithography process to open the fin body that needs to be truncated, and then etches and removes the fin body in the open area according to the photolithography definition. The existing method has high requirements for photolithography accuracy. As the process node continues to shrink, a photolithography machine with higher photolithography accuracy is required to achieve it. However, the higher the photolithography accuracy of the photolithography machine, the higher the cost will be, and the most advanced photolithography machines are usually scarce, and not every wafer manufacturing plant can be equipped with them. Therefore, in the case of continuous shrinking of process nodes, it will be very important if a photolithography machine with lower accuracy can be used to achieve truncation of the fin body.

[0003] like Figures 1A to 1C FIG. 1 is a schematic diagram of a device cross-sectional structure in each step of a conventional fin field effect transistor truncation process method; the conventional fin field effect transistor truncation process method includes the following steps:

[0004] Step 1: Figure 1A As shown, a semiconductor substrate 101 is provided, a plurality of fin bodies 102 are formed on the semiconductor substrate 101 , and a first spacer region 103 is provided between each of the fin bodies 102 .

[0005] Typically, the semiconductor substrate 101 is a silicon substrate.

[0006] A first hard mask layer 104 is also formed on the surface of the fin body 102. Preferably, the first hard mask layer 104 includes a third oxide layer 104a, a fourth nitride layer 104b and a fifth oxide layer 104c stacked together.

[0007] The fin body 102 is formed by etching the semiconductor substrate 101. For example, the formation area of ​​the fin body 102 can be defined by a photolithography process, and then the first hard mask layer 104 and the semiconductor substrate 101 between the fin body 102 are etched to form the fin body 102. As the process node decreases, the width d1 of the fin body 102 will become smaller and smaller. The width d1 is the critical dimension (TCD) of the fin body 102. At the 16nm process node, the width d1 is 16nm.

[0008] Step 2: Figure 1B As shown, a material layer 105 is formed to completely fill the first spacer 103 and extend to above the surface of the fin 102. The material layer 105 can be made of spin-on carbon (SOC).

[0009] Afterwards, a photoresist is formed and exposed and developed to form a photoresist pattern, wherein the photoresist pattern includes the photoresist stripes 106 and the spacing regions between the photoresist stripes 106. Figure 1B As shown, the width d2 of the photoresist strip 106 will cover a fin body 102 that needs to be retained and will extend to both sides of the fin body 102; the spacing area between the photoresist strips 106 will open a fin body 102 that needs to be truncated. The sum of the width d2 of the photoresist strip 106 and the width of the spacing area between the photoresist strips 106 is the width d3. It can be seen that the width d3 corresponds to the sum of the widths of the two fin bodies 102 and the two first spacing areas 103.

[0010] Step 3: Figure 1C As shown, the material layer 105 and the fin body 102 of the open area are etched according to the photolithography definition to achieve the truncation of the fin body 102. Afterwards, the photoresist and the remaining material layer 105 are removed. The truncation of the fin body is represented by a mark 102a alone. Usually, the truncation of the fin body 102a still has a certain height d4 remaining. For the 16nm process node, the height d4 is about 20nm.

[0011] The existing method has relatively high requirements for the lithography machine. At the 16nm process node, the width d2 is about 53nm and the width d3 is about 96nm, which can be achieved by using an immersion lithography machine.

[0012] However, as the process node continues to shrink, such as when the process node is 14nm, the width d2 will be less than about 36nm, and the width d3 will be less than 72nm. At this time, immersion lithography cannot be used and EUV lithography must be used. Summary of the invention

[0013] The technical problem to be solved by the present invention is to provide a truncation process method for a fin field effect transistor, which can reduce the requirements on the lithography capability of a lithography machine, and can still use a lithography machine used when the process node is larger for exposure when the process node is reduced; and can still use an immersion lithography machine for exposure below a 16nm process node.

[0014] In order to solve the above technical problems, the truncation process method of the fin field effect transistor provided by the present invention comprises the following steps:

[0015] Step 1: providing a semiconductor substrate, on which a plurality of fins are formed, and a first spacing region is provided between each of the fins.

[0016] A first material layer is formed to completely fill the first spacer and extend the first spacer to above the surface of the fin body and form a planarized surface.

[0017] Step 2: forming a first graphic structure on the surface of the first material layer, wherein the first graphic structure includes a plurality of first strip structures and second spacing areas between the first strip structures.

[0018] The first strip structure covers a fin body that needs to be cut off and extends into the first spacing regions on both sides of the covered fin body.

[0019] The area covered by the second spacer includes one fin body that needs to be cut off and two fin bodies that need to be retained and the corresponding first spacer areas.

[0020] The sum of the widths of the first strip structure and the second spacer is equal to four times the sum of the widths of the fin and the first spacer.

[0021] Step three: forming a second sidewall on the side of the first strip structure, wherein the second sidewall covers the top of the fin body on both sides of the first strip structure.

[0022] Step 4: removing the first strip-shaped structure to form a second pattern structure formed by the second sidewalls, wherein a third spacing area is provided between the second sidewalls.

[0023] Step five: using the second sidewall as a mask, etching the first material layer and the fin body in the third spacer region to achieve truncation of the fin body.

[0024] Step six: removing the second sidewall spacer and the remaining first material layer.

[0025] A further improvement is that the semiconductor substrate is a silicon substrate.

[0026] A further improvement is that the first material layer in step one is spin-coated carbon.

[0027] A further improvement is that the first graphic structure in step 2 is formed by the following steps:

[0028] A silicon contained hard mask layer (SiHM) and a photoresist are formed in sequence.

[0029] The photoresist is exposed and developed to form a photoresist pattern.

[0030] The silicon-containing hard mask layer is etched using the photoresist pattern as a mask to form the first pattern structure, and the first stripe structure is composed of the etched silicon-containing hard mask layer.

[0031] The photoresist pattern is removed.

[0032] A further improvement is that the growth temperature of the silicon-containing hard mask layer is 200°C to 230°C.

[0033] A further improvement is that before forming the silicon-containing hard mask layer, the method further includes forming a first silicon oxide layer using an atomic layer deposition process.

[0034] After the first graphic structure is formed, the surface of the first silicon oxide layer in the second spacer is exposed.

[0035] A further improvement is that the temperature of the atomic layer deposition process for forming the first silicon oxide layer is 60°C to 90°C.

[0036] A further improvement is that the step of forming the second sidewall in step three includes:

[0037] An atomic layer deposition process is used to form a second silicon oxide layer, where the second silicon oxide layer covers the top surface and the side surface of each of the first strip structures and the surface of the first silicon oxide layer in the second spacer.

[0038] Dry etching is performed to remove the second silicon oxide layer on the top surface of the first strip structure, and the second silicon oxide layer remaining on the first strip structure forms the second sidewall, and the superimposed layer of the first silicon oxide layer and the second silicon oxide layer on the surface of the second spacer has a partial thickness remaining.

[0039] A further improvement is that the temperature of the atomic layer deposition process for forming the second silicon oxide layer is 60°C to 90°C.

[0040] A further improvement is that in step four, a wet etching process is used to remove the first strip structure.

[0041] A further improvement is that the etching solution of the wet etching process for removing the first strip-shaped structure is TMAH.

[0042] A further improvement is that in step one, a first hard mask layer is also formed on the surface of the fin body.

[0043] A further improvement is that the first hard mask layer includes a third oxide layer, a fourth nitride layer and a fifth oxide layer stacked on top of each other.

[0044] A further improvement is that in step five, the height of the fin body after being cut off is less than or equal to 20 nm.

[0045] A further improvement is that the minimum process node of the FinFET is below 16nm.

[0046] A further improvement is that the exposure process of the photoresist is implemented using an immersion photolithography machine.

[0047] A further improvement is that the silicon-containing hard mask layer is composed of a silicon-containing photoresist material.

[0048] In the fin body truncation process of the fin transistor of the present invention, the photolithography process is not directly used to define the fin body to be truncated, but the first graphic structure is first defined, and then the fin body to be truncated is defined by the second side wall formed on both sides of the first connection structure of the first graphic structure. Obviously, the size of the first graphic structure will be larger than the size of the second graphic structure corresponding to the second side wall. The smaller second graphic structure does not need to be defined by the photolithography process, but is self-aligned on the basis of the larger first graphic structure. Therefore, the present invention can reduce the requirements on the photolithography capability of the photolithography machine, and can still use the photolithography machine used when the process node is larger for exposure when the process node is reduced, which can reduce the process difficulty and save costs.

[0049] In the prior art, when the process node is below 16nm, especially below 14nm, an extreme ultraviolet (EUV) lithography machine is required for exposure; through the method of the present invention, an immersion lithography machine can still be used for exposure below the 16nm process node. EUV lithography machines are very expensive, so the present invention can greatly save costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0051] Figure 1A-Figure 1C It is a schematic diagram of the device cross-sectional structure in each step of the existing truncation process method of the fin field effect transistor;

[0052] Figure 2 is a flow chart of a truncation process method of a fin field effect transistor according to an embodiment of the present invention;

[0053] Figure 3A-3G It is a schematic diagram of the device cross-sectional structure in each step of the truncation process method of the fin field effect transistor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] like Figure 2 As shown, it is a flow chart of a truncation process method of a fin field effect transistor according to an embodiment of the present invention; Figures 3A to 3GFIG. 1 is a schematic diagram of a device cross-sectional structure in each step of a truncation process method of a fin field effect transistor according to an embodiment of the present invention; the truncation process method of a fin field effect transistor according to an embodiment of the present invention comprises the following steps:

[0055] Step 1: Figure 3A As shown, a semiconductor substrate 1 is provided, a plurality of fin bodies 2 are formed on the semiconductor substrate 1 , and a first spacing region 202 is provided between each of the fin bodies 2 .

[0056] In the method of the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate.

[0057] A first hard mask layer 3 is also formed on the surface of the fin body 2. Preferably, the first hard mask layer 3 includes a third oxide layer 3a, a fourth nitride layer 3b and a fifth oxide layer 3c stacked together.

[0058] The fin 2 is formed by etching the semiconductor substrate 1 .

[0059] The first material layer 4 is formed to completely fill the first spacer 202 and extend to the surface of the fin 2 to form a planarized surface. Preferably, the first material layer 4 is spin-coated carbon.

[0060] Step 2: Figure 3C As shown, a first graphic structure is formed on the surface of the first material layer 4 , wherein the first graphic structure includes a plurality of first strip structures 6 a and second spacing areas 203 between the first strip structures 6 a .

[0061] The first strip structure 6 a covers a portion of the fin body 2 that needs to be cut off and extends into the first spacing regions 202 on both sides of the covered fin body 2 .

[0062] The area covered by the second spacer 203 includes one fin body 2 that needs to be cut off and two fin bodies 2 that need to be retained and the corresponding first spacer 202 .

[0063] The sum of the widths of the first strip structure 6a and the second spacer 203 is equal to 4 times the sum of the widths of the fin body 2 and the first spacer. Figure 3C Indicated by d101. Figure 1B Compared with the corresponding width d3 in , it can be seen that the width d101 in the embodiment of the present invention can be twice the width d3, so the embodiment of the present invention can reduce the requirements on the lithography accuracy of the lithography machine.

[0064] In the method of the embodiment of the present invention, the first graphic structure is formed by the following steps:

[0065] like Figure 3A As shown, a first silicon oxide layer 5, a silicon-containing hard mask layer 6 and a photoresist 201 are formed in sequence.

[0066] The first silicon oxide layer 5 is formed by an atomic layer deposition process; preferably, the temperature of the atomic layer deposition process of the first silicon oxide layer 5 is 60° C. to 90° C., which is a low-temperature atomic layer deposition process.

[0067] The silicon-containing hard mask layer 6 is made of a silicon-containing photoresist material.

[0068] The growth temperature of the silicon-containing hard mask layer 6 is 200° C. to 230° C.

[0069] Afterwards, if Figure 3B As shown, the photoresist 201 is exposed and developed to form a photoresist 201 pattern. It can be seen that the photoresist 201 pattern includes photoresist strips 201a and spacing areas between the photoresist strips 201a.

[0070] like Figure 3C As shown, the silicon-containing hard mask layer 6 is etched using the photoresist 201 pattern as a mask to form the first pattern structure, and the first strip structure 6a is composed of the silicon-containing hard mask layer 6 after etching.

[0071] The photoresist 201 pattern is removed.

[0072] After the first graphic structure is formed, the surface of the first silicon oxide layer 5 in the second spacer region 203 is exposed.

[0073] Step 3: Figure 3E As shown, a second sidewall 7a is formed on the side of the first strip-shaped structure 6a, and the second sidewall 7a covers the top of the fin body 2 on both sides of the first strip-shaped structure 6a.

[0074] In the embodiment of the present invention, the step of forming the second sidewall 7a includes:

[0075] like Figure 3D As shown, the second silicon oxide layer 7 is formed by an atomic layer deposition process, and the second silicon oxide layer 7 covers the top surface and the side surface of each of the first strip structures 6a and the surface of the first silicon oxide layer 5 in the second spacer 203. Preferably, the temperature of the atomic layer deposition process for forming the second silicon oxide layer 7 is 60°C to 90°C.

[0076] like Figure 3EAs shown, dry etching is performed to remove the second silicon oxide layer 7 on the top surface of the first strip structure 6a, and the second silicon oxide layer 7 remaining on the first strip structure 6a forms the second sidewall 7a, and the superposition layer of the first silicon oxide layer 5 and the second silicon oxide layer 7 on the surface of the second spacer 203 has a partial thickness remaining. The remaining part of the superposition layer of the first silicon oxide layer 5 and the second silicon oxide layer 7 on the surface of the second spacer 203 is separately indicated by a mark 5a.

[0077] Depend on Figure 3E It can be seen that the second spacing area 203 will be reduced, and the reduced width is equal to the width of two second side walls 7 a . The reduced second spacing area 203 is the spacing area between two adjacent second side walls 7 a .

[0078] Step 4: Figure 3F As shown, the first strip structure 6 a is removed to form a second graphic structure formed by the second sidewalls 7 a , and a third spacing area is provided between the second sidewalls 7 a .

[0079] Depend on Figure 3F It can be seen that the third spacing area includes the reduced second spacing area 203 and the area where the first strip structure 6a is removed.

[0080] In the embodiment of the present invention, a wet etching process is used to remove the first strip-shaped structure 6 a.

[0081] Preferably, TMAH is used as an etching solution in the wet etching process for removing the first strip-shaped structures 6 a.

[0082] Step 5: Figure 3G As shown, the first material layer 4 and the fin body 2 in the third spacer region are etched using the second sidewall 7 a as a mask to achieve truncation of the fin body 2 .

[0083] Step six: remove the second sidewall 7a and the remaining first material layer 4.

[0084] In the truncation process of the fin body 2 of the fin-type transistor in the embodiment of the present invention, the photolithography process is not directly used to define the fin body 2 to be truncated, but the first graphic structure is first defined, and then the fin body 2 to be truncated is defined by the second side wall 7a formed on both sides of the first connection structure of the first graphic structure. Obviously, the size of the first graphic structure will be larger than the size of the second graphic structure corresponding to the second side wall 7a. The smaller second graphic structure does not need to be defined by the photolithography process, but is self-aligned on the basis of the larger first graphic structure. Therefore, the embodiment of the present invention can reduce the requirements on the photolithography capability of the photolithography machine, and can still use the photolithography machine used when the process node is larger for exposure when the process node is reduced, which can reduce the process difficulty and save costs.

[0085] In the prior art, when the process node is below 16nm, especially below 14nm, an extreme ultraviolet (EUV) lithography machine is required for exposure; through the method of the embodiment of the present invention, an immersion lithography machine can still be used for exposure below the 16nm process node. EUV lithography machines are very expensive, so the embodiments of the present invention can greatly save costs.

[0086] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A truncation process method for a fin field effect transistor, characterized in that: The steps include: Step 1: providing a semiconductor substrate, on which a plurality of fins are formed, and a first spacer region is provided between each of the fins; Forming a first material layer to completely fill the first spacer and extend the first material layer to a surface of the fin body and form a planarized surface; Step 2: forming a first graphic structure on the surface of the first material layer, wherein the first graphic structure includes a plurality of first stripe structures and second spacing areas between the first stripe structures; The first strip structure covers a fin body that needs to be cut off and extends to the first spacing areas on both sides of the covered fin body; The area covered by the second spacer includes one fin body to be cut off and two fin bodies to be retained and the corresponding first spacer areas; The sum of the widths of the first strip structure and the second spacing area is equal to 4 times the sum of the widths of the fin body and the first spacing; Step 3: forming a second side wall on the side of the first strip structure, wherein the second side wall covers the top of the fin body on both sides of the first strip structure; Step 4: removing the first strip-shaped structure to form a second pattern structure formed by the second sidewalls, wherein a third spacing area is provided between the second sidewalls; Step 5: using the second sidewall as a mask, etching the first material layer and the fin body in the third spacer region to achieve truncation of the fin body; Step six: removing the second sidewall spacer and the remaining first material layer.

2. The truncation process method of the fin field effect transistor according to claim 1, characterized in that: The semiconductor substrate is a silicon substrate.

3. The truncation process method of the fin field effect transistor according to claim 1, characterized in that: The first material layer in step one is spin-coated carbon.

4. The truncation process method of the fin field effect transistor according to claim 3, characterized in that: The first graphic structure in step 2 is formed by the following steps: sequentially forming a silicon-containing hard mask layer and a photoresist; Exposing and developing the photoresist to form a photoresist pattern; Using the photoresist pattern as a mask, etching the silicon-containing hard mask layer to form the first pattern structure, wherein the first stripe structure is composed of the etched silicon-containing hard mask layer; The photoresist pattern is removed.

5. The truncation process method of the fin field effect transistor according to claim 4, characterized in that: The growth temperature of the silicon-containing hard mask layer is 200° C. to 230° C.

6. The truncation process method of the fin field effect transistor according to claim 4, characterized in that: Before forming the silicon-containing hard mask layer, the method further includes forming a first silicon oxide layer by using an atomic layer deposition process; After the first graphic structure is formed, the surface of the first silicon oxide layer in the second spacer is exposed.

7. The truncation process method of the fin field effect transistor according to claim 6, characterized in that: The temperature of the atomic layer deposition process for forming the first silicon oxide layer is 60° C. to 90° C.

8. The truncation process method of the fin field effect transistor according to claim 6, characterized in that: The step of forming the second sidewall in step three includes: forming a second silicon oxide layer by an atomic layer deposition process, wherein the second silicon oxide layer covers the top surface and the side surface of each of the first strip-shaped structures and the surface of the first silicon oxide layer in the second spacer area; Dry etching is performed to remove the second silicon oxide layer on the top surface of the first strip structure, and the second silicon oxide layer remaining on the first strip structure forms the second sidewall, and the superimposed layer of the first silicon oxide layer and the second silicon oxide layer on the surface of the second spacer has a partial thickness remaining.

9. The truncation process method of the fin field effect transistor according to claim 8, characterized in that: The temperature of the atomic layer deposition process for forming the second silicon oxide layer is 60° C. to 90° C.

10. The truncation process method of the fin field effect transistor according to claim 8, characterized in that: In step four, a wet etching process is used to remove the first strip structure.

11. The truncation process method of the fin field effect transistor according to claim 10, characterized in that: The etching solution of the wet etching process for removing the first strip-shaped structure is TMAH.

12. The truncation process method of the fin field effect transistor according to claim 1, wherein: In step one, a first hard mask layer is also formed on the surface of the fin body.

13. The truncation process method of the fin field effect transistor according to claim 12, wherein: The first hard mask layer includes a third oxide layer, a fourth nitride layer and a fifth oxide layer stacked together.

14. The truncation process method of the fin field effect transistor according to claim 1, wherein: In step five, the height of the fin body after being cut off is less than or equal to 20 nm.

15. The truncation process method of the fin field effect transistor according to claim 4, characterized in that: The minimum process node of FinFET is below 16nm.

16. The truncation process method of the fin field effect transistor according to claim 15, characterized in that: The exposure process of the photoresist is implemented by using an immersion photolithography machine.

17. The truncation process method of the fin field effect transistor according to claim 4, characterized in that: The silicon-containing hard mask layer is made of a silicon-containing photoresist material.

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