Display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel includes a display area and a non-display area, with the non-display area at least partially surrounding the display area. The non-display area includes a bending area that bends a portion of the display panel to the side of the display panel away from the light-emitting surface. The bending area includes multiple signal lines, with at least two signal lines located on different metals. This invention's display panel achieves narrow step widths without affecting signal electrical properties or the overall performance of the display panel, while also reducing manufacturing complexity and improving process yield.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Currently, display technology has permeated all aspects of people's daily lives, and correspondingly, more and more materials and technologies are being used in displays. Display panels, as a crucial component of display devices, are used to realize the display function. Today, the mainstream display panels are mainly liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays.

[0003] Organic light-emitting diodes (OLEDs), as current-driven light-emitting devices, are increasingly used in high-performance displays. OLED display panels possess numerous superior characteristics, including self-emission, wide viewing angle, fast response speed, high contrast, wide color gamut, low power consumption, thin panel, rich colors, flexible display capability, and wide operating temperature range. Therefore, they are hailed as the next-generation "star" flat panel display technology. An OLED display panel includes an anode and a cathode, as well as a hole transport layer, an organic light-emitting layer, and an electron transport layer disposed between the anode and cathode. The anode provides hole injection, and the cathode provides electron injection. Driven by an external voltage, holes and electrons injected from the cathode and anode recombine in the organic light-emitting layer, forming electron-hole pairs (i.e., excitons) at bound energy levels. These excitons radiate and emit photons, producing visible light.

[0004] Currently, OLED products are gradually shifting towards high-end, high refresh rates, narrow bezels, and high display quality, requiring continuous optimization of panel design to adapt to market demands. OLED's most obvious advantage is its ability to achieve a narrow bezel design by bending the panel at the bottom edge, but related technologies have limitations in achieving a truly narrow bezel and are prone to short circuits.

[0005] Therefore, there is an urgent need to provide a display panel and display device that can achieve narrow steps and improve short circuits. Summary of the Invention

[0006] In view of this, the present invention provides a display panel and a display device for achieving narrow steps and improving the problem of short circuits.

[0007] On one hand, the present invention provides a display panel including a display area and a non-display area, wherein the non-display area at least partially surrounds the display area, and the non-display area includes a bending area through which a portion of the display panel is bent to the side of the display panel away from the light-emitting surface;

[0008] The bending area includes multiple signal lines, with at least two signal lines located in different metal layers.

[0009] On the other hand, the present invention also provides a display device including the above-described display device.

[0010] Compared with related technologies, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0011] The display panel of this invention bends a portion of the display panel to the side away from the light-emitting surface via a bending region. At least two signal lines in the bending region are located on different metal layers, thus reducing the number of signal lines on each metal layer. This reduces the space occupied by the signal lines in the second direction, enabling a narrow step design in the second direction. Furthermore, within the equal space in the second direction, the width of the signal lines in the second direction can be increased, as can the spacing between adjacent signal lines. Increasing the width of the signal lines in the second direction is equivalent to increasing their cross-sectional area, thereby reducing the resistance of a single signal line. Increasing the spacing between adjacent signal lines reduces the risk of short circuits between adjacent signal lines, improving product yield.

[0012] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0013] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0015] Figure 1 This is a schematic diagram of the planar structure of a display panel in related technologies;

[0016] Figure 2 yes Figure 1 A cross-sectional view along line A-A' in the middle;

[0017] Figure 3 yes Figure 1 A cross-sectional view along the B-B' direction;

[0018] Figure 4 This is a schematic diagram of a planar structure of a display panel provided by the present invention;

[0019] Figure 5 yes Figure 4 A cross-sectional view along the C-C' direction;

[0020] Figure 6 yes Figure 4 A cross-sectional view along the D-D' direction;

[0021] Figure 7 yes Figure 4 Another cross-sectional view along the C-C' direction;

[0022] Figure 8 yes Figure 4 Another cross-sectional view along the D-D' direction;

[0023] Figure 9 yes Figure 4 Another cross-sectional view along the C-C' direction;

[0024] Figure 10 yes Figure 4 Another cross-sectional view along the C-C' direction;

[0025] Figure 11 yes Figure 4 Another cross-sectional view along the D-D' direction;

[0026] Figure 12 yes Figure 4 Another cross-sectional view along the D-D' direction;

[0027] Figure 13 yes Figure 4 Another cross-sectional view along the D-D' direction;

[0028] Figure 14 yes Figure 4 Another cross-sectional view along the C-C' direction;

[0029] Figure 15 yes Figure 4 Another cross-sectional view along the C-C' direction;

[0030] Figure 16 yes Figure 4 Another cross-sectional view along the C-C' direction;

[0031] Figure 17 yes Figure 4 Another cross-sectional view along the D-D' direction;

[0032] Figure 18 yes Figure 4 Another cross-sectional view along the D-D' direction;

[0033] Figure 19 yes Figure 4 Another cross-sectional view along the C-C' direction;

[0034] Figure 20 This is a schematic diagram of the structure of a display device provided by the present invention. Detailed Implementation

[0035] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0036] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0037] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0038] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0039] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0040] Given that the display panels in related technologies cannot achieve narrow steps and are prone to short circuits, the inventors conducted the following research on related technologies, referring to... Figure 1 , Figure 2 and Figure 3 , Figure 1 This is a schematic diagram of the planar structure of a display panel in related technologies. Figure 2 yes Figure 1 A cross-sectional view along line A-A'. Figure 3 yes Figure 1 A cross-sectional view along line B-B' is shown. The display panel 000 in the related technology has a display area AA' and a non-display area BB' surrounding the display area AA'. The non-display area BB' has a bending area 1' and a fan-out trace area 2'. Part of the display panel is bent to the side of the display panel away from the light-emitting surface K' through the bending area 1'. The display panel 000 includes, in sequence, a first substrate 091, a buffer layer 092, a first insulating layer 093, a second insulating layer 094, a third insulating layer 095, a fourth insulating layer 096, a first metal layer M3', a planarization layer 097, and a pixel definition layer 098, wherein... Figure 1 and 2As shown, all signal lines 03 are placed on the first metal layer M3' in the bending region 1'. Since there are a large number of signal lines 03, which can be gate drive circuit signal lines, data signal lines, high potential signal lines, low potential signal lines, and touch lines, all need to pass through the bending region. Therefore, this area greatly affects the compression of the step area in the second direction X, making it impossible to achieve the design of a narrow step in the second direction X. In addition, if all signal lines 03 are placed on the first metal layer M3', it will inevitably cause process limits. If a narrow step needs to be designed in the second direction, the width a' and the spacing b' of the signal lines need to be compressed in order to place all signal lines 03 in the bending region 1'. However, this will inevitably lead to an increase in the resistance of a single signal line 03, and it is also easy to cause short circuits between two adjacent signal lines 03 in the bending region 1', reducing the product yield.

[0041] In view of this, the present invention provides a display panel and a display device for realizing narrow steps and preventing short circuits in the bending area. Specific embodiments of the display panel and display device will be described in detail below.

[0042] Reference Figure 4 , Figure 5 and Figure 6 , Figure 4 This is a schematic diagram of a planar structure of a display panel provided by the present invention. Figure 5 yes Figure 4 A cross-sectional view along the C-C' direction. Figure 6 yes Figure 4 A cross-sectional view along the D-D' direction. In this embodiment, a display panel 100 includes a display area AA and a non-display area BB. The non-display area BB at least partially surrounds the display area AA. The non-display area BB includes a bending area 1, through which a portion of the display panel 100 is bent to the side of the display panel 100 away from the light-emitting surface K. The bending area 1 includes multiple signal lines 3, with at least two signal lines 3 located in different metal layers.

[0043] Reference Figure 4 , Figure 4 The display panel 100 includes a display area AA and a non-display area BB. Figure 4The diagram only shows the case where the non-display area BB completely surrounds the display area AA. Of course, the non-display area BB can also partially surround the display area AA; this is not specifically limited here. The non-display area BB includes a lower border BB1. Along the first direction, the lower border BB1 includes a fan-out routing area 2 and a bending area 1. The fan-out routing area 2 is located between the display area AA and the bending area 1. In this embodiment, the bending area 1 bends part of the display panel 100 to the side of the display panel 100 away from the light-emitting surface K. Optionally, the fan-out routing area 2 can be equipped with a multiplexer (Demux), which can decompose a signal into multiple signal channels. Although the multiplexer can divide the signal lines 3 in the non-display area BB into multiple transmissions to the display area AA, there are still quite a few signal lines 3 in the non-display area BB, such as high-potential signal lines PVDD, low-potential signal lines PVEE, gate circuit drive signal lines VSR, data signal lines DATA, and touch signal lines TP. Figures 4 to 6 Signal line 33 is not classified in the document.

[0044] Optional, Figure 5 The diagram also shows that the bending area 1 of the display panel 100 includes a substrate 91, and a buffer layer 92, a first insulating layer 93, a second insulating layer 94, a third insulating layer 95, a fourth insulating layer 96, a first metal layer M3, a planarization layer 97, a pixel definition layer 98, and a touch layer TM, which are sequentially stacked on one side of the substrate 91. The diagram schematically shows a case where the signal line 3 is located in different metal layers. Figure 5 and Figure 6 The substrate 91, buffer layer 92, first insulating layer 93, second insulating layer 94, third insulating layer 95, fourth insulating layer 96, first planarization layer 97, pixel definition layer 98, and second planarization layer 97 are not patterned. The specific metal layer where the signal line 3 in the bending region 1 is located is not limited, as long as at least two signal lines 3 in the bending region 1 are located in different metal layers. Figure 5 Only a portion of signal line 3 is shown located in the first metal layer M3, and a portion of signal line 3 is located in the touch layer TM. Figure 5 The diagram also shows a capacitor metal Mc, which forms a storage capacitor with the gate M1. Of course, as long as the signal lines 3 are located on different metal layers, there is no specific limitation on the number of signal lines 3 located on different metal layers.

[0045] Figure 4 The width of the bending area 1 in the second direction is only schematically shown. Narrow steps can be designed according to user requirements. In this embodiment, the width of the bending area 1 in the second direction is not specifically limited. Figure 5 The signal lines 3 distributed on different metal layers are filled with the same pattern. Of course, the signal lines 3 distributed on different metal layers can be different types of signal lines.

[0046] Optional, refer to Figure 5 The substrate 91 can be formed of any suitable insulating material that is flexible. For example, the flexible substrate can be formed of polymeric materials such as polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyaryl compounds (PAR), or glass fiber reinforced plastic (FRP). The flexible substrate can be transparent, translucent, or opaque. A buffer layer 92 is located on a flexible substrate and covers the entire upper surface of the flexible substrate. The buffer layer 92 includes an inorganic layer or an organic layer. For example, the buffer layer 92 can be formed from an inorganic material selected from materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), or aluminum nitride (AlNx), or an organic material selected from materials such as acrylic, polyimide (PI), or polyester. The buffer layer 92 can include a single layer or multiple layers. The buffer layer 92 blocks oxygen and moisture, prevents moisture or impurities from diffusing through the flexible substrate, and provides a flat surface on the upper surface of the flexible substrate. The insulating layers (first insulating layer 93, second insulating layer 94, third insulating layer 95, and fourth insulating layer 96) in this invention can be formed from an insulating inorganic layer such as silicon oxide or silicon nitride. Alternatively, the insulating layers can also be formed from insulating organic layers. The planarization layer includes organic layers such as acrylic, polyimide (PI), or benzocyclobutene (BCB).

[0047] As described above, in related technologies, since all signal lines are located in the first metal layer, this area greatly affects the compression of the step area in the second direction, making it impossible to achieve a narrow step design in the second direction. Furthermore, having all signal lines in the first metal layer necessitates compressing the width and spacing of the signal lines, leading to increased signal line resistance and increasing the risk of short circuits between adjacent signal lines in the bending area, thus reducing product yield. In this embodiment, at least two signal lines 3 in the bending area 1 are located in different metal layers, reducing the number of signal lines 3 on each metal layer. Therefore, the space occupied by the signal lines 3 in the second direction can be reduced, enabling a narrow step design in the second direction. On the other hand, within the same width in the second direction, the width of the signal lines 3 in the second direction can be increased, as can the spacing between adjacent signal lines 3. Increasing the width of the signal lines 3 in the second direction is equivalent to increasing the cross-sectional area of ​​the signal lines 3, thus reducing the resistance of a single signal line 3. Increasing the spacing between adjacent signal lines 3 reduces the risk of short circuits between adjacent signal lines 3, improving product yield.

[0048] Of course, the more signal lines 3 distributed in different metal layers, the more conducive it is to realize the narrow step design in the second direction. The width of the signal line 3 in a single metal layer can also be set to be larger, and the spacing between adjacent signal lines 3 can also be set to be larger. This is more conducive to reducing the circuit of a single signal line 3 and reducing the risk of short circuit between adjacent signal lines 3.

[0049] In some alternative embodiments, refer to Figure 7 and Figure 8 , Figure 7 yes Figure 4 Another cross-sectional view along the C-C' direction. Figure 8 yes Figure 4 Another cross-sectional view along the D-D' direction, for ease of illustration. Figure 8 The cross-sectional view only shows the structure of the bending region 1 near the display area AA, and does not show the part bent to the back of the display panel 100. In this embodiment, the display panel 100 includes: a substrate 91; a thin film transistor 20 located on one side of the substrate 91; a light-emitting device 30 located on the side of the thin film transistor 20 away from the substrate 91; and a touch layer TM located on the side of the light-emitting device 30 away from the substrate 91. The light-emitting device 30 includes an anode layer 310, the thin film transistor 20 includes a source-drain layer M2, and a first metal layer M3 is provided between the anode layer 310 and the source-drain layer M2. In the bending region 1, at least one signal line 3 is on the same layer as the first metal layer M3, and at least one signal line 3 is on the same layer as the touch layer TM.

[0050] Optionally, the thin-film transistor is located on the buffer layer 92. Figure 8 The structure is described using a top-gate type thin-film transistor as an example. The thin-film transistor includes a semiconductor active layer on a buffer layer 92, comprising a source region and a drain region formed by doping with N-type or P-type impurity ions. The region between the source and drain regions is a channel region where no impurities are present. The semiconductor active layer can be formed by crystallizing amorphous silicon to change it into polycrystalline silicon. To crystallize the amorphous silicon, a gate M1 is located on a gate insulating layer. The gate can include one or more layers of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), or chromium (Cr), or alloys such as aluminum (Al):neodymium (Nd) alloys or molybdenum (Mo):tungsten (W) alloys. The source-drain layer M2 has a source and a drain, which are electrically connected (or bonded) to the source and drain regions of the active layer 201 through contact holes, which are formed by selectively removing the insulating layer.

[0051] Optional, Figure 8The diagram also shows an encapsulation layer 50 located on the side of the light-emitting device 30 away from the substrate 91. Optionally, the encapsulation layer 50 can be a stacked structure of an inorganic encapsulation layer 50, an organic encapsulation layer 50, and an inorganic encapsulation layer 50. Of course, the present invention does not limit the specific structure of the encapsulation layer 50. The encapsulation layer 50 can have multiple inorganic encapsulation layers 50 and multiple organic encapsulation layers 50, as long as it can provide good protection for the light-emitting device 30 in the display area AA.

[0052] Optionally, in addition to the anode, the light-emitting device 30 also includes a light-emitting layer 320 located on the side of the anode away from the substrate 91, and a cathode 33033 on the side of the light-emitting layer 320 away from the substrate 91. The thin-film transistor 20 drives the light-emitting device 30 to emit light for display. Figure 8 The illustration will only take one light-emitting device 30 as an example.

[0053] certainly Figure 8 The signal line 3 located in the first metal layer M3 in the bending region 1 is illustrated using a data line connected to the source of the thin-film transistor 20 as an example. The signal line 3 located in the touch layer TM in the bending region 1 can be any one of the following: touch line, high-potential signal line PVDD, low-potential signal line PVEE, or gate circuit drive signal line VSR. No specific limitations are made here. Figure 7 The number of signal lines 31 located in the first metal layer M3 and the number of signal lines 32 located in the touch layer TM are only for illustrative purposes and are not specifically limited here.

[0054] In this embodiment, in the bending region 1, at least one signal line 3 is on the same layer as the first metal layer M3, and at least one signal line 3 is on the same layer as the touch layer TM. This distributes the signal lines 3 in the bending region 1 on the touch layer TM and the first metal layer M3. Naturally, the number of signal lines 3 on the touch layer TM and the first metal layer M3 will be reduced, so the space occupied by the signal lines 3 in the second direction can be reduced, thus enabling a narrow step design in the second direction. On the other hand, within the same width in the second direction, the width of the signal lines 3 in the second direction can be increased, and the spacing between adjacent signal lines 3 can also be increased. For example, the width of the signal line 31 on the first metal layer M3 in the second direction can be increased, which is equivalent to increasing the cross-sectional area of ​​the signal line 31. Therefore, the resistance of a single signal line 331 can be reduced. Moreover, the spacing between adjacent signal lines 31 can be set larger. Increasing the spacing between adjacent signal lines 3 can reduce the risk of short circuits between adjacent signal lines 31 and improve product yield. Similarly, the width of the signal line 32 on the touch layer TM in the second direction can be increased, which is equivalent to increasing the cross-sectional area of ​​the signal line 32. Therefore, the resistance of a single signal line 32 can be reduced. In addition, the spacing between adjacent signal lines 32 can also be set larger. Increasing the spacing between adjacent signal lines 32 can reduce the risk of short circuit between adjacent signal lines 32 and improve product yield.

[0055] In some alternative embodiments, refer to Figure 9 , Figure 9 yes Figure 4 Another cross-sectional view along the C-C' direction shows that signal line 3 includes different types of signal lines 3. Signal line 3 includes a first type of signal line X1 and a second type of signal line X2. The first type of signal line X1 includes a high-potential signal line PVDD and a low-potential signal line PVEE. The second type of signal line X2 includes a gate circuit drive signal line VSR, a data signal line DATA, and a touch signal line TP. The first type of signal line X1 is on the same layer as the touch layer TM, and the second type of signal line X2 is on the same layer as the first metal layer M3.

[0056] In this embodiment, the signal lines 3 located in the bending area 1 are divided into two categories. The first category of signal lines X1 are high-potential signal lines PVDD and low-potential signal lines PVEE. The high-potential signal line PVDD transmits positive DC, and the low-potential signal line PVEE transmits negative DC. The width of the first category of signal lines X1 needs to be wider. The second category of signal lines X2 are gate circuit drive signal lines VSR, data signal lines DATA, and touch signal lines TP, which are the most numerous signal lines 3 in the display panel 100.

[0057] Figure 9 The number of high-potential signal lines PVDD, low-potential signal lines PVEE, gate circuit drive signal lines VSR, data signal lines DATA, and touch signal lines TP are for illustrative purposes only.

[0058] In this embodiment, the high-potential signal line PVDD and the low-potential signal line PVEE are on the same layer as the touch layer TM. This is because the OLED display panel 100 has an IR drop (IR-Drop), which refers to the phenomenon of voltage drop or rise on the power and ground networks in an integrated circuit. Therefore, the high-potential signal line PVDD and the low-potential signal line PVEE need to be designed to be wide to reduce their resistance and improve the IR drop phenomenon. Placing the high-potential signal line PVDD and the low-potential signal line PVEE in the touch layer TM allows for a wider signal line 32. The gate circuit drive signal line VSR, the data signal line DATA, and the touch signal line TP are required in large numbers and also occupy space. Placing them in the first metal layer M3 allows for a wider signal line 32 since the high-potential signal line PVDD and the low-potential signal line PVEE do not need to be placed in the first metal layer M3. This increases the spacing between adjacent signal lines 3 (gate circuit drive signal line VSR, data signal line DATA, and touch signal line TP) and prevents short circuits.

[0059] In some alternative embodiments, reference continues to be made to... Figure 4 and Figure 9 In the direction from the non-display area BB to the display area AA, the gate circuit drive signal line VSR, the touch signal line TP, and the data signal line DATA are arranged in sequence.

[0060] In the second direction, the arrangement of signal lines 3 in the first metal layer M3 is as follows: gate circuit drive signal line VSR, touch signal line TP, data signal line DATA, touch signal line TP, and gate circuit drive signal line VSR. Here, the second direction refers to the horizontal direction, which intersects with the first direction. The first direction refers to the direction from the display area AA to the bending area 1.

[0061] Optionally, the gate circuit drive signal line VSR, touch signal line TP, and data signal line DATA are arranged sequentially, with VSR, TP, and DATA set separately for easier partitioning. The gate circuit drive signal line VSR is a drive signal, transmitting a high-to-low voltage switching signal, responsible for driving the gate drive circuit of the display panel 100. The gate drive circuit is typically located on the left and right edges of the non-display area BB, so placing VSR on the outermost edge facilitates fabrication.

[0062] In some alternative embodiments, reference continues to be made to... Figure 9 In the direction from the substrate 91 toward the touch layer TM, the gate circuit drive signal line VSR and the low-potential signal line PVEE overlap at least partially, the touch signal line TP and the low-potential signal line PVEE overlap at least partially, and the data signal line DATA and the high-potential signal line PVDD overlap at least partially.

[0063] Figure 9The diagram only shows the following scenario: in the direction from the substrate 91 towards the touch layer TM, the gate M1 circuit driving signal overlaps with the low-potential signal line PVEE, the touch signal line TP overlaps with the low-potential signal line PVEE, and the data signal line DATA overlaps with the high-potential signal line PVDD. Alternatively, the gate M1 circuit driving signal can partially overlap with the low-potential signal line PVEE, the touch signal line TP partially overlaps with the low-potential signal line PVEE, and the data signal line DATA partially overlaps with the high-potential signal line PVDD. In this case, the number of signal lines 3 on both the touch layer TM and the first metal layer M3 is relatively small in the second direction, thus reducing the space occupied by the signal lines 3 in the second direction and enabling a narrow step design in the second direction. On the other hand, within the same width in the second direction, the width of the signal lines 3 in the second direction can be increased. Specifically, the width of the high-potential signal line PVDD and the low-potential signal line PVEE on the touch layer TM in the second direction can be larger, and the spacing between adjacent signal lines 3 can also be set larger. This further increases the spacing between adjacent signal lines 3, further reducing the risk of short circuits between adjacent signal lines 3 and improving product yield. Of course, the width of the gate circuit drive signal line VSR, touch signal line TP and data signal line DATA on the first metal layer M3 in the second direction can be larger, which is equivalent to increasing the cross-sectional area of ​​the gate circuit drive signal line VSR, touch signal line TP and data signal line DATA. The spacing between adjacent signal lines 3 can also be set larger, which can further reduce the risk of short circuit between adjacent signal lines 3 and improve product yield.

[0064] In some alternative embodiments, refer to Figure 10 and Figure 11 , Figure 10 yes Figure 4 Another cross-sectional view along the C-C' direction. Figure 11 yes Figure 4 Another cross-sectional view along the D-D' direction. In this embodiment, the touch layer TM includes a touch electrode layer TM2 and a bridge electrode layer TM1. The touch electrode layer TM2 is located on the side of the bridge electrode layer TM1 away from the substrate 91. A portion of the high-potential signal lines PVDD are on the same layer as the touch electrode layer TM2, and another portion of the high-potential signal lines PVDD are on the same layer as the bridge electrode layer TM1. A portion of the low-potential signal lines PVEE are on the same layer as the touch electrode layer TM2, and another portion of the low-potential signal lines PVEE are on the same layer as the bridge electrode layer TM1.

[0065] Figure 10The figure shows that the touch layer TM in the display area AA includes a touch electrode layer TM2 and a bridge electrode layer TM1. It is understood that the display panel 100 with touch function has an emitting electrode and a sensing electrode (not shown in the figure). In order to achieve the thinness of the display panel 100, the emitting electrode and the sensing electrode are placed on the same layer. Adjacent emitting electrodes or adjacent sensing electrodes are electrically connected by a bridge. The bridge electrode layer TM1 is used to form a bridge.

[0066] like Figure 10 As shown, the high-potential signal line PVDD and the low-potential signal line PVEE are respectively located on the touch electrode layer TM2 and the bridge electrode layer TM1. This allows the high-potential signal line PVDD and the low-potential signal line PVEE to be designed to be very wide, thereby reducing the resistance of the high-potential signal line PVDD and the low-potential signal line PVEE and improving the IR voltage drop phenomenon.

[0067] In some alternative embodiments, refer to Figure 12 and Figure 13 , Figure 12 yes Figure 4 Another cross-sectional view along the D-D' direction. Figure 13 yes Figure 4 Another cross-sectional view along the D-D' direction shows that both the first type signal line X1 and the second type signal line X2 include a first sub-part 301 and a second sub-part 302 that are electrically connected. The first sub-part 301 is located in the bending area 1, and the second sub-part 302 is located in the display area AA. The first sub-part 301 of the first type signal line X1 is on the same layer as the touch layer TM, and the second sub-part 302 of the first type signal line X1 is on the same layer as the first metal layer M3. The first sub-part 301 and the second sub-part 302 of the second type signal line X2 are both on the same layer as the first metal layer M3.

[0068] Understandably, in order to illustrate the routing of the first type of signal line X1 and the second type of signal line X2 in the film layer, therefore... Figure 12 and Figure 13 The diagram shows the film layer arrangement of the first type of signal line X1 and the second type of signal line X2, respectively. Of course, this is only for illustrative purposes. Figure 12 The image shows a second type of signal line X2. For the second type of signal line X2, the first sub-part 301 located in the bending area 1 and the second sub-part 302 located in the display area AA are both on the same layer as the first metal layer M3. This eliminates the need to change the film layer of the second type of signal line X2, making it easier to manufacture and simplifying the manufacturing process. Figure 13The diagram shows a first type of signal line X1. For the first type of signal line X1, the second part in the display area AA is located in the first metal layer M3, and the first part in the bending area 1 is located in the touch layer TM. This allows the first type of signal line X1 and the second type of signal line X2 to be distributed in two film layers, the first metal layer M3 and the touch layer TM. The number of signal lines 3 on both film layers is reduced, so the space occupied by the signal lines 3 in the second direction can be reduced, thus enabling a narrow step design in the second direction. The increased width of the first type of signal line X1 in the first metal layer M3 and the second type of signal line X2 in the touch layer TM in the second direction increases the cross-sectional area of ​​the first type of signal line X1 and the second type of signal line X2, thereby reducing the resistance of a single signal line 3. The increased spacing between adjacent first type of signal line X1 or adjacent second type of signal line X2 reduces the risk of short circuits between adjacent signal lines 3 and improves product yield.

[0069] In some alternative embodiments, reference continues to be made to... Figure 13 The non-display area BB also includes a fan-out routing area 2. Along the first direction, the fan-out routing area 2 is located between the display area AA and the bending area 1. When the first sub-part 301 of the first type signal line X1 is located in the touch layer TM and the second sub-part 302 of the first type signal line X1 is located in the first metal layer M3, the first sub-part 301 extends to the fan-out routing area 2. In the fan-out routing area 2, the first sub-part 301 and the second sub-part 302 are electrically connected through vias.

[0070] Figure 13 In the middle, the lower border BB1 of the non-display area BB also includes a fan-out routing area 2. Along the first direction, the fan-out routing area 2 is located between the display area AA and the bending area 1. For the first type of signal line X1, its first sub-part 301 is located in the touch layer TM, and its second sub-part 302 is located in the first metal layer M3. If the second sub-part 302 in the display area AA is switched to the touch layer TM, the first sub-part 301 and the second sub-part 302 are electrically connected through a via. Of course, setting the via for switching the line in the fan-out routing area 2 will not increase the width of the non-display area BB (lower border BB1) in the first direction.

[0071] In some alternative embodiments, refer to Figure 14 , Figure 14 yes Figure 4 Another cross-sectional view along the C-C' direction shows that signal line 3 includes different types of signal lines 3. Signal line 3 includes a first type of signal line X1 and a second type of signal line X2. The first type of signal line X1 includes a high-potential signal line PVDD, a low-potential signal line PVEE, and a touch signal line TP. The second type of signal line X2 includes a gate circuit drive signal line VSR and a data signal line DATA. The first type of signal line X1 is on the same layer as the touch layer TM, and the second type of signal line X2 is on the same layer as the first metal layer M3.

[0072] In this embodiment, the signal lines 3 located in the bending area 1 are divided into two categories. The first category of signal lines X1 includes high-potential signal lines PVDD, low-potential signal lines PVEE, and touch signal lines TP. The high-potential signal line PVDD transmits positive DC, and the low-potential signal line PVEE transmits negative DC. The widths of the high-potential signal lines PVDD and PVEE need to be relatively wide. As for the touch signal line TP, its display area AA is also located in the touch layer TM. Therefore, the touch signal line TP in the bending area 1 is also set in the touch layer TM, eliminating the need for a separate line and reducing the risk of drilling during the manufacturing process. The second category of signal lines X2 are the gate circuit drive signal line VSR and the data signal line DATA.

[0073] Figure 9 The number of high-potential signal lines PVDD, low-potential signal lines PVEE, gate circuit drive signal lines VSR, data signal lines DATA, and touch signal lines TP are for illustrative purposes only.

[0074] In this embodiment, the high-potential signal line PVDD and the low-potential signal line PVEE are on the same layer as the touch layer TM. As mentioned above, because the OLED display panel 100 has an IR drop, which is a phenomenon that occurs when the voltage drops or rises on the power and ground networks in an integrated circuit, the high-potential signal line PVDD and the low-potential signal line PVEE need to be designed to be very wide. This can reduce the resistance of the high-potential signal line PVDD and the low-potential signal line PVEE and improve the IR drop phenomenon. The high-potential signal line PVDD and the low-potential signal line PVEE are placed in the touch layer TM, which allows the signal line 32 to be set wider. For the touch signal line TP, its display area AA is also located in the touch layer TM, so the touch signal line TP in the bending area 1 is also placed in the touch layer TM, eliminating the need for a separate line and reducing the risk of drilling during the manufacturing process. The gate circuit drive signal line VSR and the data signal line DATA require a large number and also occupy space, so they are placed in the first metal layer M3. Since only the second type signal line X2 is set in the first metal layer M3, the first type signal line X1 does not need to be set, which can increase the spacing between adjacent signal lines 3 and prevent short circuit problems.

[0075] In some alternative embodiments, refer to Figure 15 , Figure 15 yes Figure 4 Another cross-sectional view along the C-C' direction shows that the signal line 3 includes the same type of signal line 3. The same type of signal line 3 includes a first signal line 311 and a second signal line arranged alternately in the direction from the non-display area BB to the display area AA shown. The first signal line 311 is on the same layer as the first metal layer M3, and the second signal line 312 is on the same layer as the touch layer TM.

[0076] Optionally, signal line 3 may include a high-potential signal line PVDD, a low-potential signal line PVEE, a touch signal line TP, a gate circuit drive signal line VSR, and a data signal line DATA. For example, the high-potential signal line PVDD of the same type includes a first signal line 311 and a second signal line 312 alternately arranged in the direction from the non-display area BB to the display area AA shown. The first signal line 311 is disposed in the first metal layer M3, and the second signal line 312 is disposed in the touch layer TM. Similarly, the first signal line 311 of the low-potential signal line PVEE can also be disposed in the first metal layer M3. 3. A low-potential second signal line 312 is disposed in the touch layer TM. A first signal line 311 of the touch signal line TP is disposed in the first metal layer M3. A second signal line 312 of the touch signal line TP is disposed in the touch layer TM. A first signal line 311 of the gate circuit drive signal line VSR is disposed in the first metal layer M3. A second signal line 312 of the gate circuit drive signal line VSR is disposed in the touch layer TM. A first signal line 311 of the data signal line DATA is disposed in the first metal layer M3. A second signal line 312 of the data signal line DATA is disposed in the touch layer TM. Figure 15 The above is for illustrative purposes only and does not specify the type of signal line 3.

[0077] In this embodiment, the signal lines 3 of the same type include a first signal line 311 and a second signal line 312 arranged alternately in the direction from the non-display area BB to the display area AA. The first signal line 311 and the second signal line 312 are respectively disposed on the first metal layer M3 and the touch layer TM, which enables a narrow step design in the second direction. On the other hand, within the same width in the second direction, the width of the signal line 3 in the second direction can be increased, and the spacing between adjacent signal lines 3 can also be increased. Increasing the width of the signal line 3 in the second direction is equivalent to increasing the cross-sectional area of ​​the signal line 3, so the resistance of a single signal line 3 can be reduced. Increasing the spacing between adjacent signal lines 3 can reduce the risk of short circuit between adjacent signal lines 3 and improve product yield.

[0078] In some alternative embodiments, refer to Figure 16 , Figure 16 yes Figure 4 Another cross-sectional view along the C-C' direction, signal line 3 is either a data signal line (DATA) or a touch signal line (TP).

[0079] It is understandable that the data signal lines DATA and touch signal lines TP are the two most numerous signal lines 3 in the display panel 100. Setting the first signal line 311 of the data signal line DATA on the first metal layer M3 and setting the second signal line 312 of the data signal line DATA on the touch layer TM, or setting the first signal line 311 of the touch signal line TP on the first metal layer M3 and setting the second signal line 312 of the touch signal line TP on the touch layer TM, can achieve an even distribution of the most numerous signal lines 3 on the two film layers. This can achieve a narrow step design in the second direction under better conditions. Moreover, it is a superior situation that the width of the signal line 3 in the second direction can be increased within the same width in the second direction.

[0080] In some alternative embodiments, refer to Figure 17 and Figure 18 , Figure 17 yes Figure 4 Another cross-sectional view along the D-D' direction. Figure 18 yes Figure 4 Another cross-sectional view along the D-D' direction shows that the non-display area BB also includes a fan-out routing area 2. Along the first direction, the fan-out routing area 2 is located between the display area AA and the bending area 1. The first signal line 311 and the second signal line 312 both include an electrically connected first sub-part 301 and a second sub-part 302. The first sub-part 301 is located in the bending area 1, and the second sub-part 302 is located in the display area AA. The first sub-part 301 and the second sub-part 302 of the first signal line 311 are on the same layer as the first metal layer M3. The first sub-part 301 of the second signal line 312 is located in the touch layer TM, and the second sub-part 302 of the second signal line 312 is on the same layer as the first metal layer M3.

[0081] Signal lines of the same type 3 include a first signal line 311 and a second signal line 312 arranged alternately in the direction from the non-display area BB to the display area AA shown. Figure 17 In the first signal line 311, the first sub-part 301 and the second sub-part 302 are on the same layer as the first metal layer M3; Figure 18In the first sub-section 301 of the second signal line 312 is located in the touch layer TM, and the second sub-section 302 of the second signal line 312 is on the same layer as the first metal layer M3. Optionally, the second signal line 312 can be jumpered through vias in the fan-out routing area 2, so that the first signal line 311 and the second signal line 312 in the bending area 1 are distributed in different film layers. The first signal line 311 and the second signal line 312 are respectively located on the first metal layer M3 and the touch layer TM, which can realize a narrow step design in the second direction. On the other hand, within the same width in the second direction, the width of the signal line 3 in the second direction can be increased, and the spacing between adjacent signal lines 3 can also be increased. Increasing the width of the signal line 3 in the second direction is equivalent to increasing the cross-sectional area of ​​the signal line 3, so the resistance of a single signal line 3 can be reduced. Increasing the spacing between adjacent signal lines 3 can reduce the risk of short circuit between adjacent signal lines 3 and improve product yield.

[0082] In some alternative embodiments, reference continues to be made to... Figure 7 and Figure 8 The thin-film transistor 20 also includes a buffer layer 92 located on one side of the substrate 91, an active layer 201 located on the side of the buffer layer 92 near the source-drain layer M2, a gate M1 located on the side of the active layer 201 near the source-drain layer M2, and a planarization layer 97 located on the side of the first metal layer M3 near the touch layer TM. An insulating layer is provided between the active layer 201, the gate M1, and the source-drain layer M2. The buffer layer 92, the insulating layer, and the planarization layer 97 extend to the bending region 1.

[0083] As described above, the buffer layer 92 comprises an inorganic or organic layer. For example, the buffer layer 92 may be formed from an inorganic material selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), or aluminum nitride (AlNx), or an organic material selected from acrylic, polyimide (PI), or polyester. The insulating layer may be formed from an insulating inorganic layer such as silicon oxide or silicon nitride; alternatively, the insulating layer may be formed from an insulating organic layer. The planarization layer comprises an organic layer such as acrylic, polyimide (PI), or benzocyclobutene (BCB). These materials are all bendable materials, and bending will not cause the film layer to break; they also serve to support the signal line 3.

[0084] In some alternative embodiments, refer to Figure 19 , Figure 19 yes Figure 4Another cross-sectional view along the C-C' direction shows that the display panel also includes a pixel definition layer 98, which separates the light-emitting devices 30 and extends to the bending region 1. In the bending region 1, the touch layer TM is located on the side of the pixel definition layer 98 away from the substrate 91. In the direction from the touch layer TM to the substrate 91, the thickness of the pixel definition layer 98 in the bending portion is less than the thickness of the pixel definition layer 98 in the display area AA.

[0085] It is understandable that, in the direction from the touch layer TM to the substrate 91, the thickness of the pixel definition layer 98 in the display area AA is usually relatively large. After the pixel definition layer 98 extends to the bending area 1, if the thickness of the pixel definition layer 98 in the bending portion is equal to the thickness of the pixel definition layer 98 in the display area AA, it will increase the thickness of the bending area 1, which is not conducive to manufacturing. In this embodiment, in the direction from the touch layer TM to the substrate 91, the thickness of the pixel definition layer 98 in the bending portion is h2, and the thickness of the pixel definition layer 98 in the display area AA is h1. The thickness h2 of the pixel definition layer 98 in the bending portion is less than the thickness h1 of the pixel definition layer 98 in the display area AA. This thinning of the pixel definition layer 98 in the bending area 1 can reduce the thickness of the bending area 1.

[0086] Alternatively, the pixel definition layer 98 in the bending area 1 can be directly removed, that is, in the direction from the touch layer TM to the substrate 91, the thickness h2 of the pixel definition layer 98 in the bending part is equal to 0, which can further reduce the thickness of the bending area 1.

[0087] In some alternative embodiments, please refer to Figure 20 , Figure 20 This is a schematic diagram of the structure of a display device provided by the present invention. The display device 200 provided in this embodiment includes the display panel 100 in the above embodiment. Figure 20 This embodiment uses a mobile phone as an example to illustrate the display device 200. It is understood that the display device 200 provided in this embodiment can be other display devices 200 with display functions, such as computers, televisions, electronic paper, and in-vehicle display devices; this invention does not impose specific limitations on these. The display device 200 provided in this embodiment has the beneficial effects of the display panel 100 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments; these will not be repeated here.

[0088] As can be seen from the above embodiments, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0089] The display panel of this invention bends a portion of the display panel to the side away from the light-emitting surface via a bending region. At least two signal lines in the bending region are located on different metal layers, thus reducing the number of signal lines on each metal layer. This reduces the space occupied by the signal lines in the second direction, enabling a narrow step design in the second direction. Furthermore, within the same width in the second direction, the width of the signal lines in the second direction can be increased, as can the spacing between adjacent signal lines. Increasing the width of the signal lines in the second direction is equivalent to increasing the cross-sectional area of ​​the signal lines, thereby reducing the resistance of a single signal line. Increasing the spacing between adjacent signal lines reduces the risk of short circuits between adjacent signal lines, improving product yield.

[0090] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, It includes a display area and a non-display area, wherein the non-display area at least partially surrounds the display area, and the non-display area includes a bending area through which a portion of the display panel is bent to the side of the display panel away from the light-emitting surface; The display panel includes: a substrate; a thin-film transistor located on one side of the substrate; a light-emitting device located on the side of the thin-film transistor away from the substrate; and a touch layer located on the side of the light-emitting device away from the substrate. The light-emitting device includes an anode layer, the thin-film transistor includes a source-drain layer, and a first metal layer is disposed between the anode layer and the source-drain layer; The bending area includes multiple signal lines, wherein at least one signal line is on the same layer as the first metal layer and at least one signal line is on the same layer as the touch layer. The signal lines include signal lines of the same type, including a first signal line and a second signal line. The first signal line is on the same layer as the first metal layer, and the second signal line is on the same layer as the touch layer. Within the bending area, the first signal line and the second signal line are not connected. Both the first signal line and the second signal line include a gate circuit driving signal line, a touch signal line, and a data signal line. In the direction from the non-display area to the display area, the gate circuit driving signal line located on the first metal layer and the gate circuit driving signal line located on the touch layer are arranged alternately, as are the touch signal lines located on the first metal layer and the touch signal lines located on the touch layer, and the data signal lines located on the first metal layer and the data signal lines located on the touch layer are arranged alternately.

2. The display panel according to claim 1, characterized in that, The signal lines include different types of signal lines, including a first type of signal line and a second type of signal line. The first type of signal line includes high-potential signal lines and low-potential signal lines. The second type of signal line includes gate circuit drive signal lines, data signal lines and touch signal lines. The first type of signal line is on the same layer as the touch layer, and the second type of signal line is on the same layer as the first metal layer.

3. The display panel according to claim 2, characterized in that, In the direction from the non-display area to the display area, the gate circuit drive signal line, the touch signal line, and the data signal line are arranged in sequence.

4. The display panel according to claim 2, characterized in that, In the direction from the substrate to the touch layer, the gate circuit driving signal line at least partially overlaps with the low-potential signal line, the touch signal line at least partially overlaps with the low-potential signal line, and the data signal line at least partially overlaps with the high-potential signal line.

5. The display panel according to claim 2, characterized in that, The touch layer includes a touch electrode layer and a bridge electrode layer, wherein the touch electrode layer is located on the side of the bridge electrode layer away from the substrate. A portion of the high-potential signal lines are on the same layer as the touch electrode layer, another portion of the high-potential signal lines are on the same layer as the bridge electrode layer, a portion of the low-potential signal lines are on the same layer as the touch electrode layer, and another portion of the low-potential signal lines are on the same layer as the bridge electrode layer.

6. The display panel according to claim 2, characterized in that, Both the first type of signal line and the second type of signal line include a first sub-section and a second sub-section that are electrically connected. The first sub-section is located in the bending area, and the second sub-section is located in the display area. The first sub-section of the first type of signal line is on the same layer as the touch layer, and the second sub-section of the first type of signal line is on the same layer as the first metal layer; Both the first sub-section of the second type of signal line and the second sub-section of the second type of signal line are on the same layer as the first metal layer.

7. The display panel according to claim 6, characterized in that, The non-display area also includes a fan-out routing area, which is located between the display area and the bending area along the first direction; When the first sub-part of the first type of signal line is located in the touch layer and the second sub-part of the first type of signal line is located in the first metal layer, the first sub-part extends to the fan-out trace area, and in the fan-out trace area, the first sub-part and the second sub-part are electrically connected through vias.

8. The display panel according to claim 1, characterized in that, The signal lines include different types of signal lines, including a first type of signal line and a second type of signal line. The first type of signal line includes high-potential signal lines, low-potential signal lines and touch signal lines. The second type of signal line includes gate circuit drive signal lines and data signal lines. The first type of signal line is on the same layer as the touch layer, and the second type of signal line is on the same layer as the first metal layer.

9. The display panel according to claim 1, characterized in that, The signal line is a data signal line or a touch signal line.

10. The display panel according to claim 9, characterized in that, The non-display area also includes a fan-out routing area, which is located between the display area and the bending area along the first direction; Both the first signal line and the second signal line include an electrically connected first sub-section and a second sub-section, the first sub-section being located in the bending area and the second sub-section being located in the display area; The first sub-section and the second sub-section of the first signal line are on the same layer as the first metal layer; The first sub-section of the second signal line is located in the touch layer, and the second sub-section of the second signal line is in the same layer as the first metal layer.

11. The display panel according to claim 1, characterized in that, The thin-film transistor further includes a buffer layer located on one side of the substrate, an active layer located on the side of the buffer layer near the source-drain layer, a gate located on the side of the active layer near the source-drain layer, and a planarization layer located on the side of the first metal layer near the touch layer. An insulating layer is provided between the active layer, the gate, and the source-drain layer. The buffer layer, the insulating layer, and the planarization layer extend to the bending region.

12. The display panel according to claim 11, characterized in that, The display panel further includes a pixel definition layer that separates the light-emitting devices and extends to the bending area; In the bending region, the touch layer is located on the side of the pixel definition layer away from the substrate. In the direction from the touch layer to the substrate, the thickness of the pixel definition layer in the bending area is less than the thickness of the pixel definition layer in the display area.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 12.

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