Modular stacking semiconductor packaging method
Through the modular stacked semiconductor packaging method, the same chip module and sealant layer prepared in advance are used to reduce electrical connection defects caused by bare crystal alignment errors and improve the yield of stacked semiconductor packaging.
Patent Information
- Application Number
- CN202011442512.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-10-27
- Filing Date
- 2020-12-08
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2040-12-08
AI Technical Summary
The existing stacked semiconductor packaging methods have reduced packaging yield due to the alignment error of the bare crystal at different positions, and lack effective improvement solutions.
By adopting a modular stacked semiconductor packaging method, by providing a first carrier plate and N*M identical chip modules, each chip module is coated with a first colloid and is in the component area of the first carrier plate. The first rewiring layer is formed inside, the chip module is stacked and electrically connected, and the second sealing layer is formed to form a coating, the carrier plate is removed and the modular stacked semiconductor elements forming multiple N layers are cut to reduce the aligning error. electrical connection defects.
The defects in the bare crystal electrical connection in the chip module caused by the alignment error are greatly reduced, and the yield of the stacked multi-layer stacked semiconductor packaging method is improved.
Smart Images
Figure CN114496810B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a stacked semiconductor packaging method, and more particularly to a modular stacked semiconductor packaging method. Background Art
[0002] The existing stacked semiconductor packaging method mainly prepares the bare die to be packaged in advance, and can be stacked in sequence on a substrate or a first carrier and then sealed at one time, and the stacked bare die is covered with a single sealing body to form a stacked semiconductor packaging structure; or a first layer of bare die is first fixed on the substrate or the first carrier and then sealed, and the first layer of bare die is covered with a first layer of sealing body, and then a first layer of circuit layer is formed on the first layer of sealing body, and then a second layer of bare die is fixed on the first layer of circuit layer, and then sealed again, and the second layer of bare die is covered with a second layer of sealing body, and this is repeated N times until an N-layer stacked semiconductor packaging structure is formed.
[0003] The above two common stacked semiconductor packaging methods, whether stacking bare die in sequence or forming a multi-layer semiconductor package in sequence, are prone to packaging yield reduction due to alignment errors because the bare die are arranged in different positions of the stacked semiconductor packaging structure, and further improvement is necessary. Summary of the invention
[0004] In order to solve the technical problems existing in the existing stacked semiconductor packaging method, the main purpose of the present invention is to propose a modular stacked semiconductor packaging method to overcome the above problems.
[0005] In order to achieve the above object, the present invention proposes a modular stacking semiconductor packaging method, which comprises the following steps:
[0006] (a) providing a first carrier board and N*M identical chip modules; wherein the first carrier board has M component areas, and each chip module is composed of a stacked die group encapsulated by a first encapsulant;
[0007] (b) forming a first redistribution layer in each of the component regions of the first carrier;
[0008] (c) stacking N chip modules on the first redistribution layer in each of the device regions of the first carrier, and the N chip modules are electrically connected to each other;
[0009] (d) forming a second sealing layer on the first redistribution layers on the first carrier to cover the chip modules;
[0010] (e) removing the first carrier to expose a surface of each of the first redistribution layers, and forming a plurality of solder balls on the exposed surface; and
[0011] (f) Cutting the second encapsulation layer along the boundaries of the adjacent device regions to form a plurality of N-layer modular stacked semiconductor devices.
[0012] From the above description, it can be seen that the present invention mainly prepares the same chip modules in advance, and each chip module already includes a plurality of bare chips stacked on each other. When the stack packaging process is performed using these chip modules, the electrical connection defects between the bare chips in the chip modules caused by alignment errors are greatly reduced, thereby improving the yield of the stacked multi-layer stacked semiconductor packaging method.
[0013] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figures 1A to 1K sectional views of different steps in the first embodiment of the modular stacked semiconductor packaging method of the present invention.
[0015] FIG. 2A to FIG. 2F sectional views of different steps in the second embodiment of the modular stacked semiconductor packaging method of the present invention.
[0016] FIG. 3A to FIG. 3F sectional views of different steps in the first embodiment of the modular stacked semiconductor packaging method of the present invention.
[0017] Reference numerals
[0018] 1. 1a, 1b: Modular stacked semiconductor components
[0019] 10: First redistribution layer
[0020] 11: Surface
[0021] 20, 20a~20d: chip module
[0022] 21: Second redistribution layer
[0023] 211: Second pad layer
[0024] 212: first pad layer
[0025] 22: The first sealing layer
[0026] 22': First seal
[0027] 23: Conductive through hole
[0028] 231: End
[0029] 30: Bare crystal group
[0030] 30a~30d: Bare crystal
[0031] 31a~31d: Metal contacts
[0032] 40: Second sealing layer
[0033] 40': Second sealing colloid
[0034] 50: First carrier board
[0035] 51: Component area
[0036] 60: Second carrier board
[0037] 61: Module area DETAILED DESCRIPTION
[0038] The structural principle and working principle of the present invention are described in detail below in conjunction with the accompanying drawings:
[0039] First see Figures 1A to 1K As shown, the first embodiment of the modular stacking semiconductor packaging method of the present invention comprises the following steps (a) to (f):
[0040] In step (a), if Figure 1E and Figure 1F As shown, a first carrier 50 and N*M identical chip modules 20 are prepared; wherein the first carrier 50 has M component areas 51, and each chip module 20 is mainly composed of a first encapsulant 22' encapsulating a stacked die set 30. In this embodiment, each chip module 20 is composed of Figures 1A to 1E The first method shown is made, as Figure 1A , Figure 1B As shown, a second carrier 60 and a plurality of identical bare crystals 30a, 30b are prepared, the second carrier 60 includes a plurality of module areas 61, a second redistribution layer 21 is formed in each module area 61, the metal contacts 31a on the active surface of some bare crystals 30a are flip-chip bonded to the second redistribution layer 21, and the back surfaces of the remaining bare crystals 30b are fully adhered (i.e., flip-chip bonded) to the back surfaces of the bare crystals 30a on the second redistribution layer 21, and the metal contacts 31b on the active surface are facing away from the second redistribution layer 21, and the four sides of the stacked two bare crystals 30a, 30b are flush; Figure 1C As shown, a first sealing layer 22 is formed on the second redistribution layers 21 to cover the bare die 30a, 30b; Figure 1D As shown, at least one through hole penetrating the first sealing layer 22 is formed in each module area 61, and a metal material is filled in each through hole to form a conductive through hole 23, that is, each conductive through hole is formed by electroplating the metal material in each through hole, and the first sealing layer 22 is ground to expose the metal contact 31b of the active surface of the bare die 30b, and the exposed end 231 of each conductive through hole 23 forms the first pad layer 212 of each chip module 20; Figure 1EAs shown, the first sealing layer 22 is cut along the boundary of the adjacent module area 61 to form a plurality of identical chip modules 20 , and an exposed surface of the second redistribution layer 21 of each chip module 20 is a second pad layer 211 .
[0041] In step (b), if Figure 1F As shown, a first redistribution layer 10 is formed in each device region 51 on the first carrier 50; in this embodiment, the first redistribution layers 10 are manufactured simultaneously.
[0042] In step (c), if Figure 1F , Figure 1G and Figure 1H As shown, N chip modules 20a~20d are stacked on the first redistribution layer 10 of each component area 51 of the first carrier 50 and electrically connected to each other. In this embodiment, the first pad layers 212 of the chip modules 20a located on the first layer are oriented toward the first carrier 50 and are electrically connected to the first redistribution layer 10 in the corresponding component area 51, respectively. At this time, the second pad layers 211 of the chip modules 20a located on the first layer are oriented toward a direction away from the first redistribution layer 10; then, the first pad layers 212 of the chip modules 20b also located on the second layer are oriented toward and electrically connected to the second pad layers 211 of the chip modules 20a located on the first layer; at this time, the second pad layers 211 of the chip modules 20b located on the second layer are oriented toward a direction away from the first redistribution layer 10; and this step is repeated. The steps are repeated until an N-layer (N=4) stack is completed, that is, the first pad layers 212 of the chip modules 20c located on the third layer are respectively oriented toward and electrically connected to the second pad layers 211 of the chip modules 20b located on the second layer; at this time, the second pad layers 211 of the chip modules 20c located on the third layer are oriented toward a direction away from the first redistribution layer 10; then, the first pad layers 212 of the chip modules 20d located on the fourth layer are respectively oriented toward and electrically connected to the second pad layers 211 of the chip modules 20c located on the third layer; at this time, the second pad layers 211 of the chip modules 20d located on the fourth layer are oriented toward a direction away from the first redistribution layer 10.
[0043] In step (d), if Fig. 1I As shown, a second sealing layer 40 is formed on the first redistribution layers 10 on the first carrier 50 to cover the chip modules 20a-20d.
[0044] In step (e), the first carrier 50 is removed to expose a surface 11 of each of the first redistribution layers 10 , and a plurality of solder balls 12 are formed on the exposed surface 11 .
[0045] In step (f), if Fig. 1I and Figure 1JAs shown, the second encapsulation layer 40 is cut along the boundary of the adjacent component area 51 to form a plurality of N-layer modular stacked semiconductor components 1; in this embodiment, each of the modular stacked semiconductor components 1 stacks four-layer chip modules 20a-20d and is encapsulated with a second encapsulation body 40'; wherein the stacked die group of each chip module 20a-20d includes two identical die 30a, 30b, which are stacked back to back, and the four sides thereof are flush, as shown in FIG. Figure 1E As shown, the metal contact 31b on the active surface of one die 30b and the exposed end 231 of the conductive through hole 23 form the first pad layer 212, and the metal contact 31a on the active surface of another die 30a is electrically connected to the second pad layer 211 and is covered by the second encapsulant 40'.
[0046] See also FIG. 2B to FIG. 2F , which is a second embodiment of the modular stacking semiconductor packaging method of the present invention, and Figure 1F to Figure 1K The steps (a) to (f) shown are substantially the same, except that the chip modules are made differently in step (a). Figure 2A As shown, a second carrier 60 and a plurality of bare crystals 30, 30b are provided; wherein the second carrier 60 includes a plurality of module areas 61; the second redistribution layer 21 is formed in each of the module areas 61 of the second carrier 60; the metal contacts 31a on the active surface of some bare crystals 30a are flip-chip bonded to the second redistribution layer 21; the active surface portions of the remaining bare crystals 30b are adhered to the back surfaces of the bare crystals 30a on the second redistribution layer 21, and the metal contacts 31b on the active surface are flip-chip bonded to The second redistribution layer 21; a first sealing layer 22 is formed on the second redistribution layers 21 to cover the bare chips 30a, 30b; at least one through hole penetrating the first sealing layer 22 is formed in each module area 61; a metal material is filled in each through hole to form a conductive through hole 23, and one end 231 of each conductive through hole 23 exposed on the surface of the first sealing layer 22 constitutes a first pad layer 212 of each chip module 20, and the other end is electrically connected to the second redistribution layer 21; Figure 2A and Figure 2B As shown, the first encapsulation layer 22 is finally cut along the boundary of the adjacent module area 61 to form a plurality of identical chip modules 20, that is, each chip module 20 is mainly composed of a first encapsulation body 22' encapsulating a stacked die group 30, and the exposed surface of the second redistribution layer 21 is the second pad layer 211 of each chip module 20; in this embodiment, the second pad layer 211 has an exposed pad corresponding to the exposed pad of the first pad layer 212 (that is, the exposed end 231 of the conductive through hole 23).
[0047] After the chip modules 20 are manufactured according to the above description, the following steps are performed: Figure 2C to Figure 2F Steps (b) to (f) are shown.
[0048] In step (b), if Figure 2C As shown, a first redistribution layer 10 is formed on each device region 51 of the first carrier 50 ; in this embodiment, the first redistribution layers 10 are manufactured simultaneously.
[0049] In step (c), if Figure 2C As shown, the chip module 20a of the first layer is first electrically connected to the corresponding first redistribution layer 10, and its second pad layer 211 is upward away from the first redistribution layer 10, and then the chip modules 20b~20d of the second to fourth layers are stacked in sequence and electrically connected to the second pad layer 211 of the previous layer.
[0050] In step (d), if Figure 2D As shown, a second sealing layer 40 is formed on the first redistribution layers 10 on the first carrier 50 to cover the chip modules 20a-20d.
[0051] In step (e), if Figure 2D and Figure 2E As shown, the first carrier 50 is removed to expose a surface 11 of each of the first redistribution layers 10 , and a plurality of solder balls 12 are formed on the exposed surface 11 .
[0052] In step (f), if Figure 2E and Figure 2F As shown, the second encapsulation layer 40 is cut along the boundary of the adjacent device area 51 to form a plurality of N-layer modular stacked semiconductor devices 1a; in this embodiment, each of the modular stacked semiconductor devices 1a stacks four-layer chip modules 20a-20d and is wrapped with a second encapsulation body 40'; Figure 2B and Figure 2E As shown, the stacked die group of each chip module 20a~20d includes two identical die 30a, 30b, and are stacked in the same direction so that the metal contacts 31a, 31b of the two identical die 30a, 30b are exposed and correspond to the second pad layer 211. The at least one conductive through hole 23 connects the first pad layer 212 and the second pad layer 211.
[0053] See also FIG. 3B to FIG. 3F , which is a third embodiment of the modular stacking semiconductor packaging method of the present invention, and Figure 1F to Figure 1K The steps (a) to (f) shown are substantially the same, except that the chip modules 20 are made differently in step (a). Figure 3AAs shown, a second carrier 60 and a plurality of first and second bare crystals 30a~30d are provided; wherein the second carrier 60 includes a plurality of module areas 61; the second redistribution layer 21 is formed in each of the module areas 61 of the second carrier 60; the metal contact 31a on the active surface of the second bare crystal 30a located on the first layer is flip-chip bonded to the second redistribution layer 21; the active surface portion of the first bare crystal 30b located on the second layer is adhered to the back surface of the second bare crystal 30a located on the first layer, and the metal contact 31b on its active surface is flip-chip bonded to the second redistribution layer 21; the back surface of the first bare crystal 30c located on the third layer is fully adhered to the back surface of the first bare crystal 30b located on the second layer, and the metal contact 31c on its active surface corresponds to the first pad layer 212; the back surface portion of the second bare crystal 30d located on the fourth layer is adhered to the active surface of the first bare crystal 30c located on the third layer, and the metal contact 31d on its active surface corresponds to the first pad layer 212. A first sealing layer 22 is formed on the second redistribution layers 21 to cover the first and second bare crystals 30a-30d; at least one through hole penetrating the first sealing layer 22 is formed in each module area 61; a metal material is filled in each through hole to form a conductive through hole 23, and one end 231 of each conductive through hole 23 exposed on the surface of the first sealing layer 22 and the metal contacts 31c, 31d of the first and second bare crystals 30c, 30d of the third and fourth layers form the first pad layer 212 of each chip module 20, and the other end of each conductive through hole 23 is electrically connected to the second redistribution layer 21; please cooperate with Figure 3A and Figure 3B As shown, the first encapsulation layer 22 is finally cut along the boundary of the adjacent module area 61 to form a plurality of identical chip modules 20, that is, each chip module 20 is mainly composed of a first encapsulation body 22' encapsulating a stacked die group 30, and the exposed surface of the second redistribution layer 21 is the second pad layer 211 of each chip module 20; in this embodiment, the second pad layer 211 has an exposed pad corresponding to the exposed pad of the first pad layer 212 (that is, the exposed end 231 of the conductive through hole 23).
[0054] After the chip modules 20 are manufactured according to the above description, the following steps are performed: FIG. 3C to FIG. 3F Steps (b) to (f) are shown.
[0055] In step (b), if Figure 3C As shown, a first redistribution layer 10 is formed on each device region 51 of the first carrier 50 ; in this embodiment, the first redistribution layers 10 are manufactured simultaneously.
[0056] In step (c), if Figure 3CAs shown, the chip module 20a of the first layer is first electrically connected to the corresponding first redistribution layer 10, and its second pad layer 211 is upward away from the first redistribution layer 10, and then the chip modules 20b~20d of the second to fourth layers are stacked in sequence and electrically connected to the second pad layer 211 of the previous layer.
[0057] In step (d), if Figure 3D As shown, a second sealing layer 40 is formed on the first redistribution layers 10 on the first carrier 50 to cover the chip modules 20a-20d.
[0058] In step (e), if Figure 3D and Figure 3E As shown, the first carrier 50 is removed to expose a surface 11 of each of the first redistribution layers 10 , and a plurality of solder balls 12 are formed on the exposed surface 11 .
[0059] In step (f), if Figure 3E and Figure 3F As shown, the second encapsulation layer 40 is cut along the boundary of the adjacent device area 51 to form a plurality of N-layer modular stacked semiconductor devices 1b; in this embodiment, each of the modular stacked semiconductor devices 1b stacks four-layer chip modules 20a-20d and is encapsulated with a second encapsulation body 40'; Figure 3B As shown, the stacked die group 30 of each chip module 20a~20d includes four identical die 30a~30d, wherein the two lower die 30a, 30b are stacked in the same direction and correspond to the second pad layer 211, the two upper die 30c, 30d are stacked in the same direction and correspond to the first pad layer 212, and the two middle die 30b, 30c are fully bonded back to back.
[0060] In summary, the present invention mainly prepares identical chip modules in advance, each chip module already includes a plurality of bare die stacked on each other. When the stack packaging process is performed using these chip modules, the electrical connection defects between the bare die in the chip modules caused by alignment errors are greatly reduced, thereby improving the yield of the stacked multi-layer stacked semiconductor packaging method.
[0061] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.
Claims
1. A modular stacking semiconductor packaging method, characterized in that: The steps include: (a) providing a first carrier and N*M identical chip modules; wherein the first carrier has M component areas, each of the chip modules comprises a stacked die group, a second redistribution layer, a first encapsulation body formed on the second redistribution layer and covering the stacked die group, and at least one conductive through hole; wherein a first exposed surface of the first encapsulation body forms a first pad layer, and a second exposed surface of the second redistribution layer forms a second pad layer opposite to the first exposed surface, and at least one pad of the first pad layer corresponds to at least one pad of the second pad layer, and the at least one conductive through hole connects the first pad layer and the second pad layer; (b) forming a first redistribution layer in each of the component regions of the first carrier; (c) stacking N chip modules on the first redistribution layer in each of the device regions of the first carrier, and the N chip modules are electrically connected to each other; (d) forming a second sealing layer on the M first redistribution layers on the first carrier to cover the N chip modules; (e) removing the first carrier to expose a surface of each of the first redistribution layers, and forming a plurality of solder balls on the exposed surface of each of the first redistribution layers; as well as (f) Cutting the second encapsulation layer along the boundaries of the adjacent device regions to form a plurality of N-layer modular stacked semiconductor devices.
2. The modular stacked semiconductor packaging method according to claim 1, wherein: Wherein the step (c) comprises the following steps: (c1) the first pad layer of each chip module located on the first layer is oriented toward the first carrier board and is electrically connected to the first redistribution layer in the corresponding device area, and the second pad layer of each chip module located on the first layer is oriented toward a direction away from the first redistribution layer; (c2) directing the first pad layers of the chip modules located in the latter layer toward and electrically connecting the second pad layers of the corresponding chip modules located in the former layer, and directing the second pad layers of the chip modules located in the same layer toward a direction away from the corresponding first redistribution layer; and (c3) Repeat step (c2) until N layers of the chip module are stacked.
3. The modular stacked semiconductor packaging method according to claim 2, wherein: The stacked die group of each chip module includes two identical first die, which are stacked back to back and have four flush sides, wherein a first metal contact on the active surface of one of the two first die is electrically connected to the first pad layer, and a first metal contact on the active surface of the other of the two first die is electrically connected to the second pad layer.
4. The modular stacked semiconductor packaging method according to claim 3, wherein: Each chip module further includes two second bare crystals, the back sides of the two second bare crystals are partially arranged on the active surfaces of the corresponding first bare crystals, wherein a second metal contact on the active surface of one of the two second bare crystals is electrically connected to the first metal contact on the active surface of the corresponding first bare crystal to the first pad layer, and the second metal contact on the active surface of the other of the two second bare crystals is electrically connected to the first metal contact on the active surface of the corresponding first bare crystal to the second pad layer.
5. The modular stacked semiconductor packaging method according to claim 2, wherein: The stacked die group of each chip module includes a plurality of identical die, which are stacked in a staggered manner in the same direction, so that a metal contact on the active surface of each die is exposed and corresponds to the second pad layer.
6. The modular stacked semiconductor packaging method according to claim 3, wherein: The same method of manufacturing the N*M chip modules includes the following steps: (s1) providing a second carrier and a plurality of the first bare chips; wherein the second carrier comprises a plurality of module areas; (s2) forming the second redistribution layer in each module area of the second carrier; (s3) flip-chip bonding a portion of the first metal contacts on the active surface of the first die to the second redistribution layer; (s4) fully adhering the back surface of the remaining first die to the back surface of the portion of the first die on the second redistribution layer, with the first metal contact on the active surface facing away from the second redistribution layer; (s5) forming a first sealing layer on the plurality of second redistribution layers to cover the plurality of first bare chips; (s6) forming at least one through hole penetrating the first sealing layer in each module area; (s7) filling the at least one through hole in each module area with metal material to form the conductive through hole; (s8) grinding the first sealing layer to expose the first metal contacts on the active surfaces of the plurality of first bare crystals in step (s4) and form the first pad layer of each chip module together with the exposed ends of each conductive through hole; as well as (s9) Cutting the first sealing layer along the boundaries of adjacent module areas to form a plurality of identical chip modules.
7. The modular stacked semiconductor packaging method according to claim 4, wherein: The same method of manufacturing the N*M chip modules includes the following steps: (s1) providing a second carrier, a plurality of the first bare dies, and a plurality of the second bare dies; wherein the second carrier comprises a plurality of module areas; (s2) forming the second redistribution layer in each module area of the second carrier; (s3) flip-chip bonding the second metal contact on the active surface of the second die on the first layer to the second redistribution layer; (s4) adhering the active surface portion of the first die located on the second layer to the back surfaces of the plurality of second die located on the first layer, and flip-chip bonding the first metal contact on the active surface to the second redistribution layer; (s5) bonding the back surface of the first bare die located on the third layer to the back surfaces of the plurality of first bare die located on the second layer, with the first metal contact on the active surface facing away from the second redistribution layer; (s6) adhering a back surface portion of the second die located on the fourth layer to active surfaces of the plurality of first die located on the third layer, with the second metal contact of the active surface facing away from the second redistribution layer; (s7) forming a first sealing layer on the plurality of second redistribution layers to cover the plurality of first bare dies and the plurality of second bare dies; (s8) forming at least one through hole penetrating the first sealing layer in each module area; (s9) filling the at least one through hole in each module area with metal material to form the conductive through hole; (s10) grinding the first sealing layer to expose the first metal contacts on the active surfaces of the first die on the third layer and the second metal contacts on the active surfaces of the second die on the fourth layer, and forming a first pad layer of each chip module together with the exposed end of each conductive through hole; and (s11) cutting the first sealing layer along the boundaries of the adjacent module areas to form a plurality of identical chip modules.
8. The modular stacked semiconductor packaging method according to claim 5, wherein: The same method of manufacturing the N*M chip modules includes the following steps: (s1) providing a second carrier and a plurality of the bare chips; wherein the second carrier comprises a plurality of module areas; (s2) forming the second redistribution layer in each module area of the second carrier; (s3) flip-chip bonding the metal contacts on a portion of the active surface of the bare die to the second redistribution layer; (s4) adhering the remaining active surface portion of the bare die to the back surface of the bare die on the second redistribution layer, and flip-chip bonding the metal contacts on the active surface to the second redistribution layer; (s5) forming a first sealing layer on the plurality of second redistribution layers to cover the plurality of bare chips; (s6) forming at least one through hole penetrating the first sealing layer in each module area; (s7) filling the at least one through hole in each module area with metal material to form the conductive through hole, wherein one end of each conductive through hole exposed on the surface of the first sealing layer forms the first pad layer of each chip module, and the other end is electrically connected to the second redistribution layer; as well as (s9) Cutting the first sealing layer along the boundaries of the adjacent module areas to form a plurality of identical chip modules.
9. The modular stacking semiconductor packaging method according to any one of claims 6 to 8, characterized in that: The metal material is formed in each of the conductive through holes by electroplating the at least one through hole.