Semiconductor structure manufacturing method and semiconductor structure
By forming a space hole structure on the substrate and building an integrated pad structure therein, the problems of insufficient etching and bridging caused by small pad size are solved, and the yield and performance of semiconductor devices are improved.
Patent Information
- Application Number
- CN202011144602.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-10-23
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2040-10-23
AI Technical Summary
During semiconductor manufacturing, due to the small size of the pad structure and the limitations of the etching process, adjacent pad structures are easily bridged, resulting in defects, and affecting the yield of semiconductor devices.
By forming a plurality of spaced hole structures on the substrate, a first pad structure is formed in the holes, and a second pad structure is formed thereon, forming an integrated structure, and then a conductive layer is formed as a whole and etched, To avoid bridging caused by the limitations of the etching process during the formation of the pad structure.
This method effectively avoids the bridging problem caused by the limitations of the etching process during the formation of the pad structure, improves the yield of the semiconductor device, and ensures the integrity and performance of the pad structure.
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Figure CN114496926B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure manufacturing method and a semiconductor structure. Background Art
[0002] With the gradual development of storage device technology, dynamic random access memory (DRAM) has been gradually applied in various electronic devices with its high density and fast read and write speed. Dynamic random access memory is composed of many repeated storage cells. Each storage cell usually includes a capacitor structure and a transistor structure. The gate of the transistor structure is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor structure; the voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor structure through the bit line, or write the data information into the capacitor structure through the bit line for storage.
[0003] In the related art, the transistor structure is arranged in the substrate, and a plurality of pad structures are arranged on the substrate, and each pad structure is connected to the source of a transistor structure. During the manufacturing process, a conductive layer is first formed on the substrate, and then the conductive layer is etched to remove part of the conductive layer to form a plurality of pad structures arranged in an array; then an insulating support layer is formed between the pad structures to fill the gaps between adjacent pad structures.
[0004] Since the pad structure is small in size, insufficient etching may easily occur during etching due to the limitation of the etching process, resulting in bridging between adjacent pad structures and further causing defects. Summary of the invention
[0005] In view of this, an embodiment of the present invention provides a semiconductor structure manufacturing method and a semiconductor structure to solve the technical problem that the size of the pad structure is small, and during etching, insufficient etching is prone to occur due to the limitations of the etching process, resulting in bridging between adjacent pad structures and further causing defects.
[0006] An embodiment of the present invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate comprising a plurality of active area structures and a plurality of first hole structures arranged at intervals; forming a first pad structure in the first hole structure, the first pad structure being flush with the substrate with a surface facing away from the substrate, and the first pad structure being electrically connected to the active area structure; forming a second pad structure on the first pad structure, the second pad structure being bonded to the first pad structure, and the second pad structure being connected to a capacitor structure.
[0007] In some embodiments that may include the above embodiments, forming a first pad structure in the first hole structure includes:
[0008] A barrier layer is formed on the side walls and bottom walls of the first hole structure and the surface of the substrate; a first conductive layer is formed on the barrier layer, and the barrier layer and the first conductive layer completely fill the first hole structure; a portion of the barrier layer and a portion of the first conductive layer are removed to form a first pad structure located in the first hole.
[0009] In some embodiments that may include the above embodiments, removing a portion of the barrier layer and a portion of the first conductive layer to form a first pad structure located in the first hole includes:
[0010] The first conductive layer and the barrier layer outside the first hole are removed so that the surfaces of the first conductive layer and the barrier layer facing away from the substrate are flush with the substrate; a first supporting layer, a mask layer and a photolithography layer with a pattern are deposited on the first conductive layer, the barrier layer and the substrate; and the photolithography layer is used as a mask to remove part of the first conductive layer and the barrier layer to form the first pad structure.
[0011] In some embodiments that may include the above embodiments, using the photolithography layer as a mask to remove a portion of the first conductive layer and the barrier layer to form the first pad structure includes:
[0012] Using the photoresist layer as a mask, part of the mask layer is etched to form a mask layer with a pattern; removing the photoresist layer, and using the mask layer as a mask, part of the first supporting layer is etched to form a first supporting layer with a pattern; removing the mask layer, and using the first supporting layer as a mask, part of the first conductive layer and part of the blocking layer are etched to form the first pad structure.
[0013] In some embodiments that may include the above embodiments, a second hole structure is formed in the first supporting layer and the first hole structure while the first pad structure is formed.
[0014] In some embodiments that may include the above embodiments, forming a second pad structure on the first pad structure, wherein the second pad structure is bonded to the first pad structure comprises:
[0015] A second supporting layer is deposited in the second hole structure, and the second supporting layer fills up the second hole structure; the first supporting layer is removed, and a third hole structure is formed in the second supporting layer; a second conductive layer is deposited in the third hole structure, and the second conductive layer fills up the third hole structure, to form the second pad structure.
[0016] In some embodiments, which may include the above embodiments, an etching selectivity ratio between the material of the first supporting layer and the material of the second supporting layer is greater than 100.
[0017] In some embodiments, which may include the above embodiments, the first conductive layer and the second conductive layer are made of the same material.
[0018] In some embodiments that may include the above embodiments, the substrate further includes a bit line structure and a capacitor contact structure, the first pad structure is connected to the capacitor contact structure, and the capacitor contact structure is connected to the active area structure.
[0019] An embodiment of the present invention further provides a semiconductor structure, which is manufactured by any of the above-mentioned semiconductor structure manufacturing methods.
[0020] The semiconductor structure manufacturing method and semiconductor structure provided in the present embodiment have a plurality of active area structures and a plurality of first hole structures arranged at intervals on the substrate, a first pad structure is formed in the first hole structure, and the first pad structure is electrically connected to the active area structure; a second pad structure is formed on the first pad structure, the second pad structure is bonded to the first pad structure, and the second pad structure is connected to the capacitor structure; compared with first forming an entire conductive layer and then etching the conductive layer to form a pad structure, this method can avoid the problem of bridging adjacent pad structures due to the limitations of the etching process during the formation of the pad structure, thereby forming defects, thereby ensuring the yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0022] Figure 1 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;
[0023] Figure 2 A schematic diagram of a structure after a first hole structure is formed in a semiconductor structure manufacturing method provided by an embodiment of the present invention;
[0024] Figure 3 for Figure 2 A top view of
[0025] Figure 4 A schematic diagram of a structure after a first conductive layer is formed in a semiconductor structure manufacturing method provided by an embodiment of the present invention;
[0026] Figure 5 A schematic diagram of the structure after removing the first conductive layer outside the first hole structure in the semiconductor structure manufacturing method provided by an embodiment of the present invention;
[0027] Figure 6 for Figure 5 A top view of
[0028] Figure 7 A schematic diagram of a structure after a first supporting layer and a mask layer are formed in a semiconductor structure manufacturing method provided in an embodiment of the present invention;
[0029] Figure 8 A schematic diagram of a structure after a photolithography layer with a pattern is formed in a semiconductor structure manufacturing method provided by an embodiment of the present invention;
[0030] Fig. 9 A schematic diagram of the structure after etching the mask layer using the photolithography layer as a mask in the semiconductor structure manufacturing method provided by an embodiment of the present invention;
[0031] Fig.10 for Fig. 9 A top view of
[0032] Fig.11 A schematic diagram of the structure after etching the first supporting layer using the mask layer as a mask in the semiconductor structure manufacturing method provided by an embodiment of the present invention;
[0033] Fig.12 for Fig.11 A top view of
[0034] Fig.13 A schematic diagram of the structure after the second supporting layer is formed in the semiconductor structure manufacturing method provided by an embodiment of the present invention;
[0035] Fig.14 for Fig.13 A top view of
[0036] Fig.15 A schematic diagram of a structure after a third hole structure is formed in the semiconductor structure manufacturing method provided by an embodiment of the present invention;
[0037] Fig.16 A schematic diagram of a structure after a second conductive layer is formed in a semiconductor structure manufacturing method provided by an embodiment of the present invention;
[0038] Fig.17 A schematic diagram of a structure after a second pad structure is formed in a semiconductor structure manufacturing method provided by an embodiment of the present invention;
[0039] Fig.18 for Fig.17 Top view of the .
[0040] Description of reference numerals:
[0041] 10: substrate;
[0042] 20: first conductive layer;
[0043] 30: barrier layer;
[0044] 40: first supporting layer;
[0045] 50: mask layer;
[0046] 60: photolithography layer;
[0047] 70: second supporting layer;
[0048] 80: second conductive layer;
[0049] 101: Active region structure;
[0050] 102: insulation layer;
[0051] 103: shallow trench isolation structure;
[0052] 104: Capacitor contact structure;
[0053] 105: first hole structure;
[0054] 106: bit line structure;
[0055] 107: First bit line structure;
[0056] 108: second bit line structure;
[0057] 109: bit line blocking layer;
[0058] 201: first pad structure;
[0059] 401: second hole structure;
[0060] 501: blocking hole;
[0061] 601: Etching holes;
[0062] 701: third hole structure;
[0063] 801: Second pad structure. DETAILED DESCRIPTION
[0064] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0065] Dynamic random access memory (DRAM) includes a capacitor structure and a transistor structure. The gate of the transistor structure is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor structure. By controlling the opening or closing of the transistor, data in the capacitor structure can be read or written into the capacitor structure.
[0066] The transistor structure is often arranged in a substrate, and a pad structure is arranged on the substrate, and each pad structure is electrically connected to the source of the transistor structure. During the manufacturing process, a conductive layer (such as tungsten, etc.) is first formed on the substrate, and then the conductive layer is etched to remove part of the conductive layer to form a plurality of pad structures arranged in an array on the substrate; then an insulating support layer is formed between each pad structure to fill the gap between adjacent pad structures.
[0067] However, with the gradual miniaturization of dynamic random access memory, the size of the pad structure is smaller. During etching, insufficient etching is prone to occur due to the limitations of the etching process, resulting in the inability to completely separate adjacent pad structures, that is, bridging between adjacent pad structures, which in turn causes defects and reduces the yield of semiconductor devices.
[0068] An embodiment of the present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, wherein a plurality of first hole structures arranged at intervals are first formed on a substrate, a first pad structure is then formed in the first hole structure, and a second pad structure is then formed on the first pad structure, wherein the first pad structure and the second pad structure constitute an integrated structure; compared with first forming the entire conductive layer and then etching the conductive layer to form a pad structure, this method can avoid the problem of bridging of adjacent pad structures and the formation of defects due to the limitations of the etching process during the formation of the pad structure, thereby ensuring the yield of the semiconductor device.
[0069] Reference Figure 1 , Figure 1 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention; Figures 2 to 18 This is a schematic diagram of the various stages of semiconductor structure production. Figures 1 to 18 The method of manufacturing semiconductor structures is introduced.
[0070] The present embodiment does not limit the semiconductor structure. The semiconductor structure will be described below by taking a dynamic random access memory (DRAM) as an example, but the present embodiment is not limited thereto. The semiconductor structure in the present embodiment may also be other structures.
[0071] like Figure 1 As shown, the semiconductor structure manufacturing method provided in this embodiment includes:
[0072] S101: providing a substrate, wherein the substrate comprises a plurality of active area structures and a plurality of first hole structures arranged at intervals.
[0073] For example, Figure 2 and Figure 3 As shown, the substrate 10 may include a plurality of shallow trench isolation structures 103 and a plurality of active area structures 101 arranged at intervals. In addition, a plurality of first hole structures 105 arranged at intervals are formed on the substrate 10.
[0074] Furthermore, the shallow trench isolation structure 103 may be made of materials including silicon oxide.
[0075] Continue to refer to Figure 1 The semiconductor structure manufacturing method provided in this embodiment further includes:
[0076] S102: forming a first pad structure in the first hole structure, wherein a surface of the first pad structure facing away from the substrate is flush with the substrate, and the first pad structure is electrically connected to the active area structure.
[0077] For example, Fig.11 and Fig.12 As shown, a first pad structure 201 is formed in each first hole structure 105; specifically, a first pad structure 201 is formed in each first hole structure 105, the surface of the first pad structure 201 facing away from the substrate 10 is flush with the surface of the substrate 10, and the first pad structure 201 is electrically connected to the active area structure 101 in the substrate 10.
[0078] After forming the first pad structure 201, the method further includes:
[0079] S103: forming a second pad structure on the first pad structure, the second pad structure is bonded to the first pad structure, and the second pad structure is connected to the capacitor structure.
[0080] For example, Fig.17 and Fig.18 As shown, a second pad structure 801 is formed on the first pad structure 201 , and the second pad structure 801 is bonded to the first pad structure 201 , so that the first pad structure 201 and the second pad structure 801 form an integrated structure.
[0081] In this embodiment, after forming the second pad structure 801, a capacitor structure is subsequently formed. The second pad structure 801 is connected to the capacitor structure, so that the capacitor structure can be connected to the active area structure 101 through the second pad structure 801 and the first pad structure 201, thereby realizing electrical connection between the capacitor structure and the source in the transistor structure in the dynamic random access memory.
[0082] Continue to refer to Figure 2In this embodiment, the substrate 10 further includes a bit line structure 106 and a capacitor contact structure 104 , an insulating layer 102 is formed on the bit line structure 106 , the first pad structure 201 is connected to the capacitor contact structure 104 , and the capacitor contact structure 104 is connected to the active area structure 101 .
[0083] Exemplarily, the bit line structure 106 may include a first bit line structure 107 and a second bit line structure 108 which are stacked. The first bit line structure 107 may be made of polysilicon, the second bit line structure 108 may be made of tungsten, and the insulating layer 102 may be made of silicon nitride.
[0084] Furthermore, the bit line structure 106 further includes a bit line barrier layer 109 located between the first bit line structure 107 and the second bit line structure 108. The bit line barrier layer 109 can prevent the first bit line structure 107 and the second bit line structure 108 from penetrating each other while realizing electrical connection between the first bit line structure 107 and the second bit line structure 108, thereby affecting the electrical performance of the semiconductor device. Exemplarily, the material of the bit line barrier layer 109 can include titanium nitride, etc.
[0085] In the above implementation, if Fig.11 As shown, the first pad structure 201 is connected to the active area structure 101 through the capacitor contact structure 104, the capacitor contact structure 104 and the bit line structure 106 are arranged in the substrate 10 at intervals, the capacitor contact structure 104 is arranged on the side of each first hole structure 105 facing the active area structure 101, and each capacitor contact structure 104 corresponds to a first hole structure 105, so that after the first pad structure 201 is formed in the first hole structure 105, the first pad structure 201 can be electrically connected to the corresponding active area structure 105 through the capacitor contact structure 104. Exemplarily, the material of the capacitor contact structure 104 may include a conductive material such as polysilicon, and this embodiment does not limit the material of the capacitor contact structure 104.
[0086] The semiconductor structure manufacturing method provided in the present embodiment has a plurality of active area structures 101 and a plurality of first hole structures 105 arranged at intervals on the substrate 10, a first pad structure 201 is formed in the first hole structure 105, and the first pad structure 201 is electrically connected to the active area structure 101; a second pad structure 801 is formed on the first pad structure 201, the second pad structure 801 is bonded to the first pad structure 201, and the second pad structure 801 is connected to the capacitor structure; compared with first forming an entire conductive layer and then etching the conductive layer to form a pad structure, this method can avoid the problem of bridging of adjacent pad structures due to the limitations of the etching process during the formation of the pad structure, thereby forming defects, thereby ensuring the yield of the semiconductor device.
[0087] The semiconductor structure manufacturing method provided in this embodiment forms a first pad structure 201 in the first hole structure 105, comprising:
[0088] like Figure 4-Figure 12 As shown, a barrier layer 30 is formed on the side walls and bottom walls of the first hole structure 105, and on the surface of the substrate 10; a first conductive layer 20 is formed on the barrier layer 30, and the barrier layer 30 and the first conductive layer 20 completely fill the first hole structure 105; a portion of the barrier layer 30 and a portion of the first conductive layer 20 are removed to form a first pad structure 201 located in the first hole.
[0089] In this way, the barrier layer 30 can prevent the first conductive layer 20 from penetrating into the substrate 10, thereby ensuring the performance of the semiconductor device. In the implementation mode in which the first pad structure 201 is connected to the active area structure 101 through the capacitor contact structure 104, when the barrier layer 30 is formed, the barrier layer 30 covers the sidewall of the first hole structure 105, the surface of the capacitor contact structure 104 in the first hole structure 105, and the surface of the substrate 10. The barrier layer 30 can prevent the first conductive layer 20 from penetrating into the capacitor contact structure 104, thereby improving the performance of the semiconductor structure.
[0090] Exemplarily, the material of the barrier layer 30 may include a conductive material such as titanium nitride, so as to prevent the penetration between the first conductive layer 20 and the capacitor contact structure 104 and realize the electrical connection between the first conductive layer 20 and the capacitor contact structure 104. The material of the first conductive layer 20 may include a conductive material such as tungsten,
[0091] In this embodiment, removing a portion of the barrier layer 30 and a portion of the first conductive layer 20 to form a first pad structure 201 located in the first hole structure 105 includes:
[0092] Reference Figure 4-Figure 6 , remove the first conductive layer 20 and the barrier layer 30 outside the first hole structure 105 , so that the surfaces of the first conductive layer 20 and the barrier layer 30 facing away from the substrate 10 are flush with the substrate 10 .
[0093] Since when the first conductive layer 20 and the barrier layer 30 are formed, the first conductive layer 20 and the barrier layer 30 are not only filled in the first hole structure 105, but also cover the substrate 10; after removing the first conductive layer 20 and the barrier layer 30 outside the first hole structure 105, only the first conductive layer 20 and the barrier layer 30 located in the first hole structure 105 are retained; and the surfaces of the first conductive layer 20 and the barrier layer 30 facing away from the substrate 10 are parallel to the surface of the substrate 10, so as to facilitate the formation of subsequent film layers. Exemplarily, the first conductive layer 20 and the barrier layer 30 outside the first hole structure 105 can be removed by processes such as chemical mechanical polishing (CMP).
[0094] Afterwards, if Figure 7-Figure 12 As shown, a first supporting layer 40, a mask layer 50 and a photolithography layer 60 with a pattern are deposited on the first conductive layer 20, the barrier layer 30 and the substrate 10; the photolithography layer 60 is used as a mask to remove part of the first conductive layer 20 and part of the barrier layer 30 to form a first pad structure 201.
[0095] Through the above arrangement, the photolithography layer 60 is used as a mask to remove part of the first conductive layer 20 and part of the blocking layer 30 , and the etching accuracy is high, thereby improving the performance of the semiconductor structure.
[0096] Further, using the photolithography layer 60 as a mask to remove a portion of the first conductive layer 20 and a portion of the barrier layer 30 to form the first pad structure 201 includes:
[0097] like Figure 8-Figure 10 As shown, a portion of the mask layer 50 is etched using the photolithography layer 60 as a mask to form a mask layer 50 having a pattern. Exemplarily, the photolithography layer 60 has a pattern, so that the photolithography layer 60 has a plurality of etching holes 601, and the projection of each etching hole 601 on the first hole structure 105 covers a portion of the first conductive layer 20 and a portion of the blocking layer 30 in the first hole structure 105; when the mask layer 50 is etched using the photolithography layer 60 as a mask, a blocking hole 501 is formed on the mask layer 50 corresponding to the etching hole 601 to form a mask layer 50 having a pattern.
[0098] Afterwards, the photoresist layer 60 is removed, and a portion of the first supporting layer 40 is etched using the patterned mask layer 50 as a mask to form a patterned first supporting layer 40. Exemplarily, the first supporting layer 40 corresponding to the blocking hole 501 is removed to form a patterned first supporting layer 40.
[0099] like Fig.11 and Fig.12 As shown, the mask layer 50 is removed, and a portion of the first conductive layer 20 and a portion of the barrier layer 30 are etched using the first supporting layer 40 having a pattern as a mask to form a first pad structure 201. The first pad structure 201 includes the remaining first conductive layer 20 etched and the remaining barrier layer 30 etched. Since the projection of the etching hole 601 on the photolithography layer 60 on the first hole structure 105 covers a portion of the first conductive layer 20 and a portion of the barrier layer 30 in the first hole structure 105, when the first conductive layer 20 and the barrier layer 30 are etched using the first supporting layer 40 as a mask, only a portion of the first conductive layer 20 and a portion of the barrier layer 30 in the first hole structure 105 are removed to form a hole-like structure on the first conductive layer 20 in the first hole.
[0100] Through the above arrangement, part of the first conductive layer 20 and part of the blocking layer 30 in the first hole structure 105 are removed by pattern transfer of the photolithography layer 60, the mask layer 50 and the first support layer 40 in sequence, thereby further improving etching accuracy.
[0101] In this embodiment, the first supporting layer 40 is used as a mask to remove part of the first conductive layer 20 and part of the barrier layer 30 in the first hole structure 105, and at the same time, a first pad structure 201 having a hole structure is formed in the first hole structure 105. At the same time, a second hole structure 401 is formed in the first supporting layer 40 and the first hole structure 105. Such a configuration facilitates the subsequent formation of a semiconductor structure.
[0102] Further, forming a second pad structure 801 on the first pad structure 201, and bonding the second pad structure 801 to the first pad structure 201 includes:
[0103] like Figure 13-Figure 18 As shown, a second supporting layer 70 is deposited in the second hole structure 401, and the second supporting layer 70 completely fills the second hole structure 401; the first supporting layer 40 is removed, and a third hole structure 701 is formed in the second supporting layer 70; a second conductive layer 80 is deposited in the third hole structure 701, and the second conductive layer 80 completely fills the third hole structure 701, forming a second pad structure 801. Since the projection of the first supporting layer 40 on the first hole structure 105 covers part of the first pad structure 201 in the first hole structure 105, the second pad structure 801 formed in the third hole structure 701 is bonded to the first pad structure 201, thereby achieving connection between the second pad structure 801 and the first pad structure 201.
[0104] A second pad structure is formed in each third hole structure 701. In this way, the second pad structure 801 is formed in the third hole structure 701, which avoids the problem of adjacent second pad structures 801 being bridged due to the limitation of the etching process during the formation of the second pad structure 80, thereby ensuring the yield of the semiconductor device.
[0105] Exemplarily, when forming the second conductive layer 80, the second conductive layer 80 fills the third hole structure 701 and covers the second supporting layer 70; accordingly, after forming the second conductive layer 80, the second conductive layer 80 outside the third hole structure 701 can be removed by a process such as chemical mechanical polishing (CMP) to form a second pad structure 801 inside the third hole structure 701. The second pad structure 801 only includes the remaining second conductive layer 80.
[0106] In the above implementation, the etching selectivity ratio of the material of the first support layer 40 to the material of the second support layer 70 is greater than 100. In this way, the etching selectivity of the first support layer 40 and the second support layer 70 is relatively large, and when the first support layer 40 is removed by etching, damage to the second support layer 70 can be avoided, thereby improving the precision of the second support layer 70 and improving the performance of the semiconductor device. Among them, the material of the first support layer 40 can be silicon thin film, etc., and the material of the second support layer 70 can be silicon nitride, etc.
[0107] In this embodiment, the first conductive layer 20 and the second conductive layer 80 are made of the same material. This arrangement can reduce the resistance between the first pad structure 201 and the second pad structure 801, thereby improving the performance of the semiconductor structure. Exemplarily, the first conductive layer 20 and the second conductive layer 80 can both be made of tungsten.
[0108] Continue to refer to Figure 2-Figure 17 This embodiment also provides a semiconductor structure, which is manufactured by the semiconductor structure manufacturing method provided by any of the above embodiments.
[0109] The semiconductor structure provided in this embodiment has a plurality of active area structures 101 and a plurality of first hole structures 105 arranged at intervals on a substrate 10, a first pad structure 201 is formed in the first hole structure 105, and the first pad structure 201 is electrically connected to the active area structure 101; a second pad structure 801 is formed on the first pad structure 201, the second pad structure 801 is bonded to the first pad structure 201, and the second pad structure 801 is connected to the capacitor structure; compared with first forming an entire conductive layer and then etching the conductive layer to form a pad structure, the problem of bridging of adjacent pad structures due to the limitations of the etching process during the formation of the pad structure, thereby avoiding the problem of defects, thereby ensuring the yield of the semiconductor device.
[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a plurality of active area structures, a plurality of bit line structures located on the plurality of active area structures, an insulating layer located on the plurality of bit line structures, and a plurality of first hole structures arranged at intervals and penetrating the insulating layer; forming a barrier layer on the sidewalls and bottom wall of the first hole structure and the top surface of the insulating layer; forming a first conductive layer on the barrier layer, wherein the barrier layer and the first conductive layer fully fill the first hole structure; removing the first conductive layer and the barrier layer outside the first hole structure, so that the surfaces of the first conductive layer and the barrier layer facing away from the substrate are flush with the top surface of the insulating layer; forming a first supporting layer having a pattern on the first conductive layer, the barrier layer and the insulating layer, wherein the first supporting layer having a pattern exposes a portion of the top surface of the insulating layer, a portion of the first conductive layer and a portion of the barrier layer; Using the first supporting layer with the pattern as a mask, etching a portion of the first conductive layer and a portion of the barrier layer to form a first pad structure located in the first hole structure and a second hole structure located in the first supporting layer and the first hole structure, wherein the first pad structure is electrically connected to the active area structure respectively; Depositing a second supporting layer in the second hole structure, wherein the second supporting layer completely fills the second hole structure, and the second supporting layer covers the portion of the top surface of the insulating layer; removing the first supporting layer having the pattern, and forming a third hole structure in the second supporting layer; A second pad structure is formed in the third hole, and the second pad structure is electrically connected to the first pad structure respectively.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The etching selectivity ratio between the material of the first supporting layer and the material of the second supporting layer is greater than 100.
3. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first conductive layer and the second pad structure are made of the same material.
4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The first conductive layer and the second pad structure are both made of tungsten.
5. The method for manufacturing a semiconductor structure according to claim 1, wherein: Removing the first conductive layer and the barrier layer outside the first hole structure so that the surfaces of the first conductive layer and the barrier layer facing away from the substrate are flush with the top surface of the insulating layer, comprising: The first conductive layer and the barrier layer outside the first hole structure are removed by a chemical mechanical polishing process.
6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The material of the barrier layer includes titanium nitride.
7. The method for manufacturing a semiconductor structure according to claim 1, wherein: The substrate further includes a capacitor contact structure, the first pad structure is connected to the capacitor contact structure, and the capacitor contact structure is connected to the active area structure.
8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that After forming the second pad structure, the method further includes: A capacitor structure is formed, wherein the capacitor structure is connected to the second pad structure.
9. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing the semiconductor structure according to any one of claims 1 to 8.