Three-dimensional memory and its fabrication method, memory system

Abstract

This application provides a three-dimensional memory and a method for fabricating the same. The three-dimensional memory includes: a semiconductor layer; a stacked structure located on the semiconductor layer; a plurality of gate line slot structures penetrating the stacked structure; and a plurality of isolation portions penetrating a portion of the stacked structure near the semiconductor layer and respectively covering at least a portion of each gate line slot structure. The three-dimensional memory and fabrication method provided by this application can reduce the risk of short-circuit leakage between conductive layers in the stacked structure, thereby improving the electrical performance of the fabricated three-dimensional memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to three-dimensional memory and its fabrication method and memory system. Background Technology

[0002] To increase storage capacity per unit area, three-dimensional memory (e.g., 3D NAND) has emerged, extending vertically. Three-dimensional memory typically includes channel structures formed within a stacked structure. The conductive layers and corresponding portions of the channel structures within the stacked structure together form memory cells, arranging the memory cells one-dimensionally in a direction perpendicular to the substrate. When multiple channel structures are formed within the stacked structure, the memory cells form a three-dimensional array relative to the substrate. Furthermore, three-dimensional memory typically includes gate slot structures. These gate slot structures can be used to divide the memory cell array into memory blocks. Summary of the Invention

[0003] This application provides a three-dimensional memory. The three-dimensional memory includes: a semiconductor layer; a stacked structure located on the semiconductor layer; a plurality of gate line slot structures penetrating the stacked structure; and a plurality of isolation portions penetrating a portion of the stacked structure near the semiconductor layer and respectively covering at least a portion of each gate line slot structure.

[0004] In some embodiments, the stacked structure is divided into a first region and a second region along a first direction parallel to the semiconductor layer, and a plurality of gate line slot structures include at least one first gate line slot structure extending continuously along the first direction within the first region and the second region; and a plurality of isolation portions include at least one first isolation portion within the first region and the second region, each first isolation portion covering at least a portion of each first gate line slot structure.

[0005] In some embodiments, in the first direction, the length of the first isolation portion is less than the length of the first grid line slot structure.

[0006] In some implementations, the first isolation portion is symmetrically distributed in the first region and the second region.

[0007] In some embodiments, the three-dimensional memory includes a plurality of channel structures and a plurality of dummy channel structures, the plurality of channel structures being formed in a first region with a first distribution density, and the plurality of dummy channel structures being formed in a second region with a second distribution density, the first distribution density being different from the second distribution density.

[0008] In some embodiments, the plurality of gate line slot structures include at least one second gate line slot structure extending discontinuously along a first direction in a first region and a second region; and the plurality of isolation portions include at least one second isolation portion, each second isolation portion covering the discontinuity of each second gate line slot structure.

[0009] In some embodiments, in the first direction, the length of the second isolation portion is greater than the length of the discontinuous region of the second grid line slot structure.

[0010] In some embodiments, in a second direction parallel to the semiconductor layer, the critical dimensions of the first gate gap structure and the second gate gap structure gradually decrease along the direction toward the semiconductor layer, and the second direction is perpendicular to the first direction.

[0011] In some embodiments, both the first isolation portion and the second isolation portion are made of dielectric material.

[0012] In some embodiments, the stacked structure includes a first stacked structure and a second stacked structure in sequence along the direction away from the semiconductor layer, and the three-dimensional memory also includes a bottom select gate cutout structure, wherein the first isolation portion, the second isolation portion and the bottom select gate cutout structure penetrate through the first stacked structure.

[0013] Embodiments of this application also provide a memory system. The memory system includes: at least one three-dimensional memory as described in the embodiments above; and a controller electrically connected to the at least one three-dimensional memory and configured to control the at least one three-dimensional memory.

[0014] The embodiments of this application also provide a method for fabricating a three-dimensional memory. The method includes: forming an initial stacked structure on a substrate; forming a plurality of initial isolation portions in the initial stacked structure; forming a plurality of gate line slot structures penetrating the initial stacked structure; and transforming the plurality of initial isolation portions into a plurality of isolation portions, such that the plurality of isolation portions penetrate a portion of the initial stacked structure near the substrate and respectively cover at least a portion of each gate line slot structure.

[0015] In some embodiments, the initial stacked structure is divided into a first region and a second region along a first direction parallel to the substrate to form a plurality of gate line slot structures that initially penetrate the stacked structure, and transforming the plurality of initial isolation portions into a plurality of isolation portions includes: forming at least one first gate line slot structure that extends continuously along the first direction in the first region and the second region, and transforming at least one of the plurality of initial isolation portions into at least one first isolation portion in the first region and the second region, wherein each first isolation portion covers at least a portion of each first gate line slot structure.

[0016] In some embodiments, forming a plurality of gate line slot structures through the initial stacked structure and transforming a plurality of initial isolation portions into a plurality of isolation portions includes: forming at least one second gate line slot structure extending discontinuously along a first direction in a first region and a second region, and transforming at least one of the plurality of initial isolation portions into at least one second isolation portion, each second isolation portion covering the discontinuity of each second gate line slot structure.

[0017] In some embodiments, the initial stacked structure sequentially includes a first initial stacked structure and a second initial stacked structure along a direction away from the substrate, and forming a plurality of initial isolation portions in the initial stacked structure includes forming a plurality of initial isolation portions that penetrate the first initial stacked structure.

[0018] In some embodiments, both the first isolation portion and the second isolation portion are made of dielectric material.

[0019] According to some embodiments of the present application, the three-dimensional memory and its fabrication method and memory system are provided. By forming an isolation portion that covers at least a portion of the gate wire gap structure, the sharp corners generated during the process of forming the gate wire gap structure can be extended into the isolation portion, thereby reducing the risk of leakage paths between the conductive material remaining in the sharp corners and the conductive layers in the stacked structure in subsequent processes, and thus improving the electrical performance of the three-dimensional memory. Attached Figure Description

[0020] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0021] Figure 1 This is a top-view schematic diagram of the fabrication process of three-dimensional memory in related technologies;

[0022] Figure 2A It is based on Figure 1 The diagram shows a cross-sectional view of the three-dimensional memory taken along section line I-I'.

[0023] Figure 2B It is based on Figure 2A The diagram shows a cross-sectional view of a three-dimensional memory after the "gate replacement" process.

[0024] Figure 3A It is based on Figure 1 The diagram shows a cross-sectional view of the three-dimensional memory taken along section line II-II'.

[0025] Figure 3B It is based on Figure 3A The diagram shows a cross-sectional view of a three-dimensional memory after the "gate replacement" process.

[0026] Figure 4This is a flowchart of a method for fabricating a three-dimensional memory according to an embodiment of this application;

[0027] Figures 5A to 5H This is a cross-sectional schematic diagram of a method for fabricating a three-dimensional memory according to an embodiment of this application;

[0028] Figures 6A to 6D This is a top view schematic diagram of a method for fabricating a three-dimensional memory according to an embodiment of this application;

[0029] Figures 7A to 7C This is a schematic diagram of the structure of a three-dimensional memory according to another embodiment of this application;

[0030] Figure 8 This is a system block diagram of a memory system according to an embodiment of this application; and

[0031] Figure 9A and 9B This is a schematic diagram of a memory system according to an embodiment of this application. Detailed Implementation

[0032] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the feature.

[0034] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0035] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formalized manner unless expressly so specified herein.

[0036] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer can extend over the entire lower or upper layer structure, or can have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer can be located at or between any set of horizontal planes on or between the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can contain multiple layers.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Some embodiments of this application will now be described in detail with reference to the accompanying drawings. In the various drawings of this application, the x-direction and y-direction represent two vertical directions in a three-dimensional memory. For example, the x-direction may be the word line (WL) direction of the three-dimensional memory, and the y-direction may be the bit line (BL) direction of the three-dimensional memory.

[0038] The features, principles and other aspects of this application are described in detail below.

[0039] In some related 3D memory technologies, gate slot structures are typically formed by etching gate slots (trenches) and creating a filling structure within the gate slots. However, during the etching process, the morphology of the gate slots or the stress of adjacent structures may cause defects similar to mouse bites on the trench sidewalls. These defects can lead to leakage paths between adjacent conductive layers after replacement during the "gate replacement" process using gate slots, thus affecting the electrical performance of the 3D memory.

[0040] Figure 1 This is a top-view schematic diagram of the fabrication process of the three-dimensional memory 100' in related technologies. Figure 2A It is based on Figure 1 The diagram shown is a cross-sectional view of the three-dimensional memory 100' taken along section line I-I'. Figure 2B It is based on Figure 2A The diagram shows a cross-sectional view of the three-dimensional memory 100' after the "gate replacement" process.

[0041] like Figure 1 and 2A As shown, the three-dimensional memory 100' may include a substrate 111' and a stacked structure 112' located on the substrate 111'. Viewed from a direction perpendicular to the substrate 111', the stacked structure 112' is divided into a first region A' and a second region B' along the x-direction. A plurality of channel structures (e.g., 131) are formed in the first region A' with a first distribution density, and a plurality of dummy channel structures (e.g., 132') are formed in the second region B' with a second distribution density different from the first distribution density.

[0042] In an exemplary embodiment, after forming a plurality of channel structures (e.g., 131') and a plurality of dummy channel structures (e.g., 132'), a plurality of gate slots (e.g., first gate slot 121' and second gate slot 122') arranged in the y-direction and extending parallel to each other in the x-direction can be formed, and the plurality of gate slots can span a first region A' and a second region B'. Exemplarily, the first gate slots 121' extending continuously in the x-direction can divide the three-dimensional memory 100' into memory blocks. Adjacent first gate slots 121' may include, for example, two second gate slots 122', which further divide the memory blocks into finger memory blocks. Each second gate slot 122' is broken within a predetermined region in its extension direction, thereby forming a plurality of second gate slot portions 122-1', 122-2', with a discontinuity region 123' between adjacent second gate slot portions 122-1' and 122-2'.

[0043] In an exemplary embodiment, for the process of forming the first gate line slot 121', because the distribution densities of the channel structure 131' and the dummy channel structure 132' formed in the stacked structure 112' are different in the first region A' and the second region B', the stress of the stacked structure 112' to which the first gate line slot 121' is to be formed is different in the first region A' and the second region B'. During the process of etching the stacked structure 112' to form the first gate line slot 121', the etching material is affected by the stress of the stacked structure 112', which may cause the sidewall of the first gate line slot 121' located near the junction of the first region A' and the second region B' to develop sharp corners similar to mouse bites. For example, Figure 2AThe sharp corner 116' extending into the stacked structure 112' between the gate sacrificial layers 114a' and 114b' is shown, and this sharp corner 116' connects the adjacent gate sacrificial layers 114a' and 114b'. In subsequent processes, such as... Figure 2B As shown, through the first grid line slot 121' Figure 2A During the process of replacing the multiple gate sacrificial layers (e.g., 114a' and 114b') in the illustrated stacked structure 112' with conductive layers (e.g., 115a' and 115b'), conductive material 117' may remain in... Figure 2A Within the pointed corner 116' shown, adjacent conductive layers 115a' and 115b' are shorted and leak current through conductive material 117'.

[0044] Figure 3A It is based on Figure 1 The diagram shown is a cross-sectional view of the three-dimensional memory 100' taken along section line II-II'. Figure 3B It is based on Figure 3A The diagram shows a cross-sectional view of the three-dimensional memory 100' after the "gate replacement" process.

[0045] In an exemplary implementation, such as Figure 1 and Figure 3A As shown, for the process of forming the second gate line slot 122', viewed from the direction perpendicular to the substrate 111', the width in the y-direction of the ends of each second gate line slot portion 122-1' and 122-2' near the discontinuity region 123' needs to gradually decrease to avoid damaging the adjacent channel structure (e.g., 131') or creating a dummy channel structure (e.g., 132') due to excessively large end dimensions of the second gate line slot portions 122-1' and 122-2'. However, due to the morphological characteristics of the ends of the second gate line slot portions 122-1' and 122-2' described above, sharp corners may be generated on the sidewalls of the second gate line slot portions 122-1' and 122-2' near the discontinuity region 123', for example, Figure 3A The sharp corner 118' extending into the stacked structure 112' between the gate sacrificial layers 114a' and 114b', connects adjacent gate sacrificial layers 114a' and 114b'. Similarly, as shown... Figure 3B As shown, via the second grid line slot portions 122-1' and 122-2', Figure 3A During the process of replacing the multiple gate sacrificial layers (e.g., 114a' and 114b') in the illustrated stacked structure 112' with conductive layers (e.g., 115a' and 115b'), conductive material 119' may remain in... Figure 3AWithin the pointed corner 118' shown, adjacent conductive layers 115a' and 115b' are shorted and leak current through conductive material 119'.

[0046] Figure 4 This is a flowchart of a three-dimensional memory fabrication method 1000 according to an embodiment of this application, which improves the above-described process. Figure 4 As shown, the three-dimensional memory fabrication method 1000 includes steps S110 to S130.

[0047] S110, forming an initial stacked structure on the substrate;

[0048] S120, forming multiple initial isolation sections in the initial stacked structure;

[0049] S130, forming multiple gate line slot structures that penetrate the initial stacked structure, and transforming multiple initial isolation portions into multiple isolation portions, such that the multiple isolation portions pass through a portion of the initial stacked structure near the substrate, and respectively cover at least a portion of each gate line slot structure.

[0050] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps may be performed simultaneously or in a manner different from [the steps described]. Figure 4 The execution is performed in the order shown.

[0051] Figures 5A to 5H This is a cross-sectional schematic diagram of a method 1000 for fabricating a three-dimensional memory according to an embodiment of this application. Figures 6A to 6D This is a top view schematic diagram of a method 1000 for fabricating a three-dimensional memory according to an embodiment of this application. The following is in conjunction with... Figures 5A to 6D The steps S110 to S130 described above are further described.

[0052] S110 forms an initial stacked structure on the substrate.

[0053] In step S110, as Figure 5A As shown, substrate 111 may include silicon (Si), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), III-V compound semiconductors, and any other suitable semiconductor materials. Exemplarily, substrate 111 may be formed thereon of, such as an initial stacked structure 112, a channel structure 131 (see reference 112), etc. Figure 5EThe substrate 111 can be removed in a subsequent process, and a semiconductor layer (not shown) can be reformed in the general space of the substrate 111, so that the final three-dimensional memory does not include the substrate 111. Optionally, the material of the semiconductor layer includes, but is not limited to, polysilicon.

[0054] In some embodiments, a first initial stacked structure 1121 may be formed on substrate 111 first to provide a fabrication basis for forming a plurality of initial isolation portions (e.g., 141 and 142) in step S120, which will be described below. For example, the first initial stacked structure 1121 may include a plurality of dielectric layers (e.g., first dielectric layer 1131) and a plurality of gate sacrificial layers (e.g., first gate sacrificial layer 1141) alternately stacked along a direction perpendicular to substrate 111. The method of forming the first initial stacked structure 1121 may include thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Exemplarily, the first dielectric layer 1131 and the first gate sacrificial layer 1141 may be made of materials with different etch selectivity ratios under the same etch conditions. For example, the first dielectric layer 1131 may be made of silicon oxide, and the first gate sacrificial layer 1141 may be made of silicon nitride. The first gate sacrificial layer 1141 in the first initial stacked structure 1121 can be replaced by the first conductive layer (e.g.) in a subsequent process. Figure 5G The 1151a and 1151b shown are replaced and used as the gate of the bottom selection transistor.

[0055] It should be noted that, Figure 5A The number of pairs of first dielectric layer 1131 and first gate sacrificial layer 1141 in the first initial stacked structure 1121 shown is merely exemplary. The first initial stacked structure 1121 may include, for example, 1, 2, 4, 5...n pairs of first dielectric layer 1131 and first gate sacrificial layer 1141. The first gate sacrificial layer (e.g., 1141) in the first initial stacked structure 1121 is replaced by the first conductive layer (e.g., ...). Figure 5G The 1151a and 1151b shown can be used, for example, as gates of bottom-select transistors, so the number of first gate sacrificial layers 1141 in the first initial stacked structure 1121 can correspond to the number of bottom-select transistors.

[0056] S120, multiple initial isolation sections are formed in the initial stacked structure.

[0057] Figures 5B to 5E as well as Figures 6A to 6B An example of a process embodying step S120 is shown, wherein, Figure 5B yes Figure 6A The diagram shown is a cross-sectional view of the three-dimensional memory 100 taken along section line III-III'. Figure 5E yes Figure 6B The diagram shows a cross-sectional view of the three-dimensional memory 100 taken along section line III-III'.

[0058] In some implementations, such as Figure 5B and 6A As shown, a first initial isolation portion 141 may be formed in a first initial stacked structure 1121. Exemplarily, an opening penetrating the first initial stacked structure 1121 may be formed in a predetermined area using photolithography and etching processes (e.g., dry etching or wet etching). Further, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to fill the opening with a dielectric material, such as silicon oxide, to form the first initial isolation portion 141. Exemplarily, in the y-direction, the size (width) of the first initial isolation portion 141 is larger than the first gate gap 121 to be formed (see reference). Figure 6C The size (width) of ).

[0059] In some embodiments, a second initial isolation portion 142 penetrating the first initial stacked structure 1121 may be formed in a predetermined region using a process similar to that used to form the first initial isolation portion 141. Optionally, the second initial isolation portion 142 may be made of the same material as the first initial isolation portion 141, such as silicon oxide.

[0060] In some embodiments, a process similar to that used to form the first initial isolation portion 141 can be employed to form a bottom selection gate cutout structure 151 penetrating the first initial stacked structure 1121 within a predetermined region. For example, the bottom selection gate cutout structure 151 may extend along the x-direction (see reference). Figure 6A Optionally, the bottom selected gate cutout structure 151 may be made of the same material as the first initial isolation portion 141 and / or the second initial isolation portion 142, such as silicon oxide.

[0061] In some embodiments, the first initial isolation portion 141, the second initial isolation portion 142, and the bottom selection gate notch structure 151 can be formed in the same photolithography and etching process using mask design. Therefore, the process methods for forming the first initial isolation portion 141 and / or the second initial isolation portion 142 are well compatible with the process methods for forming the bottom selection gate notch structure 151, which helps reduce the process complexity of forming the first initial isolation portion 141 and / or the second initial isolation portion 142. Optionally, the first initial isolation portion 141, the second initial isolation portion 142, and the bottom selection gate notch structure 151 can also be formed stepwise in the first initial stacked structure 1121; this application does not specifically limit this.

[0062] It should be noted that, as Figure 6AAs shown, the "predetermined area" formed by the first initial isolation portion 141, the second initial isolation portion 142, and the bottom selected gate cutout structure 151, along with the first gate line slot structure 124 and the second gate line slot structure 125 formed in subsequent processes (see reference). Figure 6D The predetermined areas where the first initial isolation section 141, the second initial isolation section 142, and the bottom selection gate cutout structure 151 are located will be described in detail below.

[0063] In one example of step S120, such as Figure 5C As shown, a first portion 1122-1 of the second initial stacked structure 1122 may be formed on the first initial stacked structure 1121, covering, for example, the end face of the first initial isolation portion 141, the second initial isolation portion 142, and / or the bottom select gate notch structure 151, as well as the surface of the first initial stacked structure 1121. Then, a first channel hole 133-1 extending through the first portion 1122-1 of the second initial stacked structure and the first initial stacked structure 1121 to, for example, the substrate 111 may be formed using photolithography and etching processes (e.g., dry or wet etching processes). Optionally, a first sacrificial layer (not shown) may be formed within the first channel hole 133-1 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Next, as... Figure 5D As shown, a second portion 1122-2 of the second initial stacked structure 1122 is formed on a first portion 1122-1 of the second initial stacked structure 1122 to cover the surface of the first portion 1122-1 of the second initial stacked structure 1122 and, for example, a first sacrificial layer within a first channel hole 133-1. Further, a second channel hole 133-2, penetrating the second portion 1122-2 of the second initial stacked structure 1122 and at least partially aligned with the first channel hole 133-1, can be formed, for example, using photolithography and etching processes (e.g., dry or wet etching processes). Optionally, the first sacrificial layer within the first channel hole 133-1 can be removed using, for example, a dry or wet etching process, thereby forming a first channel hole 133-1 and a second channel hole 133-2 penetrating the first initial stacked structure 1121 and the second initial stacked structure 1122 and communicating with each other; for example, both can be collectively referred to as "channel hole 133" and used in the following description.

[0064] In some embodiments, similar to the first initial stacked structure 1121, the second initial stacked structure 1122 may include a plurality of dielectric layers (e.g., a second dielectric layer 1132) and a plurality of gate sacrificial layers (e.g., a second gate sacrificial layer 1142) alternately stacked in a direction perpendicular to the substrate 111. Exemplarily, the formation process and material selection of the second dielectric layer 1132 and the second gate sacrificial layer 1142 in the second initial stacked structure 1122 may be the same as those of the first dielectric layer 1131 and the first gate sacrificial layer 1141 in the first initial stacked structure 1121, and will not be repeated here. Optionally, the second gate sacrificial layer 1142 in the second initial stacked structure 1122 may be replaced by a second conductive layer (e.g., ...) in a subsequent process. Figure 5G The 1152 shown is replaced and used as the gate of the memory cell.

[0065] It should be noted that the method of forming the second initial stacked structure 1122 and the channel hole 133 described above is only exemplary, and the method of forming the second initial stacked structure 1122 and the channel hole 133 is not limited thereto.

[0066] In some embodiments, the first initial stacked structure 1121 and the second initial stacked structure 1122 formed after the above-described process can be divided into a first region A and a second region B along the x-direction in a plane parallel to the substrate 111, and are respectively used to form, for example, a channel structure 131 and a dummy channel structure 132 (see reference). Figure 6B The dummy channel hole (not shown) can be formed using the same or similar process as that used to form the channel hole 133, for example, simultaneously.

[0067] It is worth noting that, such as Figure 6A As shown, the first initial isolation section 141 can be located within the first region A and the second region B. In other words, the first initial isolation section 141 can span the first region A and the second region B. For example, the boundary (dashed line) between the first region A and the second region B, within a predetermined area along the negative x-direction and the positive x-direction respectively, can be called the boundary region, and the first initial isolation section 141 can be located within the boundary region.

[0068] In some implementations, such as Figure 5E and 6BAs shown, the channel holes 133 formed using the above-described process can form, for example, a plurality of channel structures (e.g., 131) arranged in an alternating pattern within the first region A of the initial laminated structure 112 at a first distribution density. Similarly, dummy channel holes formed using the above-described process can form, for example, a plurality of dummy channel structures (e.g., 132) arranged in an alternating pattern within the second region B of the initial laminated structure 112 at a second distribution density, for example, less than the first distribution density. In other words, in one example, from the first region A to the second region B, the distribution density of the plurality of channel structures (e.g., 131) to the plurality of dummy channel structures (e.g., 132) gradually decreases, thereby causing the stress distribution of the initial laminated structure 112 to be uneven near or within the boundary between the first region A and the second region B.

[0069] In some embodiments, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used in the trench vias 133 (see reference). Figure 5D A functional layer 1311, consisting of a charge blocking layer, a charge trapping layer, and a tunneling layer (not shown), and a channel layer 1312 are sequentially formed within the channel structure 131. The materials of the charge blocking layer, charge trapping layer, and tunneling layer may sequentially include silicon oxide, silicon nitride, and silicon oxide, thereby forming the functional layer 1311 with an ONO structure. The material of the channel layer 1312 may include semiconductor materials such as silicon (e.g., amorphous silicon, polycrystalline silicon, monocrystalline silicon). Optionally, a dielectric material, such as silicon oxide, may be filled inside the channel structure 131.

[0070] In some embodiments, the channel structure 131 may further include a channel plug (not shown) located at the end remote from the substrate 111. The channel plug may be fabricated using the same semiconductor material as the channel layer 1312 and is in contact with the channel layer 1312. The channel plug may, for example, serve as the drain of the channel structure 131. Optionally, any known process method may be used to electrically connect the channel layer 1312 to the substrate 111. For example, deep hole etching (SONO Etch) process, SWNN (Side Wall N-poly / N-Sub) process, or deep hole-less etching (SONO Less) process, etc., are not specifically limited in this application.

[0071] In some embodiments, the functional layer 1311 and the channel layer 1312 in the channel structure 131, along with the portions corresponding to each second gate sacrifice 1142 (i.e., the replaced second conductive layer 1152) in the initial stacked structure 112 and a portion of the second conductive layer 1152, together constitute a memory cell. A portion of the second conductive layer 1152 may correspond to the gate of the memory cell. For example, multiple memory cells arranged along the extension direction of the channel structure 131 are connected in series in a direction perpendicular to the substrate 111 and share the channel layer 1312. Under voltage control of the second conductive layer 1152, the memory cell can cause charge carriers in the channel layer 1312 to enter the charge trapping layer in the functional layer 1311, or cause charge carriers in the charge trapping layer of the functional layer 1311 to retreat back to the channel layer 1312, thereby putting the memory cell into a programming state or an erasing state. Optionally, the multiple memory cells connected in series in a direction perpendicular to the substrate 111 may have selection transistors at both ends, for example, for controlling the on or off of the multiple memory cells connected in series. For example, the selection transistor may be referred to as a top selection transistor or a bottom selection transistor depending on its location. Optionally, the bottom selection transistor may be disposed close to the substrate 111, and the number of bottom selection transistors may be at least one, such as four, without specific limitation in this application.

[0072] In some embodiments, multiple dummy channel structures (e.g., 132) penetrate the initial stacked structure 112 within the second region B. The dummy channel structures 132 may have a similar outer contour shape and forming process to the channel structure 131, and may be used, for example, to provide mechanical support and / or load balancing. Optionally, the dummy channel structures 132 may be filled with at least one insulating material, such as silicon oxide. It is worth noting that, although... Figure 6B It is shown that on a plane parallel to the substrate 111, the critical dimension (e.g., diameter) of the dummy channel structure 132 is larger than the critical dimension (e.g., diameter) of the channel structure 131. However, the critical dimension of the dummy channel structure 132 may also be smaller than or equal to the critical dimension of the channel structure 131. This application does not specifically limit this.

[0073] S130, forming multiple gate wire gap structures that penetrate the initial stacked structure, and transforming multiple initial isolation sections into... Multiple isolation sections are provided, such that multiple isolation sections extend through a portion of the initial stacked structure near the substrate and respectively cover each gate. At least a portion of the line slot structure.

[0074] Figures 5F to 5H as well as Figures 6C to 6D An example of step S130 is shown, wherein, Figure 5F yes Figure 6C The diagram shown is a cross-sectional view of the three-dimensional memory 100 taken along section line III-III'. Figure 5H yes Figure 6DThe diagram shows a cross-sectional view of the three-dimensional memory 100 taken along section line III-III'. It should be noted that the positions of the sharp corners 116 and 117 are shown for clarity. Figure 6C and Figure 6D A top view of the three-dimensional memory 100 at the horizontal plane where the sharp corners 116 and 117 are located is shown. It will be understood that at other horizontal planes of the three-dimensional memory 100 where there are no sharp corners (e.g., at the horizontal plane away from the substrate 111), the outer contour of the first gate line slot 121 or the second gate line slot 122 may not have sharp corners when viewed from the top view.

[0075] In one example of step S130, such as Figure 5F and 6C As shown, a first gate line slot 121 penetrating the initial stacked structure 112 can be formed, for example, using photolithography and etching processes (e.g., dry and wet etching processes). The first gate line slot 121 can extend continuously in the x-direction within the first region A and the second region B. Exemplarily, the first gate line slot 121 can penetrate the first initial isolation portion 141 in the boundary region of the first region A and the second region B, such that the first initial isolation portion 141 is divided into a first isolation portion 143 comprising two parts 143-1 and 143-2, the two parts 143-1 and 143-2 being located between the two outer walls of the first gate line slot 121 and the first initial stacked structure 1121, respectively.

[0076] In some embodiments, when the stress distribution is uneven near or within the boundary between the first region A and the second region B of the initial stacked structure 112, the etching material is affected by the stress of the initial stacked structure 112 during the etching process to form the first gate line gap 121, causing the sidewalls of the first gate line gap 121 to develop sharp corners similar to those of a rat bite. For example, a sharp corner 116 extending between the first gate sacrificial layers 1141a and 1141b and into the first isolation portions 143-1 and 143-2. ​​Since the first isolation portion 143 covers both sides of the first gate line gap 121, the sharp corner 116 does not extend into, for example, the first initial stacked structure 1121, but into the first isolation portion 143, thus preventing communication between adjacent first gate sacrificial layers (e.g., 1141a and 1141b).

[0077] In some embodiments, a second gate line slot 122 extending through the initial stacked structure 112 may be formed, for example, using a process similar to that used to form the first gate line slot 121. The second gate line slot 122 may extend intermittently in the x-direction within the first region A and / or the second region B. The second gate line slot 122 may be broken in the x-direction to form a discontinuous region 123, and to form second gate line slot portions 122-1 and 122-2 that are separated from each other. Exemplarily, the second gate line slot portions 122-1 and 122-2 may extend through the second initial isolation portion 142, such that the second initial isolation portion 142 transforms into a second isolation portion 144. For example, in the x-direction, the second isolation portion 144 may have two opposing surfaces that are in contact with the discontinuities (the discontinuities near the substrate 111) of the second gate line slot portions 122-1 and 122-2, respectively, such that at least a portion of the second isolation portion 144 fills the space between the second gate line slot portions 122-1 and 122-2 within the discontinuity region 123. In other words, the second isolation portion 144 covers the discontinuities (the portions near the substrate 111) of the second gate line slot portions 122-1 and 122-2.

[0078] It should be noted that the location of the discontinuity region 123 at the boundary between the first region A and the second region B is merely exemplary; the discontinuity region 123 may also be located within the first region A or the second region B. In other words, the second grid line gap 122 may be interrupted within the first region A, the second region B, or the boundary region between the first region A and the second region B. Therefore, the second initial isolation portion 142 may penetrate the first initial stacked structure 1121 within the first region A, the second region B, or the boundary region between the first region A and the second region B.

[0079] In some implementations, such as Figure 6C As shown, the width of the end of the second gate line slot portion 122-1 or 122-2 near the discontinuity region 123 in the y-direction can gradually decrease. During the process of etching the initial stacked structure 112 to form the second gate line slot 122, sharp corners similar to mouse bites may be generated on the sidewalls of the second gate line slot portion 122-1 or 122-2 near the discontinuity region 123. For example, a sharp corner 118 between the first gate sacrificial layers 1141a and 1141b and extending into the second isolation portion 144. Since the second isolation portion 144 covers the discontinuity of the second gate line slot portions 122-1 and 122-2, the sharp corner 118 does not extend into, for example, the first initial stacked structure 1121, but extends into the second isolation portion 144, thus preventing communication between adjacent first gate sacrificial layers (e.g., 1141a and 1141b).

[0080] In some embodiments, a wet etching process may be used, for example, to remove multiple first gate sacrificial layers (e.g., 1141a) and multiple second gate sacrificial layers (e.g., 1142) in the initial stacked structure 112 via the first gate line gap 121 and / or the second gate line gap 122 to form a sacrificial gap (not shown). Further, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to fill the sacrificial gap with a conductive material, such as metallic tungsten, to form multiple conductive layers (e.g., first conductive layers 1151a and 1151b, second conductive layer 1152), such as... Figure 5G As shown. After the above process, the initial laminated structure 121 (reference) Figure 5F It is transformed into a layered structure 161.

[0081] In some implementations, such as Figure 5G As shown, during the process of filling conductive material, although conductive materials 117 and 119 may remain at sharp corners 116 and 118 (see reference). Figure 5F However, due to the electrical isolation effect of the first isolation portion 143 and / or the second isolation portion 144, the conductive materials 117 and 119 remaining in the sharp corners 116 and 118 are surrounded by the first isolation portion 143 and the second isolation portion 144 respectively, so that a conductive path will not be formed between adjacent first conductive layers (e.g., 1151a and 1151b) through the conductive materials 117 and 119 in the sharp corners 116 and 118, thereby preventing short circuit leakage.

[0082] In some implementations, such as Figure 5H and 6D As shown, an insulating layer 126 can be formed on the sidewall of the first gate line slot 121 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the insulating layer 126 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. Exemplarily, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form the insulating layer 126 on the first gate line slot 121 (see reference 121). Figure 5GThe first gate gap structure 124 is formed by filling at least one conductive material 127, such as doped polysilicon, copper, aluminum, tungsten, or any combination thereof. Exemplarily, the second gate gap structure 125 can be formed simultaneously using the same process. In one example, the first gate gap structure 124 and / or the second gate gap structure 125 can serve as a common source lead-out structure for multiple channel structures (e.g., 131). For example, by contacting the conductive material 127 in the first gate gap structure 124 with, for example, a substrate 111, it can be electrically connected to the channel layer 1312 of the multiple channel structures (e.g., 131). In other examples, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill at least one insulating material in the first gate gap 121 and / or the second gate gap 122 without filling it with conductive material, such that the common source of the multiple channel structures (e.g., 131) is led out through the reformed semiconductor layer 110.

[0083] According to the three-dimensional memory fabrication method 1000 provided in this application, by forming an isolation portion that covers at least a portion of the gate line gap structure, the sharp corners generated during the gate line gap formation process can extend into the isolation portion, thereby reducing the risk of leakage paths between the conductive material remaining in the sharp corners and the adjacent conductive layers in the stacked structure in subsequent processes, and thus improving the electrical performance of the three-dimensional memory.

[0084] This application also provides a three-dimensional memory 100. Figure 6D This is a top view schematic diagram of a three-dimensional memory 100 according to an embodiment of this application. Figure 5H It is based on Figure 6D The diagram shows a cross-sectional view of the three-dimensional memory 100 taken along section line III-III'. Details identical to those described above will not be repeated here.

[0085] like Figure 5H and Figure 6D As shown, the three-dimensional memory 100 includes: a semiconductor layer 110, a stacked structure 161, a plurality of gate line slot structures (e.g., a first gate line slot structure 124 and a second gate line slot structure 125), and a plurality of isolation portions (e.g., a first isolation portion 144 and a second isolation portion 144). The plurality of gate line slot structures (e.g., 124 and 125) penetrate the stacked structure 161, and the plurality of isolation portions (e.g., 143 and 144) penetrate a portion of the stacked structure 161 near the semiconductor layer 110, and respectively cover at least a portion of each gate line slot structure (e.g., 124 and 125).

[0086] In some embodiments, the semiconductor layer 110 may include, for example, polysilicon, and the stacked structure 161 is located on the semiconductor layer 110. Exemplarily, the stacked structure 161 includes alternatingly stacked plurality of dielectric layers (e.g., a first dielectric layer 1131) and plurality of conductive layers (e.g., first conductive layers 1151a and 1151b). The plurality of dielectric layers (e.g., 1131) may be made of silicon oxide, and the plurality of conductive layers (e.g., 1151a) may be made of tungsten metal. The number of stacked dielectric and conductive layers in the stacked structure 161 may be 8, 32, 64, 128, etc. The more stacked layers the stacked structure 161 has, the higher the integration density and the more memory cells it forms. The number of stacked layers and the stacking height of the stacked structure 161 can be designed according to actual storage requirements, and this application does not specifically limit this.

[0087] In some implementations, such as Figure 6D As shown, in the x-direction, the stacked structure 161 can be divided into a first region A, for example, for forming a plurality of channel structures (e.g., 131), and a second region B, for example, for forming a plurality of dummy channel structures 132. Exemplarily, the plurality of channel structures (e.g., 131) are formed in the first region A with a first distribution density (alternating), and the plurality of dummy channel structures (e.g., 132) are formed in the second region B with a second distribution density, for example, less than the first distribution density.

[0088] In some implementations, such as Figure 5H and Figure 6D As shown, the first gate line slot structure 124 penetrates the stacked structure 161 and extends continuously along the x-direction within the first region A and the second region B to divide the three-dimensional memory 100 into memory blocks. A first isolation portion 143 penetrates a portion of the stacked structure 161 near the semiconductor layer 110 within the first region A and the second region B, and covers a portion of the first gate line slot structure 124 located within the boundary region, thereby forming an insulating isolation between the portion of the first gate line slot structure 124 located within the boundary region and the portion of the stacked structure 161 near the semiconductor layer 110. Exemplarily, the first isolation portion 143 may include two portions 143-1 and 143-2, respectively located on both sides of the portion of the first gate line slot structure 124 located within the boundary region, thereby forming an insulating isolation between the first gate line slot structure 124 and the portions of the stacked structure 161 on both sides near the semiconductor layer 110. Optionally, the first isolation portion 143 may be made of a dielectric material such as silicon oxide.

[0089] In some embodiments, during the process of forming the first gate gap structure 124, the sharp corners filled with conductive material 117 extending toward the first isolation portion 143-1 and / or 143-2 are surrounded in the first isolation portion 143-1 and / or 143-2, which can prevent the formation of leakage paths between the conductive material 117 in the sharp corners and the conductive layers (e.g., 1151a and 1151b) in the stacked structure 161, thereby improving the electrical performance of the three-dimensional memory.

[0090] In some embodiments, the critical dimension of the first gate gap structure 124 gradually decreases along the direction toward the semiconductor layer 110 in a plane parallel to the semiconductor layer 110. For example, the width of the first gate gap structure 124 in the y-direction gradually decreases along the direction toward the semiconductor layer 110. In other words, in the y-direction, the width w1 of the first gate gap structure 124 away from the semiconductor layer 110 is greater than the width w2 of the first gate gap structure 124 near the semiconductor layer 110. In this case, the sharp corners filled with conductive material 117 as described above are more easily formed in the portion of the stacked structure 161 near the semiconductor layer 110, and by providing the first isolation portion 143 in the portion of the stacked structure 161 near the semiconductor layer 110, the risk of leakage paths forming between adjacent conductive layers (e.g., 1151a and 1151b) in the stacked structure 161 can be further reduced.

[0091] In some embodiments, the first isolation portion 143 may extend in the x-direction. In the x-direction, the length of the first isolation portion 143 may be less than the length of the first gate line slot structure 124. For example, the length of the first isolation portion 143 in the x-direction may be 400 nm to 500 nm. Optionally, the first isolation portion 143 may be symmetrically distributed within the first region A and the second region B. For example, the first isolation portion 143 may be symmetrically distributed relative to the boundary between the first region A and the second region B. It should be noted that this application does not specifically limit the extension length of the first isolation portion 143 in the x-direction; for example, the length of the first isolation portion 143 may also be equal to the length of the first gate line slot structure 124. It is understandable that the sharp corners filled with conductive material 117 are formed due to the uneven stress distribution in the first region A and the second region B. The fact that the length of the first isolation portion 143 is smaller than that of the first gate gap structure 124 can reduce the space occupied by the first isolation portion 143 while avoiding the formation of leakage paths between adjacent conductive layers (e.g., 1151a and 1151b) in the stacked structure 161.

[0092] In some implementations, such as Figure 5H and Figure 6DAs shown, the second gate slot structure 125 extends intermittently through the stacked structure 161 and along the x-direction within the first region A and the second region B to further divide the memory block into memory blocks. The second gate slot structure 125 may be interrupted within a predetermined region of the first region A, the second region B, or the boundary between the first region A and the second region B, such that the second gate slot structure 125 forms a plurality of second gate slot structure portions (e.g., 125-1 and 125-2) spaced apart from each other in the x-direction. There may be a discontinuity region 123 between adjacent second gate slot structure portions (e.g., 125-1 and 125-2). For example, in the x-direction, the second isolation portion 144 may have two opposing surfaces that contact the discontinuities (near a portion of the semiconductor layer 110) of the second gate slot structure portions 125-1 and 125-2, such that at least a portion of the second isolation portion 144 fills the space between the second gate slot structure portions 125-1 and 125-2 within the discontinuity region 123. In other words, the second isolation portion 144 covers the discontinuities (near the semiconductor layer 110) of the second gate slot structure portions 125-1 and 125-2, thereby forming an insulating barrier between the second gate slot structure portions 125-1 and 125-2 and the stacked structure 161. Optionally, the second isolation portion 144 may be made of a dielectric material such as silicon oxide.

[0093] In some embodiments, during the process of forming the second gate gap structure 125, the sharp corners filled with conductive material 119 extending toward the second isolation portion 144 are surrounded in the second isolation portion 144, which can prevent the conductive material 119 in the sharp corners from forming a leakage path with the conductive layers (e.g., 1151a and 1151b) in the stacked structure 161, thereby improving the electrical performance of the three-dimensional memory.

[0094] In some embodiments, the critical dimensions of the second gate gap structure 125 gradually decrease along the direction toward the semiconductor layer 110 in a plane parallel to the semiconductor layer 110. For example, in the y-direction, the critical dimensions of the respective second gap structure portions 125-1 and 125-2 near the discontinuity region 123 gradually decrease along the direction toward the semiconductor layer 110. In this case, the sharp corners filled with conductive material 119 as described above are more easily formed in the portion of the stacked structure 161 near the semiconductor layer 110, and by providing the second isolation portion 144 in the portion of the stacked structure 161 near the semiconductor layer 110, the risk of leakage paths forming between adjacent conductive layers (e.g., 1151a and 1151b) in the stacked structure 161 can be effectively reduced.

[0095] In some embodiments, the discontinuity region 123 may be located within the first region A, the second region B, or the boundary region between the first region A and the second region B. When the discontinuity region 123 is located within the boundary region between the first region A and the second region B, the respective second gate slot structure portions 125-1 and 125-2 may develop sharp corners filled with conductive material on both sides in the y-direction due to uneven stress in the first region A and the second region B. The second isolation portion 144 extends in the x-direction within the first region A and the second region B, and the length of the second isolation portion 144 in the x-direction is greater than the length of the discontinuity region 123 in the x-direction, such that the surface of the second isolation portion 144 in the x-direction can also contact the sidewalls of the respective second gate slot structure portions 125-1 and 125-2. In other words, the second isolation portion 144 covers a portion of the second gate line slot structure 125 located in the boundary region in the y direction, thereby surrounding the sharp corners extending in the y direction formed during the process of forming the second gate line slot structure portions 125-1 / 125-2 within the second isolation portion 144, which can further reduce the risk of leakage paths forming between adjacent conductive layers (e.g., 1151a and 1151b) in the stacked structure 161.

[0096] According to the three-dimensional memory 100 provided in this application, by providing an isolation portion that covers at least a portion of the gate wire gap structure, the sharp corners generated during the process of forming the gate wire gap structure can extend into the isolation portion, thereby reducing the risk of leakage paths between the conductive material remaining in the sharp corners and the adjacent conductive layers in the stacked structure in subsequent processes, and thus improving the electrical performance of the three-dimensional memory.

[0097] Figures 7A to 7C This is a schematic diagram of the structure of a three-dimensional memory 200 according to another embodiment of this application. Figure 7A This is a top view of the three-dimensional memory 200. Figure 7B This is a schematic diagram of a cross-section taken along section line Ⅳ-Ⅳ'. Figure 7C This is a cross-sectional view taken along section line V-V'. The internal structure of the three-dimensional memory 200 is the same as that of the three-dimensional memory 100 described in detail above, and will not be repeated here. This embodiment is intended to illustrate that the sharp corner 217 can extend in one side of the first isolation portion 243 (see reference). Figure 7B Furthermore, it does not extend into the second isolation section 244 (see reference). Figure 7CIn other words, during the manufacturing process of the first gate line slot structure 224 and the second gate line slot structure 225, the appearance of sharp corners on the outer periphery of the first gate line slot structure 224 and / or the second gate line slot structure 225 is random. However, setting the first isolation portion 243 alone, setting the second isolation portion 244 alone, or setting the first isolation portion 243 and the second isolation portion 244 simultaneously all reduce the risk of forming leakage paths between adjacent conductive layers, thereby improving the electrical performance of the three-dimensional memory 200.

[0098] Another aspect of this application provides a memory system 12. Figure 8 A block diagram of a system 10 having a memory system 12 according to an embodiment of this application is shown.

[0099] System 10 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 12 located therein). Figure 8 As shown, system 10 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memories 14.

[0100] The three-dimensional memory 14 may be any of the three-dimensional memories described in any of the embodiments disclosed herein, for example, Figure 6D or Figure 7A The illustrated three-dimensional memory 100 or 200. In some embodiments, each three-dimensional memory 14 includes an array of memory cells and peripheral circuitry for the memory cell array. Exemplarily, the memory cell array and the peripheral circuitry may be stacked on top of each other in different planes.

[0101] According to some embodiments, controller 16 is coupled to 3D memory 14 and host 18 and is configured to control 3D memory 14. Controller 16 can manage data stored in 3D memory 14 and communicate with host 18. In some embodiments, controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 16 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as data storage devices in mobile devices such as smartphones, tablets, laptops, etc. Controller 16 can be configured to control the operation of 3D memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The controller 16 may communicate with external devices (e.g., host 18) according to a specific communication protocol. For example, the controller 16 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, peripheral component interconnection (PCI), high-speed PCI (PCI-express, PCI-E), advanced technology attachment (ATA), serial ATA, parallel ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), Firewire, etc.

[0102] The controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 9A In one example shown, the controller 16 and a single 3D memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host computer (e.g., Figure 8 The host 18) is coupled to the memory card connector 24. In such a way... Figure 9B In another example shown, the controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 8 The SSD connector 28 is coupled to the host 18. In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0103] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory, comprising: Semiconductor layer; A stacked structure is located on the semiconductor layer, and the stacked structure is divided into a first region and a second region along a first direction parallel to the semiconductor layer; Multiple grid line slot structures penetrate the stacked structure; as well as Multiple isolation sections extend through a portion of the stacked structure near the semiconductor layer and respectively cover at least a portion of each of the gate gap structures; The plurality of gate wire slot structures include at least one first gate wire slot structure that extends continuously along the first direction in the first region and the second region; as well as The plurality of isolation sections include at least one first isolation section in the first region and the second region, each first isolation section covering at least a portion of each first gate wire slot structure.

2. The three-dimensional memory of Claim 1 wherein, In the first direction, the length of the first isolation portion is less than the length of the first gate wire slot structure.

3. The three-dimensional memory of Claim 1 wherein, The first isolation section is symmetrically distributed in the first region and the second region.

4. The three-dimensional memory of Claim 1 wherein, The three-dimensional memory includes multiple channel structures and multiple dummy channel structures. The multiple channel structures are formed in the first region with a first distribution density, and the multiple dummy channel structures are formed in the second region with a second distribution density. The first distribution density and the second distribution density are different.

5. The three-dimensional memory according to claim 1, wherein, The plurality of gate wire slot structures include at least one second gate wire slot structure that extends discontinuously along the first direction in the first region and the second region. as well as The plurality of isolation sections include at least one second isolation section, each second isolation section covering the discontinuity of each second gate wire slot structure.

6. The three-dimensional memory according to claim 5, wherein, In the first direction, the length of the second isolation portion is greater than the length of the discontinuous region of the second gate wire slot structure.

7. The three-dimensional memory according to claim 5, wherein, In a second direction parallel to the semiconductor layer, the critical dimensions of the first gate slot structure and the second gate slot structure gradually decrease along the direction toward the semiconductor layer, and the second direction is perpendicular to the first direction.

8. The three-dimensional memory according to claim 5, wherein, Both the first isolation section and the second isolation section are made of dielectric material.

9. The three-dimensional memory according to claim 5, wherein, The stacked structure includes a first stacked structure and a second stacked structure in sequence along the direction away from the semiconductor layer. The three-dimensional memory also includes a bottom select gate cutout structure, wherein the first isolation portion, the second isolation portion and the bottom select gate cutout structure penetrate through the first stacked structure.

10. A memory system, comprising: At least one three-dimensional memory as described in any one of claims 1 to 9; as well as A controller, electrically connected to at least one of the three-dimensional memories, is configured to control at least one of the three-dimensional memories.

11. A method for fabricating a three-dimensional memory, comprising: An initial stacked structure is formed on the substrate; A plurality of initial isolation portions are formed in the initial stacked structure, wherein the initial stacked structure is divided into a first region and a second region along a first direction parallel to the substrate; Forming a plurality of gate wire slot structures penetrating the initial stacked structure, and transforming the plurality of initial isolation portions into a plurality of isolation portions such that the plurality of isolation portions penetrate a portion of the initial stacked structure near the substrate, and respectively cover at least a portion of each gate wire slot structure, including: At least one first gate line slot structure is formed extending continuously along the first direction in the first region and the second region, and at least one of the plurality of initial isolation portions is transformed into at least one first isolation portion in the first region and the second region, each first isolation portion covering at least a portion of each first gate line slot structure.

12. The preparation method according to claim 11, wherein, Forming multiple gate wire slot structures that penetrate the initial stacked structure, and transforming the multiple initial isolation portions into multiple isolation portions includes: At least one second gate line slot structure is formed in the first region and the second region, extending discontinuously along the first direction, and at least one of the plurality of initial isolation portions is transformed into at least one second isolation portion, each second isolation portion covering the discontinuity of each second gate line slot structure.

13. The preparation method according to claim 12, wherein, The initial stacked structure includes a first initial stacked structure and a second initial stacked structure sequentially along a direction away from the substrate, and a plurality of initial isolation portions are formed in the initial stacked structure, including: A plurality of initial isolation sections are formed that penetrate the first initial stacked structure.

14. The preparation method according to claim 12, wherein, Both the first isolation section and the second isolation section are made of dielectric material.

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