Measuring device and board for measuring clock signal jitter

Abstract

The present invention relates to a measuring device and a board for measuring clock signal jitter, wherein the computing device of the present invention is included in an integrated circuit device, and the integrated circuit device includes a universal interconnection interface and other processing devices. The computing device interacts with other processing devices to jointly complete the computing operation specified by the user. The integrated circuit device may also include a storage device, which is respectively connected to the computing device and the other processing devices, and is used for data storage of the computing device and the other processing devices.

Description

Technical Field

[0001] The present invention generally relates to the field of chip process testing and more specifically to a measuring device and a board for measuring clock signal jitter. Background Art

[0002] With the improvement of technology, the operating frequency of a large number of integrated circuits is set at hundreds of megahertz or even thousands of megahertz. At such a high operating frequency, the requirements for clock signals are getting higher and higher, that is, the clock signal must be close to the ideal value. Figure 1A An ideal clock signal is shown.

[0003] Due to the error of chip process, the rising edge and falling edge of the clock signal are offset. Figure 1B As described above, the rising edge of the clock signal is offset 101, and the falling edge is also offset 102. Such offset is called clock jitter. Clock jitter is an important indicator of clock signal design and can be defined as the random variation of the clock signal relative to the ideal clock over a period of time.

[0004] The causes of clock jitter come from mechanical noise of crystal oscillator, device resonance, signal crosstalk, voltage fluctuation, etc. If the clock jitter is too large, it may cause data transmission or calculation errors. For high-speed circuits, clock jitter measurement devices can test and verify the timing characteristics of the actual operation of the chip, providing an important reference for chip design and process research.

[0005] There are currently two methods for measuring clock jitter. The first is to perform off-chip measurements using a high-precision oscilloscope or similar equipment, and the second is to perform measurements using an on-chip measurement device, such as the vernier delay chain method, the vernier oscillator method, etc. The vernier delay chain method is one of the most commonly used on-chip jitter measurement techniques. The circuit consists of two links containing different delay units, so that the delay times of the two signals are different. The clock signal to be measured is called the data signal, and the clock signal used as the reference value is called the reference signal. First, the reference signal is set to lead the data signal by one cycle. After multiple levels of delay, the clock signal will lag behind the data signal, and the trigger will start counting. The cumulative distribution function is obtained through statistics, and then the normal distribution is obtained through differential processing.

[0006] However, the delay chain circuit requires an ideal reference clock as a benchmark, and the delay unit needs to generate a fixed delay time, which requires very precise control in the physical implementation of the chip. Secondly, the resolution is not ideal and it is possible that no data can be collected.

[0007] Therefore, an efficient clock signal jitter measurement solution is urgently needed. Summary of the invention

[0008] In order to at least partially solve the technical problem mentioned in the background technology, the solution of the present invention provides a measuring device and a board for measuring the jitter of a clock signal.

[0009] In one aspect, the present invention discloses a measuring device for measuring jitter of a clock signal, comprising a reference circuit, a data circuit and a measuring counter. The reference circuit responds to the clock signal to generate a reference signal; the data circuit responds to the clock signal to generate a data signal, wherein the clock period of the data signal differs from that of the reference signal by at least one integer period; and the measuring counter is used to record the number of jitters of the data signal edge being earlier or later than the reference signal edge of the reference signal within a specific time.

[0010] In another aspect, the present invention discloses an integrated circuit device, including the aforementioned measuring device; and discloses a board, including the aforementioned integrated circuit device.

[0011] The present invention can achieve high-resolution technical effects without relying on precise chip physical implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0013] Figure 1A is an ideal clock signal;

[0014] Figure 1B is a clock signal showing jitter;

[0015] Figure 2 is a structural diagram of a board card according to an embodiment of the present invention;

[0016] Figure 3 is a structural diagram showing a combined processing device according to an embodiment of the present invention;

[0017] Figure 4 is a circuit diagram showing a measuring device according to an embodiment of the present invention;

[0018] Figure 5 is a circuit diagram showing a mode selector according to an embodiment of the present invention;

[0019] Fig. 6A is a circuit diagram showing a reference fine-tuning delay unit according to an embodiment of the present invention;

[0020] Figure 6B is a circuit diagram showing another reference fine-tuning delay unit according to an embodiment of the present invention;

[0021] Figure 7 is a schematic diagram showing a width adjustment delay unit according to an embodiment of the present invention;

[0022] Figure 8 1 is a circuit diagram showing a measurement counter according to an embodiment of the present invention;

[0023] Fig. 9 is a flow chart illustrating a calibration mode of an embodiment of the present invention; and

[0024] Fig.10 is a flow chart illustrating a measurement mode of an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0026] It should be understood that the terms "first", "second", "third" and "fourth" etc. in the claims, specifications and drawings of the present invention are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprise" used in the specification and claims of the present invention indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their collections.

[0027] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the claims, the singular forms of "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in the specification of the present invention and the claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0028] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context.

[0029] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] Figure 2A scenario of application of the present invention is shown, which is a server in a cloud computing center, and each server is configured with multiple boards 20. Figure 2 As shown, the board 20 includes a chip 201, which is a system-on-chip (SoC), or system on chip, integrated with one or more combined processing devices, which are artificial intelligence computing units that support various deep learning and machine learning algorithms to meet the intelligent processing needs in complex scenarios in the fields of computer vision, speech, natural language processing, data mining, etc. In particular, deep learning technology is widely used in the field of cloud intelligence. A notable feature of cloud intelligence applications is the large amount of input data, which places high demands on the storage capacity and computing power of the platform. The board 20 is suitable for cloud intelligence applications and has huge off-chip storage, on-chip storage and powerful computing power.

[0031] The chip 201 is connected to an external device 203 via an external interface device 202. The external device 203 is, for example, a server, a computer, a camera, a display, a mouse, a keyboard, a network card, or a wifi interface. The data to be processed can be transmitted from the external device 203 to the chip 201 via the external interface device 202. The calculation result of the chip 201 can be transmitted back to the external device 203 via the external interface device 202. According to different application scenarios, the external interface device 202 can have different interface forms, such as a PCIe interface.

[0032] The board 20 also includes a storage device 204 for storing data, which includes one or more storage units 205. The storage device 204 is connected to the control device 206 and the chip 201 through a bus and transmits data. The control device 206 in the board 20 is configured to regulate the state of the chip 201. To this end, in an application scenario, the control device 206 may include a single-chip microcomputer (Micro Controller Unit, MCU).

[0033] Figure 3 2 is a block diagram showing a combined processing device in chip 201. Figure 3 As shown in , the combined processing device 30 includes a computing device 301 , an interface device 302 , a processing device 303 and a DRAM 304 .

[0034] The computing device 301 is configured to execute user-specified operations, and is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations. It can interact with the processing device 303 through the interface device 302 to jointly complete the user-specified operations.

[0035] The interface device 302 is used to transmit data and control instructions between the computing device 301 and the processing device 303. For example, the computing device 301 can obtain input data from the processing device 303 via the interface device 302 and write it into the storage device on the computing device 301 chip. Further, the computing device 301 can obtain control instructions from the processing device 303 via the interface device 302 and write them into the control cache on the computing device 301 chip. Alternatively or optionally, the interface device 302 can also read data in the storage device of the computing device 301 and transmit it to the processing device 303.

[0036] The processing device 303 is a general processing device that performs basic controls including but not limited to data handling, starting and / or stopping the computing device 301. According to different implementations, the processing device 303 can be a central processing unit (CPU), a graphics processing unit (GPU) or one or more types of processors in other general and / or special processors, which include but are not limited to digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, only with respect to the computing device 301, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing device 301 and the processing device 303 are integrated and considered together, the two are regarded as forming a heterogeneous multi-core structure.

[0037] DRAM 304 is used to store data to be processed, and is a DDR memory, which is usually 16G or larger in size and is used to store data of the computing device 301 and / or the processing device 303 .

[0038] An embodiment of the present invention is a measuring device for measuring clock signal jitter. The measuring device is directly embedded in a system on chip, that is, a chip 201 . Figure 4 4 shows a circuit structure diagram of a measuring device 400 , which includes a mode selector 401 , a reference circuit 402 , a data circuit 403 and a measurement counter 404 .

[0039] The mode selector 401 is used to switch between the calibration mode and the measurement mode according to the clock signal 406 and the enable signal 407. The reference circuit 402 responds to the clock signal 406 to generate the reference signal 408. The data circuit 403 responds to the clock signal 306 to generate the data signal 409, and the clock cycle of the data signal 409 and the reference signal 408 differ by at least one integer cycle. The measurement counter 404 is used to record the number of jitters of the data signal 409 being earlier or later than the reference signal edge of the reference signal 408 within a specific time. The signal edge here includes the rising edge and the falling edge of the signal.

[0040] Figure 5 The circuit diagram of the mode selector 401 is shown. The mode selector 401 includes a D flip-flop 501, an AND gate 502, a multiplexer 503 and a multiplexer 504. The D terminal of the D flip-flop 501 receives an enable signal 407, and the clock terminal receives a clock signal 406. The Q terminal of the D flip-flop 501 is connected to an input terminal of the AND gate 502. The other input terminal of the AND gate 502 receives the clock signal 406. The output terminal of the AND gate 502 is connected to input terminals of the multiplexer 503 and the multiplexer 504. The other input terminal of the multiplexer 503 receives a data oscillation signal 410. The other input terminal of the multiplexer 504 receives a reference oscillation signal 411. The multiplexer 503 outputs a data signal 420 before delay and inputs it to the data circuit 403. The multiplexer 504 outputs a reference signal 419 before delay and inputs it to the reference circuit 402. The multiplexers 503 and 504 control one of the signals at the two input terminals to become an output signal in response to a selection signal 505.

[0041] The reference circuit 402 includes a reference fine-tuning delay unit 412, an inverter 413, and a calibration counter 414. The reference fine-tuning delay unit 412 is used to delay the pre-delay reference signal 419, the inverter 413 is used to make the reference signal 408 oscillate in the calibration mode, and the calibration counter 414 is used to count the number of oscillations of the reference oscillation signal 411.

[0042] There are various circuit structures of the reference fine-tuning delay unit 412 , and two structures are disclosed as examples for illustration.

[0043] A reference fine-tuning delay unit 412 includes multiple delay units connected in series, each delay unit includes a delay step unit and a switch, Fig. 6AThe circuit diagram of a single-stage delay unit is shown. The single-stage delay unit includes a delay step unit 601 and a switch 602. The delay step unit 601 is a buffer that receives the pre-delay reference signal 419. The output of the delay step unit 601 is connected to the input end of the switch 602. The other input end of the switch 602 is also connected to the input end of the delay step unit 601. The delay step unit 601 is used to provide a unit delay time. The switch 602 determines whether the pre-delay reference signal 419 passes through the delay step unit 601 of this stage through the selection signal SEL. The reference fine-tuning delay unit 412 includes multiple stages such as Fig. 6A The delay units shown are connected in series. The switch 602 controls the amount of the pre-delay reference signal 419 flowing through the delay step unit 601 . By controlling the selection signals SEL, the reference fine-tuning delay unit 412 can adjust the overall delay time of the pre-delay reference signal 419 .

[0044] Another reference fine-tuning delay unit 412 also includes a multi-stage delay unit. Figure 6B 6 shows a circuit diagram of a single-stage delay unit, which includes a delay step unit 603, a delay step unit 604 and a switch 605. Fig. 6A The difference between the single-stage delay unit of FIG. 604 and FIG. 605 is that the two input ends of the switch 605 are connected to the delay step unit 603 and the delay step unit 604 respectively. The switch 605 determines whether the reference signal 419 before the delay passes through the delay step unit 603 or the delay step unit 604 by selecting the signal SEL. The delay step unit 603 and the delay step unit 604 have different time delays. The capacitance values ​​of the delay step unit 603 and the delay step unit 604 are adjusted during simulation so that the time delays of the two differ by a specific time, such as 1 picosecond. Such an arrangement does not require very accurate control in the physical implementation of the chip. Even if there are differences in the physical implementation, causing the actual delays of the delay step unit 603 and the delay step unit 604 to change, the delay difference between the two can still be maintained at 1 picosecond.

[0045] In this embodiment, the number of switches of the two reference fine-tuning delay units 412 is 2. N The switch 602 or 605 responds to the N-bit selection signal to control the number of delay step units through which the pre-delay reference signal 419 flows. For example, the reference fine-tuning delay unit 412 is connected in series with 2 6 (=64) single-stage delay units, each delay step unit 601 generates a delay of 1 picosecond, and the reference fine-tuning delay unit 412 can generate a delay of 64 picoseconds at most using a 6-bit selection signal. The delay time of the delay step unit corresponding to each switch 602 or 605 is the resolution of the measuring device 400.

[0046] The data circuit 403 includes a data fine-tuning delay unit 415, a wide-tuning delay unit 416, an inverter 417, and a calibration counter 418. The data fine-tuning delay unit 415 is used to control the data signal edge of the data signal 409 to be slightly earlier than the reference signal edge, so as to facilitate measurement in the measurement mode. Its structure and function are the same as those of the reference fine-tuning delay unit 412; the wide-tuning delay unit 416 is used to control the data signal edge to be at least one integer cycle later than the reference signal edge in the calibration mode. The data signal edge refers to the rising edge or falling edge of the data oscillation signal 410, and the reference signal edge refers to the rising edge or falling edge of the reference oscillation signal 411. The inverter 417 is used to make the data signal 409 oscillate in the calibration mode; the calibration counter 418 is used to count the number of oscillations. The delay time of the delay step unit in the data fine-tuning delay unit 415 is also the resolution of the measurement device 400.

[0047] Figure 7 FIG. 4 is a schematic diagram of a width adjustment delay unit 416, which includes a fixed delay unit 701 and an adjustable delay unit 702. The fixed delay unit 701 is used to provide a fixed delay time for the pre-delay data signal 420. The fixed delay time can be achieved by connecting multiple buffers in series. The adjustable delay unit 702 includes multiple buffers and switches. The switches are used to control the number of buffers through which the pre-delay data signal 420 flows to adjust the delay time. The adjustable delay unit 702 can be used. Fig. 6A or Figure 6B circuit to achieve this, for example, by connecting 2 5 (=32) buffer plus switch units, the adjustable delay unit 702 is controlled by a 5-bit selection signal. In this embodiment, in order to be able to adjust over a wide range, the adjustable delay unit 702 has an adjustment range between 20 picoseconds and 800 picoseconds. The advantage of this design is that, taking the rising edge as an example, when the rising edge of the reference signal 408 deviates far from the rising edge of the data signal 409, the adjustable delay unit 702 can be used to adjust the delay time of the data signal 409, so that the rising edge of the data signal 409 is advanced by hundreds of picoseconds or delayed by hundreds of picoseconds, so that the rising edges of the two signals are closer, thereby obtaining valid data.

[0048] The calibration counters 414 and 418 are 10-bit binary counters with an upper counting limit of 1024 times. Those skilled in the art are familiar with the circuit implementation thereof, so it will not be described in detail.

[0049] The circuit structure of the measurement counter 404 is as follows: Figure 8As shown, it includes a D flip-flop 801 and a counter 802. The reference signal 408 is input to the clock terminal of the D flip-flop 801, and the data signal 409 is input to the D terminal of the D flip-flop 801. The triggering mode of the D flip-flop 801 is edge triggering, that is, it is triggered at the rising edge of the clock terminal signal, that is, if the rising edge of the data signal 409 arrives earlier than the rising edge of the reference signal 408, then when the rising edge of the reference signal 408 touches the clock terminal of the D flip-flop 801, the D terminal of the D flip-flop 801 is already high level, resulting in the Q terminal output being 1; and if the rising edge of the data signal 409 arrives later than the rising edge of the reference signal 408, then when the rising edge of the reference signal 408 touches the clock terminal of the D flip-flop 801, the D terminal of the D flip-flop 801 is still low level, resulting in the Q terminal output being 0. The signal at the Q end is input to the counter 802, and the structure of the counter 802 can be the same as that of the calibration counters 414 and 418, and is used to count the level of the Q end signal, and then obtain the number of times that the data signal 409 is ahead of the reference signal 408 and the number of times that the data signal 409 is behind the reference signal 408 within a certain period. The description here takes the measurement of the rising edge as an example, and those skilled in the art can easily extend the method of measuring the falling edge without creative input, so it is not repeated.

[0050] The operation of the measuring device 400 will be described below.

[0051] In the calibration mode, the measuring device 400 performs the following operations: Fig. 9 The process shown.

[0052] In step 901, reset signal, enable signal and selection signal are set to enter calibration mode. In this step, reset signal is sent to reset all D flip-flops in measuring device 400, enable signal 407 is set to 0, the output of Q terminal of D flip-flop 501 is also 0, so that the output terminal of AND gate 502 is 0, and selection signal 505 of multiplexer 503 and multiplexer 504 is set to 1 to select the output terminal signal of AND gate 502 to pass through multiplexer 503 and multiplexer 504.

[0053] In step 902, the switches of the width-adjustable delay unit 416 are set. More specifically, half of the switches in the adjustable delay unit 702 are set to be turned on and half are turned off, so that the pre-delay data signal 420 passes through half of the delay units of the adjustable delay unit 702. Taking the aforementioned adjustable delay unit 702 with 32 stages of delay units in series as an example, in this step, the pre-delay data signal 420 passes through 16 buffers. It has been verified in simulation that such a delay time can make the data signal 409 approximately one cycle later than the reference signal 408.

[0054] In step 903, the switches in the reference fine-tuning delay unit 412 and the data fine-tuning delay unit 415 are set to be fully turned on, so that the pre-delay reference signal 419 does not pass through all the delay step units of the reference fine-tuning delay unit 412, and the pre-delay data signal 420 does not pass through all the delay step units of the data fine-tuning delay unit 415. In this case, the clock signal 406 is only delayed by approximately 1 cycle based on the width adjustment delay unit 416.

[0055] In step 904, all reset signals are turned off and the D flip-flop starts to operate.

[0056] In step 905, the selection signal 505 is set to 0 and maintained for a specific period, and the output signals of the multiplexer 503 and the multiplexer 504 are respectively changed to the data oscillation signal 410 and the reference oscillation signal 411. The reference oscillation signal 411 (i.e., the reference signal 419 before delay) generates almost no delay time after passing through the reference fine-tuning delay unit 412, and then passes through the inverter 413 and returns to the input end of the multiplexer 504. Since the input end and the output end of the inverter 413 are inverted, the inverter 413 can make the reference oscillation signal 411 oscillate, and the selection signal 505 is set to maintain at 0 within 1000 cycles, so the calibration counter 414 counts the number of oscillations of the reference oscillation signal 411 when the switch is fully turned on.

[0057] The data oscillation signal 410 (i.e., the data signal before delay 420) has almost no delay time after passing through the data fine-tuning delay unit 415, and then passes through the wide-tuning delay unit 416, so that the clock period difference between the data oscillation signal 410 and the reference oscillation signal 411 is close to at least one integer period, and finally passes through the inverter 417 to generate oscillation and return to the input end of the multiplexer 503. The calibration counter 418 counts the number of oscillations of the data oscillation signal 410 when the switch is fully turned on within 1000 periods.

[0058] In step 906, the selection signal 505 is set to 1 and maintained for several cycles. In this step, the pre-delay reference signal 419 and the pre-delay data signal 420 become the output signals of the AND gate 502, that is, they are maintained at 0, and the calibration counter 414 and the calibration counter 418 start to collect counting signals, that is, to identify the number of oscillations of the data oscillation signal 410 and the reference oscillation signal 411 within 1000 time periods. Since counting the number of times takes time, this step needs to be maintained for several cycles, which is 5 cycles in this embodiment.

[0059] In step 907, the data of calibration counter 414 and calibration counter 418 are read to obtain the oscillation times of data oscillation signal 410 and reference oscillation signal 411. Since the switches in reference fine-tuning delay unit 412 and data fine-tuning delay unit 415 are all turned on in step 903, the delay is minimum and the oscillation times are maximum. Therefore, the oscillation times of data oscillation signal 410 obtained in this step are the maximum value S. max The oscillation number of the reference oscillation signal 411 is the maximum value C max .

[0060] In step 908, a reset signal and a selection signal are set. In this step, a reset signal is sent to reset all D flip-flops in the measuring device 400, and the selection signal 505 of the multiplexer 503 and the multiplexer 504 is set to 1 to select the output signal of the AND gate 502 to pass through the multiplexer 503 and the multiplexer 504.

[0061] In step 909, the switches in the reference fine-tuning delay unit 412 and the data fine-tuning delay unit 415 are set to be completely closed, so that the pre-delay reference signal 419 passes through all the delay step units of the reference fine-tuning delay unit 412, and the pre-delay data signal 420 passes through all the delay step units of the data fine-tuning delay unit 415. In this case, the reference signal 408 and the data signal 409 generate the maximum delay time.

[0062] In step 910, all reset signals are turned off and the D flip-flop starts to operate.

[0063] In step 911, the selection signal 505 is set to 0 and maintained for a specific period, and the output signals of the multiplexer 503 and the multiplexer 504 are respectively changed to the data oscillation signal 410 and the reference oscillation signal 411. The inverter 413 allows the reference oscillation signal 411 to oscillate, and the selection signal 505 is set to be maintained at 0 for 1000 periods, so the calibration counter 414 counts the number of oscillations of the reference oscillation signal 411 when the switch is fully closed. The data oscillation signal 410 also oscillates, and the calibration counter 418 counts the number of oscillations of the data oscillation signal 410 when the switch is fully closed for 1000 periods.

[0064] In step 912, the selection signal 505 is set to 1 and maintained for several cycles. In this step, the signals of the reference circuit 402 and the data circuit 403 are 0, and the calibration counter 414 and the calibration counter 418 start to collect counting signals, that is, to identify the number of oscillations of the data oscillation signal 410 and the reference oscillation signal 411 within 1000 time cycles. Similarly, the selection signal 505 is maintained at 1 for several cycles.

[0065] In step 913, the data of the calibration counter 414 and the calibration counter 418 are read to obtain the oscillation times of the data oscillation signal 410 and the reference oscillation signal 411. Since the switches in the reference fine-tuning delay unit 412 and the data fine-tuning delay unit 415 are all turned off in step 909, the delay is the largest and the oscillation times are the smallest. Therefore, the minimum oscillation times S of the data oscillation signal 410 obtained in this step is min The minimum oscillation number C of the reference oscillation signal 411 min .

[0066] At this point, the calibration mode ends, and the measuring device 400 measures the minimum oscillation number S of the data terminal within 1000 time periods. min and the maximum value S max , and the minimum oscillation number of the reference end within 1000 time periods C min and the maximum value C max The resolution of the data oscillation path is:

[0067]

[0068] In this embodiment, the calibration cycle is 1000 cycles, the number of delay units in the data fine-tuning delay unit 415 is 32, and the resolution Ts is the unit delay of the data fine-tuning delay unit 415, that is, the fine-tuning delay step controlled by each switch in the data fine-tuning delay unit 415.

[0069] Similarly, the resolution of the reference oscillation path is:

[0070]

[0071] The resolution Tc is the unit delay in the reference fine-tuning delay unit 412 , that is, the fine-tuning delay step controlled by each switch in the reference fine-tuning delay unit 412 .

[0072] In the calibration mode, the fine-tuning delay step lengths of the data fine-tuning delay unit 415 and the reference fine-tuning delay unit 412 are measured. This method can tolerate errors in the physical implementation of the chip and still produce a fixed delay time.

[0073] Then the measuring device 400 enters the measuring mode. Fig.10 The flowchart shown is executed by the measuring device 400 in the measuring mode.

[0074] In step 1001, reset signal, enable signal and selection signal are set to enter measurement mode. In this step, reset signal is sent to reset all D flip-flops in measurement device 400, enable signal 407 is set to 0, the output of Q terminal of D flip-flop 501 is also 0, so that the output terminal of AND gate 502 is 0, and selection signal 505 of multiplexer 503 and multiplexer 504 is set to 1 to select the output terminal signal of AND gate 502 to pass through multiplexer 503 and multiplexer 504.

[0075] In step 1002 , the switches of the width adjustable delay unit 416 are set. More specifically, half of the switches in the adjustable delay unit 702 are set to be on and half to be off, so that the data signal 409 is about one cycle later than the reference signal 408 .

[0076] In step 1003 , all switches in the reference fine-tuning delay unit 412 are set to be closed and all switches in the data fine-tuning delay unit 415 are set to be opened. In this case, the reference signal 408 generates a maximum delay and the data signal 409 generates a minimum delay.

[0077] In step 1004, all reset signals are turned off and the D flip-flop starts to operate.

[0078] In step 1005, the enable signal 407 is set to 1 and maintained for a specific period. When the enable signal 407 is 1, the output of the Q terminal of the D flip-flop 501 is also 1, so that the output terminal of the AND gate 502 follows the clock signal 406. At the same time, since the selection signal 505 of the multiplexer 503 and the multiplexer 504 is set to 1 in step 1001, the clock signal 406 enters the reference circuit 402 and the data circuit 403 through the multiplexer 503 and the multiplexer 504. The selection signal 505 is set to be maintained at 1 within 1000 cycles, so the number of times the signal edge of the data signal 409 received by the counter 404 leads and lags behind the signal edge of the reference signal 408 within 1000 cycles is measured, that is, the number of jitters of the data signal 409 within 1000 cycles is recorded.

[0079] In step 1006, the enable signal 407 is set to 0 and maintained for several cycles, the output terminal signals of the multiplexer 503 and the multiplexer 504 are 0, so the reference signal 408 and the data signal 409 are 0, and the measurement counter 404 starts to output the number of jitters, that is, to identify the number of jitters of the data signal 409 within 1000 time periods. Since it takes time to count the number of times, the selection signal 505 needs to be 1 for several cycles, which is 5 cycles in this embodiment.

[0080] In step 1007, the data of the counter 802 is read to obtain the number of jitters.

[0081] In step 1008 , a reset signal is set so that all D flip-flops in the measuring device 400 are reset.

[0082] In step 1009, one of the switches in the data fine-tuning delay unit 415 is turned off. Under the premise of the original setting, one more switch in the data fine-tuning delay unit 415 is turned off to increase one unit of time delay on the data path.

[0083] In step 1010, all reset signals are turned off and the D flip-flop starts to operate.

[0084] In step 1011, the enable signal 407 is set to 1 and maintained for a specific period, and the clock signal 406 enters the reference circuit 402 and the data circuit 403 through the multiplexers 503 and 504. The selection signal 505 is set to be maintained at 1 within 1000 cycles, so the measurement counter 404 receives the reference signal 408 and the data signal 409 within 1000 cycles and records the number of jitters of the data signal 409 within 1000 cycles.

[0085] In step 1012 , the enable signal 407 is set to 0 and maintained for several cycles, and the measurement counter 404 starts to output the number of jitters.

[0086] In step 1013 , the data of the counter 802 is read to obtain the jitter times of the clock signal 406 .

[0087] In step 1014 , a reset signal is set so that all D flip-flops in the measuring device 400 are reset.

[0088] In step 1015, one of the switches in the reference fine-tuning delay unit 412 is turned on. One more switch in the reference fine-tuning delay unit 412 is turned on under the original setting to reduce one unit of time delay on the reference path.

[0089] In step 1016, all reset signals are turned off and the D flip-flop starts to operate.

[0090] In step 1017, the enable signal 407 is set to 1 and maintained for a specific period, and the clock signal 406 enters the reference circuit 402 and the data circuit 403 through the multiplexers 503 and 504. The selection signal 505 is set to be maintained at 1 within 1000 cycles, so the measurement counter 404 measures the number of jitters of the data signal 409 within 1000 cycles.

[0091] In step 1018 , the enable signal 407 is set to 0 and maintained for several cycles, and the measurement counter 404 starts to output the number of jitters.

[0092] In step 1019 , the data of the counter 802 is read to obtain the jitter times of the clock signal 406 .

[0093] In step 1020, it is determined whether all switches in the reference fine-tuning delay unit 412 are turned on. If so, it means that the jitter data under all fine-tuning conditions have been measured, so step 1021 is executed to end the process. If not, it returns to step 1009 to continue to fine-tune the time delay to measure the jitter data.

[0094] After obtaining all the jitter data, a normal distribution diagram of the jitter of the clock signal can be made to study the differences between simulation data and process, and to optimize and improve the circuit.

[0095] Another embodiment of the present invention is a computer-readable storage medium, on which a computer program code for measuring clock signal jitter is stored, and when the computer program code is run by a processor, the method of each embodiment described above is executed. In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the solution of the present invention is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present invention. The aforementioned memory may include, but is not limited to, various media that can store program codes, such as a U disk, a flash disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0096] The present invention uses two oscillation circuits to work, and through the adjustment of the calibration mode, it can effectively avoid the problem of failing to collect valid data. In the measurement mode, the on and off of the switch are adjusted in sequence to record the number of jitters under different time delays, and then obtain the normal distribution diagram of the clock signal jitter, so as to study the differences between simulation data and processes, and optimize and improve the circuit. The measurement device of the present invention does not need to accurately control the physical implementation of the chip, and the resolution is improved, making it easy to collect data.

[0097] It should be noted that, for the purpose of simplicity, the present invention describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will appreciate that the scheme of the present invention is not limited by the order of the described actions. Therefore, based on the disclosure or teaching of the present invention, those skilled in the art will appreciate that some of the steps therein may be performed in other orders or simultaneously. Further, those skilled in the art will appreciate that the embodiments described in the present invention may be regarded as optional embodiments, i.e., the actions or modules involved therein are not necessarily necessary for the implementation of one or some schemes of the present invention. In addition, depending on the different schemes, the present invention also has different emphases on the description of some embodiments. In view of this, those skilled in the art will appreciate that the parts not described in detail in a certain embodiment of the present invention may also refer to the relevant descriptions of other embodiments.

[0098] In terms of specific implementation, based on the disclosure and teachings of the present invention, those skilled in the art can understand that several embodiments disclosed in the present invention can also be implemented in other ways not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this article splits them on the basis of considering the logical functions, and there may be other ways of splitting them in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in the units or components can be selectively disabled. In terms of the connection relationship between different units or components, the connection discussed in the above text in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0099] In the present invention, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. The aforementioned components or units may be located at the same location or distributed on multiple network units. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the scheme described in the embodiment of the present invention. In addition, in some scenarios, multiple units in the embodiment of the present invention may be integrated into one unit or each unit may exist physically separately.

[0100] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as central processing units, GPUs, FPGAs, DSPs, and ASICs, etc. Further, the aforementioned storage unit or storage device may be any appropriate storage medium (including magnetic storage media or magneto-optical storage media, etc.), which may be, for example, a variable resistive memory (Resistive Random Access Memory, RRAM), a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), an enhanced dynamic random access memory (Enhanced Dynamic Random Access Memory, EDRAM), a high bandwidth memory (High Bandwidth Memory, HBM), a hybrid memory cube (Hybrid Memory Cube, HMC), ROM and RAM, etc.

[0101] The foregoing content can be better understood in accordance with the following terms:

[0102] Item A1. A measuring device for measuring the jitter of a clock signal, comprising: a reference circuit, responsive to the clock signal, for generating a reference signal; a data circuit, responsive to the clock signal, for generating a data signal, wherein the clock period of the data signal differs from that of the reference signal by approximately at least one integer period; and a measuring counter, for recording the number of jitters of the data signal edge being earlier or later than the reference signal edge of the reference signal within a specific time.

[0103] Item A2. The measuring device according to Item A1 further includes: a mode selector for switching between a calibration mode and a measurement mode; in the calibration mode, the data circuit adjusts the delay time of the data signal so that the clock period of the data signal differs from that of the reference signal by close to at least 1 integer period; in the measurement mode, the measurement counter records the number of jitters.

[0104] Item A3. The measuring device of Item A2, wherein the reference circuit comprises a reference fine-tuning delay unit for generating a delay for the clock signal.

[0105] Item A4. A measuring device according to Item A3, wherein the reference fine-tuning delay unit comprises a plurality of delay step units and switches, wherein the switches control the number of the clock signals flowing through the delay step units.

[0106] Item A5. A measuring device according to Item A2, wherein the data circuit includes a width adjustment delay unit for controlling the edge of the data signal to be at least one integer cycle later than the edge of the reference signal in the calibration mode.

[0107] Item A6. A measuring device according to Item A5, wherein the wide-adjustable delay unit comprises: a fixed delay unit for providing a fixed delay time for the clock signal; and an adjustable delay unit comprising a plurality of buffers and switches, wherein the switches control the amount of the clock signal flowing through the buffers.

[0108] Clause A7. The measuring device according to clause A6, wherein the number of the buffer and the number of the switch are 2 N The switch is responsive to an N-bit selection signal to control the number of the clock signals flowing through the buffer.

[0109] Item A8. The measuring device according to Item A5, wherein the data circuit further comprises a data fine-tuning delay unit for controlling the data signal edge to be slightly earlier than the reference signal edge.

[0110] Item A9. A measuring device according to Item A8, wherein the data fine-tuning delay unit comprises a plurality of delay step units and switches, and the switches control the number of delay step units through which the data signal flows to control the delay time of the data signal.

[0111] Item A10. A measuring device according to Item A4 or 9, wherein the reference circuit comprises: an inverter for causing the reference signal to oscillate in the calibration mode; and a calibration counter for counting the number of oscillations.

[0112] Item A11. A measuring device according to Item A10, wherein the calibration counter counts the number of oscillations when the switch is fully opened and fully closed respectively.

[0113] Item A12. The measuring device of Item A4 or 9, wherein the data circuit comprises: an inverter configured to cause the data signal to oscillate in the calibration mode; and a calibration counter configured to count the number of oscillations.

[0114] Item A13. A measuring device according to Item A12, wherein the calibration counter counts the number of oscillations when the switch is fully opened and fully closed respectively.

[0115] Item A14. A measuring device according to Item A4 or 9, wherein in a measuring mode, the switches are opened and closed in sequence, and the measuring counter records the number of jitters respectively.

[0116] Clause A15. The measurement device of clause A1, wherein the specific time is 1000 clock cycles.

[0117] Item A16. The measuring device of Item A1, wherein the data signal edge and the reference signal edge are one of a rising edge and a falling edge.

[0118] Clause A17. An integrated circuit device comprising a measuring device according to any one of clauses A1-16.

[0119] Clause A18. A board comprising the integrated circuit device according to clause A17.

[0120] The embodiments of the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A measuring device for measuring clock signal jitter, comprising: A reference circuit, responsive to the clock signal, for generating a reference signal; A data circuit, responsive to the clock signal, for generating a data signal, wherein the clock period of the data signal differs from that of the reference signal by approximately at least one integer period; as well as A measurement counter, for recording the number of jitters of a data signal edge of the data signal being earlier or later than a reference signal edge of the reference signal within a specific time; Mode selector, used to switch between calibration mode and measurement mode; In the calibration mode, the data circuit adjusts the delay time of the data signal so that the clock period difference between the data signal and the reference signal is close to at least one integer period; In the measurement mode, the measurement counter records the number of jitters; The data circuit includes a width adjustment delay unit for controlling the edge of the data signal to be at least one integer cycle later than the edge of the reference signal in the calibration mode; The width adjustment delay unit comprises: The adjustable delay unit includes a plurality of buffers and a plurality of switches, wherein the switches control the number of the clock signals flowing through the buffers. 2 . The measuring device according to claim 1 , wherein the reference circuit comprises a reference fine-tuning delay unit for generating a delay for the clock signal. 3 . The measuring device according to claim 2 , wherein the reference fine-tuning delay unit comprises a plurality of delay step units and a plurality of switches, and the switches control the number of the clock signal flowing through the delay step units.

4. The measuring device according to claim 1, wherein the width adjustment delay unit further comprises: The fixed delay unit is used to provide a fixed delay time for the clock signal.

5. The measuring device according to claim 4, wherein the number of the switches is 2 N The switch is responsive to an N-bit selection signal to control the number of the clock signals flowing through the buffer. 6 . The measuring device according to claim 1 , wherein the data circuit further comprises a data fine-tuning delay unit for controlling an edge of the data signal to be slightly earlier than an edge of the reference signal. 7 . The measuring device according to claim 6 , wherein the data fine-tuning delay unit comprises a plurality of delay step units and a plurality of switches, and the switches control the number of the data signal flowing through the delay step unit to control the delay time of the data signal.

8. The measuring device according to claim 3 or 7, wherein the reference circuit comprises: an inverter, configured to cause the reference signal to oscillate in the calibration mode; as well as Calibrate the counter to count the number of oscillations. 9 . The measuring device according to claim 8 , wherein the calibration counter counts the number of oscillations when the switch is fully opened and fully closed respectively.

10. The measuring device according to claim 3 or 7, wherein the data circuit comprises: an inverter, configured to cause the data signal to oscillate in the calibration mode; as well as Calibrate the counter to count the number of oscillations. 11 . The measuring device according to claim 10 , wherein the calibration counter counts the number of oscillations when the switch is fully opened and fully closed respectively. 12 . The measuring device according to claim 3 , wherein in a measuring mode, the switches are turned on and off in sequence, and the measuring counter records the number of jitters respectively.

13. The measuring device according to claim 1, wherein the specific time is 1000 clock cycles. 14 . The measuring device according to claim 1 , wherein the data signal edge and the reference signal edge are one of a rising edge and a falling edge.

15. An integrated circuit device comprising a measuring device according to any one of claims 1 to 14.

16. A card comprising the integrated circuit device according to claim 15.

Images