A compiling method for converting scalable assembly instructions into binary instructions

Abstract

The present invention discloses a compiling method for converting an extensible assembly instruction into a binary instruction, and the steps include: setting a metafunction template set table, a metafunction mapping table, and an instruction and metafunction template mapping table; step 2: obtaining each assembly instruction to be processed, searching the instruction and metafunction template mapping table, and obtaining the name and instruction operation code of the metafunction template corresponding to each assembly instruction; step 3: searching the metafunction template set table according to the name of the metafunction template, and obtaining the corresponding metafunction template; step 4: traversing the fields of each metafunction template, finding the encoding method corresponding to each field, and obtaining the binary encoding corresponding to each field; step 5: combining the binary encoding of each field with the instruction operation code, and obtaining the binary instruction encoding corresponding to each assembly instruction. The present invention can realize the compilation of assembly instructions to binary instructions, and has the advantages of simple operation, low cost, high efficiency, good scalability, etc.

Description

Technical Field

[0001] The present invention relates to the technical field of assembly instruction compilation, and in particular to a compiling method for converting extensible assembly instructions into binary instructions. Background Art

[0002] The conversion of assembly instructions into binary instructions is to compile the source program code written in assembly language into a target file of binary instructions. The compilation of assembly instructions into binary instructions is usually implemented by an assembler. There is a one-to-one correspondence between assembly instructions and binary instructions. The conversion of assembly instructions into binary instructions is the process of direct translation. The assembly language program code can be the assembly code compiled and output by a high-level language compiler, or it can be the assembly language program code written by hand. When compiling the conversion of assembly instructions into binary instructions, the difficulty lies mainly in how to accurately and efficiently define the mapping conversion relationship between the two, and how to adaptively respond to the expansion changes of different instruction set architectures (Instruction Set Architecture, referred to as ISA).

[0003] When using an assembler to compile assembly instructions into binary instructions in the prior art, the assembler needs to be developed in conjunction with the design of the target processor, that is, when designing a new processor, it is necessary to redevelop the corresponding assembler to realize the compilation of assembly instructions into binary instructions. Since ISA and target processors are different under different compilation tasks, it is usually necessary to develop different assemblers for different ISAs to meet the requirements of different target processors. Different target processors are also different in terms of instruction word length, instruction encoding mode, register setting and number of functional units, so that different assemblers are very different in the design and implementation of instruction compilation. Therefore, for each new ISA or when the original ISA needs to be improved and expanded, it is also necessary to redevelop an assembler adapted thereto to realize the conversion of assembly instructions into binary instructions. Therefore, the flexibility and scalability of the method for realizing the conversion of assembly instructions into binary instructions in the prior art are poor, and the design and development of the assembler need to be re-performed for different target processors, different ISAs, etc., resulting in low development efficiency, long cycle and high cost. Summary of the invention

[0004] The technical problem to be solved by the present invention is: in view of the technical problems existing in the prior art, the present invention provides a compiling method for converting extensible assembly instructions into binary instructions which is simple in operation, low in cost, high in efficiency and good in extensibility.

[0005] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0006] A compiling method for converting scalable assembly instructions into binary instructions, the steps comprising:

[0007] Step 1: Set a metafunction template set table, a metafunction mapping table, and an instruction-metafunction template mapping table, wherein the metafunction template set table includes multiple metafunction templates, the metafunction mapping table records the encoding method corresponding to each field in the metafunction template, and the instruction-metafunction template mapping table records the mapping relationship between the assembly instruction and the metafunction template;

[0008] Step 2: Obtain each assembly instruction to be processed, search the instruction and meta-function template mapping table according to the information of each assembly instruction, and obtain the name and instruction operation code of the meta-function template corresponding to each assembly instruction;

[0009] Step 3: searching the meta-function template set table according to the name of the meta-function template found, and obtaining the meta-function template corresponding to each assembly instruction;

[0010] Step 4: traverse the fields of each meta-function template obtained in step 3, find out the encoding method corresponding to each field in each meta-function template from the meta-function mapping table, and obtain the binary encoding corresponding to each field according to the found encoding method;

[0011] Step 5: Combine the binary codes of the fields obtained in step 4 with the instruction operation code to obtain the binary instruction code corresponding to each assembly instruction.

[0012] Furthermore, the instruction and meta-function template mapping table includes multiple instruction quintuples, each instruction of the target processor instruction set corresponds to an instruction quintuple, and the instruction quintuple includes five parts: the instruction mnemonic name, the functional unit name corresponding to the instruction, the first parameter type of the instruction, the name of the meta-function template corresponding to the assembly instruction, and the instruction opcode.

[0013] Furthermore, step 1 also includes setting a register encoding mapping table and a functional unit encoding mapping table, wherein the register encoding mapping table records the mapping relationship between all registers in the target processor and their corresponding binary encodings, and the functional unit encoding mapping table records the mapping relationship between all functional units in the target processor and their corresponding binary encodings.

[0014] Furthermore, in the step 2, the instruction and meta-function template mapping table is searched according to the instruction mnemonic name, the function unit name and the first parameter type information of each assembly instruction.

[0015] Furthermore, the meta-function template includes the name of the meta-function template and a plurality of field triplets, wherein the field triplets include the field name, the number of binary bits of the field and the default binary encoding of the field.

[0016] Furthermore, in step 4, the field triplets of each meta-function template obtained in step 3 are traversed to find out the encoding method corresponding to each field in each meta-function template from the meta-function mapping table.

[0017] Furthermore, the number of the field triplets in the meta-function template is consistent with the number of fields described in the instruction of the target processor instruction set, and the field triplets are sorted in order from high to low according to the fields of the instruction description, wherein the meta-function templates having the same number of the field triplets and each of the field triples contained therein are identical use the same meta-function template name.

[0018] Furthermore, the encoding method corresponding to each field in the meta-function template specifies the corresponding binary encoding according to the number of binary bits and semantics of each field.

[0019] Furthermore, in step 4, if there is no encoding method corresponding to the current field in the meta-function mapping table, the default binary encoding of the current field is taken as the corresponding binary encoding.

[0020] A computer-readable storage medium storing a computer program, wherein the computer program implements the above method when executed.

[0021] Compared with the prior art, the advantages of the present invention are:

[0022] 1. The present invention forms a metafunction template set table by setting multiple metafunction templates, and at the same time sets a metafunction mapping table and an instruction and metafunction template mapping table to respectively record the encoding method corresponding to each field in the metafunction template and the mapping relationship between the assembly instruction and the metafunction template. When processing the assembly instruction, the metafunction template and the instruction operation code are found according to the above-mentioned mapping tables, and then the binary code corresponding to each field is found. The binary code is combined with the instruction operation code to realize the conversion of the assembly instruction to the binary instruction. Not only is the operation simple to implement, but also the flexibility and scalability of the compilation can be greatly improved, and at the same time, the development workload can be greatly reduced and the development efficiency can be improved.

[0023] 2. The present invention can realize new instruction extension by simply adding a meta-function definition, and has no impact on other meta-functions and other modules. Different processing of different fields can be realized by establishing different meta-function templates, which can significantly shorten the development cycle. At the same time, it can dynamically adapt to the improvement and expansion of ISA and is suitable for different numbers of functional units and different numbers of registers.

[0024] 3. The present invention distinguishes different instruction types according to the field description of the instruction. Different instructions with the same field description can be attributed to the same meta-function template, which can greatly reduce the number of meta-function templates. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the implementation flow of the scalable method for compiling assembly instructions to binary instructions in this embodiment.

[0026] Figure 2 It is a schematic diagram of the structure of each table set in step 1 of this embodiment.

[0027] Figure 3 It is a schematic diagram of the specific structure of the register encoding mapping table in this embodiment.

[0028] Figure 4 It is a schematic diagram of the specific structure of the functional unit coding mapping table in this embodiment.

[0029] Figure 5 It is a schematic diagram of the specific structure of the meta-function template set table and the meta-function template in this embodiment.

[0030] Figure 6 It is a schematic diagram of the specific structure of the meta-function mapping table in this embodiment.

[0031] Figure 7 It is a schematic diagram of the specific structure of the instruction and meta-function template mapping table in this embodiment.

[0032] Figure 8 It is a schematic diagram of the compilation implementation flow of an assembly instruction to a binary instruction in a specific application embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention is further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0034] like Figure 1 As shown, the steps of the compiling method of the scalable assembly instruction to binary instruction in this embodiment include:

[0035] Step 1: Set a metafunction template set table, a metafunction mapping table, and an instruction-metafunction template mapping table. The metafunction template set table contains multiple metafunction templates. The metafunction mapping table records the encoding method corresponding to each field in the metafunction template. The instruction-metafunction template mapping table records the mapping relationship between assembly instructions and metafunction templates.

[0036] Step 2: Obtain each assembly instruction to be processed, search the instruction and meta-function template mapping table according to the information of each assembly instruction, and obtain the name and instruction operation code of the meta-function template corresponding to each assembly instruction;

[0037] Step 3: Search the meta-function template set table according to the name of the meta-function template found, and obtain the meta-function template corresponding to each assembly instruction;

[0038] Step 4: traverse the fields of each meta-function template obtained in step 3, find out the encoding method corresponding to each field in each meta-function template from the meta-function mapping table, and obtain the binary encoding corresponding to each field according to the found encoding method;

[0039] Step 5: Combine the binary codes of each field obtained in step 4 with the instruction operation code to obtain the binary instruction code corresponding to each assembly instruction.

[0040] This embodiment forms a metafunction template set table by setting multiple metafunction templates, and at the same time sets a metafunction mapping table and an instruction and metafunction template mapping table to respectively record the encoding method corresponding to each field in the metafunction template and the mapping relationship between the assembly instruction and the metafunction template. When processing the assembly instruction, the metafunction template and the instruction operation code are found according to the above mapping tables, and then the binary code corresponding to each field is found. The binary code and the instruction operation code are combined to realize the conversion of the assembly instruction to the binary instruction. Not only is the operation simple to realize, but also the flexibility and scalability of the compilation can be greatly improved, and the expansion changes of different ISAs can be adaptively responded. In particular, when expanding new instructions, such as when a new field semantic action needs to be added, only one metafunction definition needs to be added, which has no effect on other metafunctions and other modules, and can significantly shorten the development cycle, reduce the development workload, and greatly improve the development efficiency.

[0041] In this embodiment, the instruction and meta-function template mapping table specifically includes multiple instruction quintuples. Each instruction of the target processor instruction set corresponds to an instruction quintuple. The instruction quintuple specifically includes five parts: the instruction mnemonic name, the functional unit name corresponding to the instruction, the first parameter type of the instruction, the name of the meta-function template corresponding to the assembly instruction, and the instruction opcode.

[0042] In this embodiment, step 1 also includes setting a register encoding mapping table and a function unit encoding mapping table, wherein the register encoding mapping table records the mapping relationship between all registers in the target processor and their corresponding binary encodings, and the function unit encoding mapping table records the mapping relationship between all function units in the target processor and their corresponding binary encodings. In step 2, for each assembly instruction, specifically according to the instruction mnemonic name, the function unit name and the first parameter type information of each assembly instruction, the instruction and meta-function template mapping table is searched to find out the name and instruction opcode of the meta-function template corresponding to each assembly instruction.

[0043] In this embodiment, the meta-function template specifically includes the name of the meta-function template, multiple field triplets, and the field triplets include the field name, the number of binary digits of the field, and the default binary encoding of the field. In step 4, the field triplets of each meta-function template obtained in step 3 are traversed to find the encoding method corresponding to each field in each meta-function template from the meta-function mapping table.

[0044] In a specific application embodiment, the number of field triplets in the metafunction template is consistent with the number of fields described in the instruction of the target processor instruction set, and the field triplets are sorted in order from high to low according to the fields described in the instruction, wherein the metafunction templates having the same number of field triplets and each of the contained field triplets being the same use the same metafunction template name, that is, the metafunction templates having the same number of field triplets and each of the contained field triplets being the same are defined as the same metafunction template. The encoding method corresponding to each field in the metafunction template specifies the corresponding binary encoding according to the number of binary bits and semantics of each field.

[0045] like Figure 2 As shown, the present embodiment specifically sets a register encoding mapping table, a function unit encoding mapping table, a meta-function template set table, a meta-function mapping table, and an instruction and meta-function template mapping table, wherein each entry in the register encoding mapping table includes a register name and a corresponding binary code to record the mapping relationship between all registers in the target processor and the corresponding binary code; each entry in the function unit encoding mapping table includes a function unit name and a corresponding binary code to record the mapping relationship between all function units in the target processor and the corresponding binary code; the meta-function template set table includes a plurality of meta-function templates, and the composition structure of each meta-function template includes: the meta-function template name , multiple field triplets, wherein the field triplet consists of three parts: the field name, the number of binary bits of the field and the default binary encoding of the field; each entry in the metafunction mapping table includes a field name and a corresponding encoding method to record the encoding method corresponding to the field in the metafunction template, and the encoding method corresponding to the field specifies the corresponding binary encoding according to the number of binary bits and semantics of the field; the metafunction template mapping table is composed of multiple instruction quintuples, and each instruction of the target processor instruction set corresponds to an instruction quintuple, which specifically consists of five parts: the instruction mnemonic name, the functional unit name corresponding to the instruction, the first parameter type of the instruction, the metafunction template name corresponding to the instruction and the instruction opcode.

[0046] The present invention distinguishes different instruction types by describing the fields of the instructions. Different instructions with the same field description can be attributed to the same meta-function template. Compared with the traditional method of distinguishing different instruction types according to instructions, the number of meta-function templates can be greatly reduced. Moreover, for the same instruction, if there are several different special processes, new different meta-function templates can be established according to different field descriptions, which can dynamically adapt to the improvement and expansion of ISA, and can be applicable to different numbers of functional units and different numbers of registers. When a new field semantic action needs to be added, only one meta-function definition needs to be added. It has good scalability, thereby greatly reducing the development workload and significantly shortening the development cycle.

[0047] In a specific application embodiment, Figure 3 As shown, the target processor specifically includes an address base register, an address offset register, a vector register, and a scalar register. The target processor includes 16 address base registers AR0-AR15 and 16 address offset registers OR0-OR15, a total of 32 address registers, which are distinguished by 5-bit encoding. The target processor includes 64 vector registers VR0-VR63, which are distinguished by 6-bit encoding. The target processor includes 64 scalar registers R0-R63, which are distinguished by 6-bit encoding.

[0048] In a specific application embodiment, Figure 4 As shown, the target processor specifically includes 11 functional units, namely SIEU, SMAC1, SMAC2, SBR, SLDST, VMAC0, VMAC1, VMAC2, VMAC3, VLDSTO, and VLDST1, which are distinguished by 4-bit encoding.

[0049] In specific application implementations, for example Figure 5 As shown, it includes M_NUM=20 meta-function templates, of which MAC_32R includes 7 field triplets and MAC_32IMM includes 7 field triplets. Since the field triplets of the above two meta-function templates are different, they are divided into 2 meta-function templates.

[0050] In specific application implementations, for example Figure 6 As shown, the meta-function mapping table includes F_NUM=30 items, and the processor instruction set of this embodiment requires F_NUM=30 field encoding methods to encode the fields.

[0051] In specific application implementations, for example Figure 7As shown, there are N_NUM=923 quintuples in total, and each quintuple corresponds to each instruction of the target processor instruction set. Among them, the metafunction template MAC_32R occupies 603 groups, and the metafunction template MAC_32IMM occupies 194 groups. The two metafunction templates have covered 88% of the instructions of the instruction set, and 5 instructions occupy a metafunction template alone. This shows that most instructions can use the same metafunction template. As long as the semantic process of generating binary codes for different instruction types is the same, different instruction types can also use the same metafunction template, and then the corresponding assembly function can be generated instantly according to the description of the metafunction template according to the above method of this embodiment. The present invention can take into account the universality and particularity of the instruction format by adopting the metafunction template, so as to dynamically adapt to the improvement and expansion of ISA.

[0052] In a specific application example, Figure 8 As shown, the detailed process of using the above method of the present invention to compile an assembly instruction VFMULS32.VMAC1 VR10, VR11, VR13 to a binary instruction 0X25166AC0 is as follows:

[0053] S1. According to the instruction mnemonic name = VFMULS32, the function unit name = VMAC1 and the first parameter type = R of the assembly instruction, the instruction and meta-function template mapping table is searched to obtain the meta-function template name = MAC_32R and the instruction opcode = 0101100000 corresponding to the assembly instruction.

[0054] S2. Search the meta-function template set table according to the meta-function template name to obtain the meta-function template MAC_32R corresponding to the assembly instruction.

[0055] S3. Traverse all field triplets of the meta-function template obtained in step S2.

[0056] S4. For each field triplet obtained in step S3, search the meta-function mapping table according to the field name, obtain the encoding method corresponding to the field, and obtain the corresponding binary encoding through the encoding method corresponding to the field. If the meta-function mapping table does not have an encoding method corresponding to the field name, the default binary encoding of the field is used.

[0057] S5. According to the binary code of each field obtained in step S4 and the instruction operation code combination, the binary instruction code corresponding to the current assembly instruction is obtained.

[0058] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A compiling method for converting scalable assembly instructions into binary instructions, characterized in that the steps include: Step 1: Set a metafunction template set table, a metafunction mapping table, and an instruction-metafunction template mapping table, wherein the metafunction template set table includes multiple metafunction templates, the metafunction mapping table records the encoding method corresponding to each field in the metafunction template, and the instruction-metafunction template mapping table records the mapping relationship between the assembly instruction and the metafunction template; Step 2: Obtain each assembly instruction to be processed, search the instruction and meta-function template mapping table according to the information of each assembly instruction, and obtain the name and instruction operation code of the meta-function template corresponding to each assembly instruction; Step 3: searching the meta-function template set table according to the name of the meta-function template found, and obtaining the meta-function template corresponding to each assembly instruction; Step 4: traverse the fields of each meta-function template obtained in step 3, find out the encoding method corresponding to each field in each meta-function template from the meta-function mapping table, and obtain the binary encoding corresponding to each field according to the found encoding method; Step 5: Combine the binary codes of the fields obtained in step 4 with the instruction operation code to obtain the binary instruction code corresponding to each assembly instruction.

2. The compiling method for converting scalable assembly instructions into binary instructions according to claim 1, characterized in that: The instruction and meta-function template mapping table includes multiple instruction quintuples, each instruction of the target processor instruction set corresponds to an instruction quintuple, and the instruction quintuple includes five parts: the instruction mnemonic name, the functional unit name corresponding to the instruction, the first parameter type of the instruction, the name of the meta-function template corresponding to the assembly instruction, and the instruction opcode.

3. The compiling method for converting scalable assembly instructions into binary instructions according to claim 2, characterized in that: The step 1 also includes setting a register encoding mapping table and a functional unit encoding mapping table, wherein the register encoding mapping table records the mapping relationship between all registers in the target processor and the corresponding binary encodings, and the functional unit encoding mapping table records the mapping relationship between all functional units in the target processor and the corresponding binary encodings.

4. The compiling method for converting scalable assembly instructions into binary instructions according to claim 3, characterized in that: In the step 2, the instruction and meta-function template mapping table is searched according to the instruction mnemonic name, the function unit name and the first parameter type information of each assembly instruction.

5. The compiling method for converting scalable assembly instructions into binary instructions according to claim 1, characterized in that: The meta-function template includes the name of the meta-function template and a plurality of field triplets, wherein the field triplets include the field name, the number of binary digits of the field and the default binary encoding of the field.

6. The compiling method for converting scalable assembly instructions into binary instructions according to claim 5, characterized in that: In the step 4, the field triplets of each meta-function template obtained in step 3 are traversed to find out the encoding method corresponding to each field in each meta-function template from the meta-function mapping table.

7. The compiling method for converting scalable assembly instructions into binary instructions according to claim 6, characterized in that: The number of field triplets in the metafunction template is consistent with the number of fields described in the instruction of the target processor instruction set, and the field triplets are sorted in order from high to low according to the fields of the instruction description, wherein the metafunction templates having the same number of field triplets and each of the field triples contained therein being the same use the same metafunction template name.

8. The compiling method for converting scalable assembly instructions into binary instructions according to any one of claims 1 to 6, characterized in that: The encoding method corresponding to each field in the meta-function template specifies the corresponding binary encoding according to the number of binary bits and semantics of each field.

9. The compiling method for converting scalable assembly instructions into binary instructions according to any one of claims 1 to 6, characterized in that: In step 4, if there is no encoding method corresponding to the current field in the meta-function mapping table, the default binary encoding of the current field is taken as the corresponding binary encoding.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed, the method according to any one of claims 1 to 9 is implemented.

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