Array substrate and manufacturing method thereof, and display panel

Abstract

The present application discloses an array substrate and a manufacturing method thereof, and a display panel; the array substrate comprises a plurality of thin film transistors, a flat layer and a plurality of first shading portions, the first shading portions penetrate through the multiple insulating layers of the array substrate, the first end of the first shading portion is connected to the flat layer, the second end of the first shading portion extends at least to the active layer of the thin film transistor, and the surface of the first shading portion comprises a rough surface; the present application sets the first shading portion at the periphery of the thin film transistor, after the light outside the thin film transistor is irradiated to the first shading portion, the light is diffusely reflected due to the rough surface of the first shading portion, and the light is dispersed to different directions, thereby reducing the light intensity in the same direction, and at the same time, part of the light is transmitted into the first shading portion and is reflected and refracted again at the critical surface, and the light is further diverged, thereby reducing the light intensity transmitted in the same direction and reducing the light reaching the active layer of the thin film transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new type of display technology. It has gradually attracted people's attention with its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] Since the active layer of the OLED device is sensitive to light, especially ultraviolet light, the threshold voltage of the thin film transistor will decrease under the action of light, affecting the electrical properties of the thin film transistor. In the prior art, a metal light shielding layer is used to block external light to prevent the light from irradiating the active layer, but the light intensity inside the OLED device is still very high, and the light can be reflected back and forth between the gate and the metal light shielding layer and irradiate the active layer. Therefore, how to reduce the light inside the OLED device that irradiates the active layer of the thin film transistor is one of the problems that technicians in this field urgently need to solve. Summary of the invention

[0004] The present application provides an array substrate and a manufacturing method thereof, and a display panel, so as to reduce the technical problem of light from inside an OLED device irradiating onto an active layer of a thin film transistor.

[0005] To solve the above-mentioned problems, the technical solutions provided by this application are as follows:

[0006] The present application provides an array substrate, the array substrate comprising:

[0007] substrate;

[0008] A plurality of thin film transistors are disposed on the substrate;

[0009] A planar layer, disposed on the plurality of thin film transistors; and

[0010] A plurality of first light shielding portions, arranged at the periphery of the plurality of thin film transistors, the first light shielding portions penetrating the multiple insulating layers of the array substrate, a first end of the first light shielding portion being connected to the planar layer, and a second end of the first light shielding portion extending at least to the active layer of the thin film transistor;

[0011] Wherein, the first light shielding portion includes a rough surface, and the first light shielding portion is connected to the multiple insulating layers through the rough surface.

[0012] In the array substrate of the present application, the array substrate includes a plurality of second light-shielding portions, the second light-shielding portions are arranged on the substrate, the projection of the active layer on the second light-shielding portions is located within the second light-shielding portions, and the projection of the first light-shielding portions on the second light-shielding portions does not overlap with the second light-shielding portions.

[0013] In the array substrate of the present application, the array substrate includes a plurality of second light-shielding portions, the second light-shielding portions are arranged on the substrate, the projection of the active layer on the second light-shielding portions is located within the second light-shielding portions, and the projection of the first light-shielding portions on the second light-shielding portions overlaps with the second light-shielding portions.

[0014] In the array substrate of the present application, the second end of the first light shielding portion is connected to the second light shielding portion.

[0015] In the array substrate of the present application, the first light shielding portion includes a first sub-light shielding portion, a second sub-light shielding portion, and a third sub-light shielding portion that are separately arranged. In a top view of the array substrate, the first sub-light shielding portion, the second sub-light shielding portion, and the third sub-light shielding portion are arranged spaced apart from the gate, source, and drain of the thin film transistor;

[0016] Among them, the first sub-light-shielding portion and the second sub-light-shielding portion are located on the same side of the source and drain connection of the thin film transistor, and the third sub-light-shielding portion is located on the other side of the source and drain connection, and the first sub-light-shielding portion and the second sub-light-shielding portion are arranged on both sides of the gate of the thin film transistor.

[0017] In the array substrate of the present application, the thickness of the first sub-light-shielding portion and the second sub-light-shielding portion is greater than the thickness of the third sub-light-shielding portion.

[0018] In the array substrate of the present application, the material of the first light shielding portion is the same as the material of the planar layer.

[0019] In the array substrate of the present application, the refractive index of the first light shielding portion is different from the refractive index of the insulating layer.

[0020] The present application also provides a method for manufacturing an array substrate, the method for manufacturing the array substrate comprising:

[0021] providing a substrate;

[0022] forming a plurality of insulating layers on the substrate, and forming a first light shielding groove on the plurality of insulating layers;

[0023] A planar layer is formed on the multiple insulating layers, and the planar layer fills the first light shielding portion groove to form the first light shielding portion.

[0024] The present application also provides a display panel, which includes a display body and the above-mentioned array substrate, and the array substrate and the display body are combined into one body.

[0025] Beneficial effect: The present application discloses an array substrate and a manufacturing method thereof, and a display panel, wherein the array substrate comprises a substrate, a plurality of thin film transistors arranged on the substrate, a flat layer arranged on the plurality of thin film transistors, and a plurality of first shading portions arranged around the plurality of thin film transistors, wherein the first shading portion penetrates through the multiple insulating layers of the array substrate, a first end of the first shading portion is connected to the flat layer, and a second end of the first shading portion extends at least to the active layer of the thin film transistor; the first shading portion comprises a rough surface, and the first shading portion is connected to the multiple insulating layers through the rough surface; the present application arranges the first shading portion around the thin film transistor The first end of the first light-shielding portion is connected to the flat layer, and the second end of the first light-shielding portion extends at least to the active layer of the thin film transistor. After the light outside the thin film transistor is irradiated on the first light-shielding portion, the light is diffusely reflected due to the rough surface of the first light-shielding portion, and the light is dispersed to different directions, thereby reducing the intensity of the light in the same direction; part of the light is transmitted into the first light-shielding portion, and is reflected and refracted at the critical surface of the first light-shielding portion and the insulating layer. Since the surface of the first light-shielding portion at the critical surface is a rough surface, the light is further diverged, thereby reducing the intensity of the light transmitted in the same direction, thereby reducing the light reaching the active layer of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0027] Figure 1 is a cross-sectional view of the array substrate of the present application;

[0028] Figure 2 This is a first top view of the array substrate of the present application;

[0029] Figure 3 This is a second top view of the array substrate of the present application;

[0030] 4A to 4F This is a manufacturing process diagram of the array substrate of this application.

[0031] Notes on the attached drawings:

[0032] Substrate 101, insulating layer 102, first insulating layer 1021, second insulating layer 1022, third insulating layer 1023, planarization layer 103, thin film transistor 200, first light shielding portion 300, second light shielding portion 400, first sub-light shielding portion 301, second sub-light shielding portion 302, third sub-light shielding portion 303, active layer 201, gate 202, source 203, drain 204, first light shielding portion groove 310, thickness S of the first light shielding portion, thickness S1 of the first sub-light shielding portion, thickness S2 of the second sub-light shielding portion, thickness S3 of the third sub-light shielding portion. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; and "inside" and "outside" refer to the outline of the device.

[0034] Since the active layer of the OLED device is sensitive to light, especially ultraviolet light, the threshold voltage of the thin film transistor will decrease under the action of light, affecting the electrical properties of the thin film transistor. In the prior art, a metal light shielding layer is used to block external light to prevent light from irradiating the active layer, but the light intensity inside the OLED device is still very high, and the light can be reflected back and forth between the gate and the metal light shielding layer and irradiate the active layer. Therefore, how to prevent the internal light of the OLED device from irradiating the active layer of the thin film transistor is one of the problems that technicians in this field urgently need to solve. Based on the above technical problems, this application proposes the following solution.

[0035] This application provides an array substrate. Figures 1 to 3The array substrate includes a substrate 101, a plurality of thin film transistors 200 arranged on the substrate 101, a flat layer 103 arranged on the plurality of thin film transistors 200, and a plurality of first shading portions 300 arranged on the periphery of the plurality of thin film transistors 200, wherein the first shading portions 300 penetrate through the multi-layer insulating layer 102 of the array substrate, a first end of the first shading portion 300 is connected to the flat layer 103, and a second end of the first shading portion 300 extends at least to the active layer 201 of the thin film transistor 200; wherein the first shading portion 300 includes a rough surface, and the first shading portion 300 is connected to the multi-layer insulating layer through the rough surface.

[0036] The present application sets a first light shielding portion 300 on the periphery of the thin film transistor 200, wherein the first end of the first light shielding portion 300 is connected to the flat layer 103, and the second end of the first light shielding portion 300 extends at least to the active layer 201 of the thin film transistor 200. After the light outside the thin film transistor 200 is irradiated on the first light shielding portion 300, the light is diffusely reflected due to the rough surface of the first light shielding portion 300, and the light is dispersed to different directions, thereby reducing the intensity of the light in the same direction; part of the light is transmitted into the first light shielding portion 300, and is reflected and refracted at the critical surface between the first light shielding portion 300 and the insulating layer 102. Since the surface of the first light shielding portion 300 at the critical surface is a rough surface, the light is further diverged, thereby reducing the intensity of the light transmitted in the same direction, thereby reducing the light reaching the active layer 201 of the thin film transistor 200.

[0037] The technical solution of the present application is now described in conjunction with specific embodiments.

[0038] In this example, see Figure 1 , a plurality of thin film transistors 200 are arranged on the array substrate, and the thin film transistors 200 are used to drive the pixels to emit light. The array substrate can be used for LCD display panels, OLED display panels, Mini-LED display panels, Micro-LED display panels, etc. When the array substrate is used for a self-luminous display panel, such as an OLED display panel, a Mini-LED display panel, or a Micro-LED display panel, its light emission direction can be top emission or bottom emission, and this application does not limit this.

[0039] In this embodiment, the thin film transistor 200 may be a thin film transistor with a top gate structure or a thin film transistor with a bottom gate structure, which is not limited in the present application.

[0040] In this embodiment, the substrate 101 may be a hard material, such as glass, or a flexible material, such as polyimide, polycarbonate, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, polyarylate or glass fiber reinforced plastic.

[0041] In this example, see Figures 1 to 3 The first light shielding portion 300 is disposed at the periphery of the thin film transistor 200 to form a retaining wall structure. Furthermore, the first light shielding portion 300 can be disposed perpendicular to the substrate 101, or can be disposed at an acute angle or an obtuse angle with the substrate 101, and the present application does not limit this. The first end of the first light shielding portion 300 is connected to the flat layer 103, and the second end of the first light shielding portion 300 extends downward, at least to the active layer 201 of the thin film transistor 200. Therefore, the first light shielding portion 300 can block the light from the side from directly irradiating the active layer 201.

[0042] In this embodiment, the first light shielding portion 300 includes a rough surface, and the rough surface includes an inner side wall facing the thin film transistor 200, an outer side wall away from the thin film transistor 200, and a bottom surface connecting the inner side wall and the outer side wall. When the light outside the thin film transistor 200 is irradiated to the outer side wall, the light is diffusely reflected because the outer side wall is a rough surface, and the light is dispersed to different directions, reducing the intensity of the light in the same direction; part of the light is refracted into the first light shielding portion 300 and emitted to the inner side wall. Since the inner side wall is a rough surface, the light is reflected and refracted, and the light is further diverged, thereby reducing the intensity of the light transmitted in the same direction, thereby reducing the light reaching the active layer of the thin film transistor.

[0043] In this example, see Figure 1 , the thickness S of the first light shielding portion refers to the horizontal distance between the outer wall and the inner wall of the first light shielding portion. The thickness S of the first light shielding portion is gradually changed in the direction perpendicular to the substrate 101, and the thickness S of the first light shielding portion gradually increases in the direction away from the substrate. Through the above arrangement, at places where the thickness S of the first light shielding portion is different, the reflection and refraction angles of the light are different, thereby further diverging the light, reducing the light passing through the first light shielding portion 300, and reducing the light irradiating the active layer 201 of the thin film transistor 200.

[0044] In this embodiment, the thin film transistor 200 further includes a gate 202, a source 203, a drain 204 and other structures. The gate 202, the source 203, and the drain 204 are arranged within the multi-layer insulating layer 102. The structure is a conventional setting and the present application does not impose any limitation on this.

[0045] See also Figure 1 and Figure 2 In the array substrate of the present application, the array substrate includes a plurality of second light-shielding portions 400, the second light-shielding portions 400 are arranged on the substrate 101, the projection of the active layer 201 on the second light-shielding portions 400 is located within the second light-shielding portions 400, and the projection of the first light-shielding portion 300 on the second light-shielding portion 400 does not overlap with the second light-shielding portion 400.

[0046] In this embodiment, the second light shielding portion 400 is made of a light blocking material, such as metal or metal alloy, including molybdenum, titanium, molybdenum-titanium alloy, etc.

[0047] In this example, see Figure 2 , the projection of the first light shielding portion 300 on the second light shielding portion 400 does not overlap with the second light shielding portion 400, that is, the first light shielding portion 300 is arranged at the periphery of the second light shielding portion 400, and the first light shielding portion 300 is arranged around the second light shielding portion 400. The first light shielding portion 300 is arranged to avoid the gate 202, source 203, and drain 204 of the thin film transistor 200.

[0048] In this example, see Figure 2 In the top view on the substrate 101, the first light shielding portion 300 and the second light shielding portion 400 are spaced apart, and the distance between the first light shielding portion 300 and the second light shielding portion 400 is 1 micrometer to 20 micrometers.

[0049] In this embodiment, the gate 202 , the source 203 , and the drain 204 of the thin film transistor 200 extend to the outside of the thin film transistor 200 for connecting to a power line (not shown) of the array substrate.

[0050] In this embodiment, the array substrate includes a plurality of second light-shielding portions 400, which are arranged on the substrate 101, and the projection of the active layer 201 on the second light-shielding portion 400 is located within the second light-shielding portion 400, that is, the active layer 201 is completely blocked by the second light-shielding portion 400, and the light from below the second light-shielding portion 400 cannot penetrate the second light-shielding portion 400, thereby preventing the active layer 201 from being directly irradiated by the light from the direction of the substrate 101.

[0051] In this embodiment, by making the projection of the first light-shielding portion 300 on the second light-shielding portion 400 not overlap with the second light-shielding portion 400, the first light-shielding portion 300 can have a larger space, thereby increasing the thickness S of the first light-shielding portion. When the thickness S of the first light-shielding portion increases, more light can be filtered to weaken the intensity of the light, thereby further reducing the light irradiating the active layer 201.

[0052] In the array substrate of this application, please refer to Figure 3 The array substrate includes a plurality of second light shielding portions 400, the second light shielding portions 400 are arranged on the substrate 101, the projection of the active layer 201 on the second light shielding portions 400 is located within the second light shielding portions 400, and the projection of the first light shielding portion 300 on the second light shielding portions 400 overlaps with the second light shielding portions 400.

[0053] In this embodiment, the projection of the first light shielding portion 300 on the second light shielding portion 400 may partially overlap with the second light shielding portion 400, that is, the first light shielding portion 300 is located on the boundary line of the second light shielding portion 400. Through the above arrangement, the relationship between the thickness S of the first light shielding portion and the aperture ratio can be balanced to achieve a better light shielding effect and a higher aperture ratio.

[0054] In this example, see Figure 3 , the projection of the first light shielding portion 300 on the second light shielding portion 400 overlaps with the second light shielding portion 400, that is, the projection of the first light shielding portion 300 is located inside the second light shielding portion 400. Through the above arrangement, this embodiment can reduce the outer dimensions of the first light shielding portion 300 and reduce the influence of the first light shielding portion 300 on the aperture ratio, thereby increasing the effective light emitting area of ​​the display panel, that is, increasing the aperture ratio of the display panel.

[0055] In the array substrate of the present application, Figure 3 On the basis of this, the second end of the first light shielding portion 300 can be connected to the second light shielding portion 400.

[0056] In this embodiment, the projection of the first light shielding portion 300 on the second light shielding portion 400 overlaps with the second light shielding portion 400, and the second end of the first light shielding portion 300 is connected to the second light shielding portion 400. Through the above arrangement, the second end of the first light shielding portion 300 can contact the second light shielding portion 400, thereby eliminating the gap between the two, preventing light from being incident on the active layer 201 of the thin film transistor 200 from the gap between the two, thereby improving the light shielding effect of the first light shielding portion 300.

[0057] In the array substrate of this application, please refer to Figure 2 and Figure 3, the first light shielding portion 300 includes a first sub-light shielding portion 301, a second sub-light shielding portion 302, and a third sub-light shielding portion 303 which are separately arranged. In the top view of the array substrate, the first sub-light shielding portion 301, the second sub-light shielding portion 302, and the third sub-light shielding portion 303 are spaced apart from the gate 202, the source 203, and the drain 204 of the thin film transistor 200;

[0058] Among them, the first sub-light-shielding portion 301 and the second sub-light-shielding portion 302 are located on the same side of the line connecting the source 203 and the drain 204 of the thin film transistor 200, and the third sub-light-shielding portion 303 is located on the other side of the line connecting the source 203 and the drain 204, and the first sub-light-shielding portion 301 and the second sub-light-shielding portion 302 are arranged on both sides of the gate 202 of the thin film transistor 200.

[0059] In this embodiment, the gate 202 extends to the outside of the thin film transistor 200 and is used to connect to a power line on the array substrate, such as a scan line.

[0060] In this embodiment, the source electrode 203 extends to the outside of the thin film transistor 200 and is used to connect to a power line, such as a signal line, on the array substrate.

[0061] In this embodiment, the drain electrode 204 extends to the outside of the thin film transistor 200 and is used to connect to a power line on the array substrate, such as an electrode wiring of a light emitting unit.

[0062] In this example, see Figure 2 and Figure 3 The first light shielding portion 300 includes a first sub-light shielding portion 301, a second sub-light shielding portion 302, and a third sub-light shielding portion 303, which are separately arranged. In the top view of the array substrate, the first sub-light shielding portion 301 and the second sub-light shielding portion 302 are arranged on the same side of the line connecting the source 203 and the drain 204, and the first sub-light shielding portion 301 and the second sub-light shielding portion 302 are separated by the gate 202. Through the above arrangement, the first light shielding portion 300 can avoid the gate 202, the source 203, the drain 204 and the power lines connected thereto, so as not to affect the structure of the array substrate.

[0063] In this example, see Figure 2 and Figure 3, in the top view of the array substrate, the first light shielding portion 300 is spaced from the thin film transistor 200, and the spacing distance between the first light shielding portion 300 and the thin film transistor 200 can be 1 micron to 20 microns, for example, the spacing distance between the first light shielding portion 300 and the thin film transistor 200 can be 1 micron to 2 microns. Specifically, in the top view of the array substrate, the spacing distance between the first sub-light shielding portion 301 and the source 203 and the gate 202 in any direction is at least 1 micron; the spacing distance between the second sub-light shielding portion 302 and the gate 202 and the drain 204 in any direction is at least 1 micron; the spacing distance between the third sub-light shielding portion 303 and the gate 202 and the second light shielding portion 400 is at least 1 micron.

[0064] In the array substrate of this application, please refer to Figure 2 and Figure 3 , the thickness S2 of the first sub-light-shielding portion 301 and the second sub-light-shielding portion is greater than the thickness S3 of the third sub-light-shielding portion.

[0065] In this embodiment, the thickness S1 of the first sub-light shielding portion refers to the horizontal distance between the inner side wall and the outer side wall of the first sub-light shielding portion 301. The thickness S2 of the second sub-light shielding portion refers to the horizontal distance between the inner side wall and the outer side wall of the second sub-light shielding portion 302. The thickness S3 of the third sub-light shielding portion refers to the horizontal distance between the inner side wall and the outer side wall of the third sub-light shielding portion 303. Among them, the thickness S1 of the first sub-light shielding portion, the thickness S2 of the second sub-light shielding portion, and the thickness S3 of the third sub-light shielding portion gradually increase in the direction away from the substrate 101. Through the above arrangement, at positions with different thicknesses, the reflection and refraction angles of the light are different, thereby further diverging the light, reducing the light passing through the first light shielding portion 300, and reducing the light irradiated on the active layer 201 of the thin film transistor 200.

[0066] In this example, see Figure 2 and Figure 3 , the thickness S1 of the first sub-light-shielding portion is greater than the thickness S3 of the third sub-light-shielding portion, and the thickness S2 of the second sub-light-shielding portion is greater than the thickness S3 of the third sub-light-shielding portion.

[0067] In this embodiment, the thickness S1 of the first sub-light-shielding portion may range from 1.5 micrometers to 10 micrometers, the thickness S2 of the second sub-light-shielding portion may range from 1.5 micrometers to 10 micrometers, and the thickness S3 of the third sub-light-shielding portion may range from 1.5 micrometers to 10 micrometers.

[0068] Through the above arrangement, this embodiment can further enhance the shading effect of the first sub-shading portion 301 and the second sub-shading portion 302 , thereby compensating for the weakening of the shading effect caused by the first sub-shading portion 301 and the second sub-shading portion 302 being separated by the gate 202 .

[0069] In the array substrate of the present application, the material of the first light shielding portion 300 is the same as the material of the planar layer 103 .

[0070] In this embodiment, the material of the first light shielding portion 300 and the material of the planar layer 103 may be the same, and the material of the first light shielding portion 300 may be organic photoresist, polyimide, or the like.

[0071] In this embodiment, the material of the first light shielding portion 300 may be different from the material of the planar layer 103. The first light shielding portion 300 may be a material doped with a light absorbing or light blocking material, for example, black light absorbing particles may be doped in the first light shielding portion 300. Through the above configuration, the first light shielding portion 300 can further absorb light, reduce the light passing through the first light shielding portion 300, and reduce the light irradiated to the active layer 201 on the thin film transistor 200.

[0072] In this embodiment, by setting the first light shielding portion 300 and the planar layer 103 to be made of the same material, the first light shielding portion 300 and the planar layer 103 can be manufactured in the same process, thereby simplifying the manufacturing process.

[0073] In the array substrate of the present application, the refractive index of the first light shielding portion 300 is different from the refractive index of the insulating layer 102 .

[0074] In this embodiment, the refractive index of the first light shielding portion 300 is different from the refractive index of the insulating layer 102. Specifically, the refractive index of the first light shielding portion 300 may be greater than the refractive index of the insulating layer 102. When the refractive index of the first light shielding portion 300 is greater than the refractive index of the insulating layer 102, the material of the first light shielding portion 300 may be organic photoresist, polyimide, etc., and at this time, the material of the insulating layer 102 may be silicon oxide, etc. Through the above configuration, when the light outside the thin film transistor 200 is irradiated to the outer wall of the first light shielding portion 300, the light is diffusely reflected and refracted, and part of the light is refracted into the first light shielding portion 300. Since the refractive index of the first light shielding portion 300 is greater than the refractive index of the insulating layer 102, on the inner wall of the first light shielding portion 300, part of the light with an incident angle greater than the critical angle is totally reflected, thereby reducing the transmitted light and reducing the light irradiated to the active layer 201 of the thin film transistor 200.

[0075] In this embodiment, the refractive index of the first light shielding portion 300 may be smaller than the refractive index of the insulating layer 102. With the above arrangement, when light from outside the thin film transistor 200 irradiates the outer wall of the first light shielding portion 300, part of the light is totally reflected at the outer wall of the first light shielding portion 300 because the refractive index of the first light shielding portion 300 is smaller than the refractive index of the insulating layer 102, thereby reducing the light that passes through the first light shielding portion 300 and reducing the light that irradiates the active layer 201 of the thin film transistor 200.

[0076] In this embodiment, by setting the refractive index of the first light-shielding portion 300 and the refractive index of the insulating layer 102 to be different, the light can be refracted at the critical surface between the first light-shielding portion 300 and the insulating layer 102, thereby changing the propagation path of the light, thereby weakening the intensity of the light in the same direction, and further reducing the light reaching the active layer 201.

[0077] See also 4A to 4F The present application also provides a method for manufacturing an array substrate, the method for manufacturing an array substrate comprising:

[0078] Providing a substrate 101;

[0079] Forming a plurality of insulating layers 102 on the substrate 101, and forming a first light shielding groove 310 on the plurality of insulating layers 102;

[0080] A planar layer 103 is formed on the multiple insulating layers 102 , and the planar layer 103 fills the first light shielding portion groove 310 to form the first light shielding portion 300 .

[0081] In this embodiment, the method of forming a plurality of insulating layers 102 on the substrate 101 and forming the first light shielding portion groove 310 on the plurality of insulating layers 102 includes:

[0082] See also Figure 4A , forming a second light shielding portion 400 on the substrate 101 ; and forming a first insulating layer 1021 on the second light shielding portion 400 .

[0083] See also Figure 4B , an active layer 201 is formed on the first insulating layer 1021 , and then a gate insulating layer (not shown in the figure) is formed, and then a gate 202 is formed.

[0084] See also Figure 4C, a second insulating layer 1022 is formed on the gate 202; via holes of the source and drain 204 are formed on the second insulating layer 1022, and a first light-shielding portion groove 310 is formed on the second insulating layer 1022, the first light-shielding portion groove 310 penetrates the second insulating layer 1022, and the first light-shielding portion groove 310 completely or partially penetrates the first insulating layer 1021.

[0085] See also Figure 4D , forming source and drain electrodes 204 in the source and drain electrode 204 via holes.

[0086] See also Figure 4E , a third insulating layer 1023 is formed on the source and drain electrodes 204; a via hole is formed at the third insulating layer 1023 corresponding to the first light shielding portion groove 310, so that the via hole of the third insulating layer 1023 is connected with the first light shielding portion groove 310. In this embodiment, the roughness of the inner surface of the via hole formed on the third insulating layer 1023 is different from the roughness of the first light shielding portion groove 310 formed on the second insulating layer 1022. Through the above arrangement, the reflection and refraction angles of the light at different thicknesses of the first light shielding portion 300 are further made different, thereby reducing the intensity of the light in the same direction, and reducing the light irradiated on the active layer 201 of the thin film transistor 200.

[0087] See also Figure 4F , a flat layer 103 is formed on the multiple layers of the insulating layer 102 , and the flat layer 103 fills the first light shielding portion groove 310 to form the first light shielding portion 300 .

[0088] In this embodiment, the steps after forming the flat layer 103 also include forming an anode (not shown in the figure) and the processes after forming the anode. Other processes are conventional processes and are not limited in this application. The material of the anode includes transparent conductive materials such as ITO.

[0089] In this embodiment, the method of forming the second light shielding portion 400 and the active layer 201 may be physical vapor deposition (PVD), or may be other conventional process methods in the art, and this application does not impose any limitation thereto.

[0090] In this embodiment, the method for forming the multilayer insulating layer 102 may be chemical vapor deposition (CVD) or other conventional process methods in the art, which is not limited in this application. The material for forming the insulating layer 102 may be any one of silicon oxide, silicon nitride, and silicon nitride or a combination thereof.

[0091] In this embodiment, the thin film transistor 200 is formed by a conventional process in the art, including photoresist coating, exposure and development, etching, etc., and this application does not impose any limitation on this.

[0092] In this embodiment, the method of forming the first light shielding portion groove 310 includes etching, and the inner surface of the first light shielding portion groove 310 is a rough surface after the etching is completed.

[0093] In this embodiment, after forming the via hole of the third insulating layer 1023, the material of the flat layer 103 is used to fill the first light shielding portion groove 310, and the filling method includes chemical vapor deposition. After the filling is completed, the material of the flat layer 103 fills the first light shielding portion groove 310 to form the first light shielding portion 300. Because the first light shielding portion 300 is in close contact with the first light shielding portion groove 310, the surface of the first light shielding portion is a rough surface. After the filling is completed, the flat layer 103 is continued to be manufactured so that the flat layer 103 is connected to the first light shielding portion 300. The material forming the first light shielding portion 300 is the same as the material of the flat layer 103. Through the above settings, the manufacturing process of the first light shielding portion 300 can be simplified.

[0094] In this embodiment, the material forming the planar layer 103 includes organic photoresist, polyimide, etc.

[0095] The present application also provides a display panel, which includes a display body and the above-mentioned array substrate, and the array substrate and the display body are combined into one body.

[0096] The present application also provides a terminal, which includes a terminal body and the above-mentioned display panel, and the display panel and the terminal body are combined into one.

[0097] In this embodiment, the terminal may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.

[0098] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0099] The above is a detailed introduction to a display panel and a mobile terminal provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A multi-layer insulation layer is arranged on the substrate, and the insulation layer is provided with a first light shielding groove; A plurality of thin film transistors are disposed in the insulating layer; A planar layer, disposed on the insulating layer, wherein the planar layer fills the first light shielding portion groove to form a first light shielding portion; Among them, multiple first light-shielding portions are arranged on the periphery of multiple thin-film transistors, the first light-shielding portions penetrate the insulating layer, and the first end of the first light-shielding portion is connected to the flat layer, and the second end of the first light-shielding portion extends at least to the active layer of the thin-film transistor; the first light-shielding portion includes a rough surface, and the first light-shielding portion is connected to multiple layers of the insulating layer through the rough surface.

2. The array substrate according to claim 1, characterized in that: The array substrate includes a plurality of second light shielding portions, which are arranged on the substrate, the projection of the active layer on the second light shielding portions is located within the second light shielding portions, and the projection of the first light shielding portions on the second light shielding portions does not overlap with the second light shielding portions.

3. The array substrate according to claim 1, characterized in that: The array substrate includes a plurality of second light shielding portions, which are arranged on the substrate, the projection of the active layer on the second light shielding portions is located within the second light shielding portions, and the projection of the first light shielding portions on the second light shielding portions overlaps with the second light shielding portions.

4. The array substrate according to claim 3, characterized in that: The second end of the first light shielding portion is connected to the second light shielding portion.

5. The array substrate according to any one of claims 2 to 4, characterized in that: The first light shielding portion includes a first sub-light shielding portion, a second sub-light shielding portion, and a third sub-light shielding portion which are separately arranged. In a top view of the array substrate, the first sub-light shielding portion, the second sub-light shielding portion, and the third sub-light shielding portion are arranged spaced apart from the gate, the source, and the drain of the thin film transistor; Among them, the first sub-light-shielding portion and the second sub-light-shielding portion are located on the same side of the source and drain connection of the thin film transistor, and the third sub-light-shielding portion is located on the other side of the source and drain connection, and the first sub-light-shielding portion and the second sub-light-shielding portion are arranged on both sides of the gate of the thin film transistor.

6. The array substrate according to claim 5, characterized in that: The thickness of the first sub-light-shielding portion and the second sub-light-shielding portion is greater than the thickness of the third sub-light-shielding portion.

7. The array substrate according to claim 1, characterized in that: The material of the first light shielding portion is the same as that of the planar layer.

8. The array substrate according to claim 1, characterized in that: The first light shielding portion has a refractive index different from that of the insulating layer.

9. A method for manufacturing an array substrate, characterized in that: include: providing a substrate; Forming multiple insulating layers and multiple thin film transistors on the substrate, forming a first light shielding groove on the multiple insulating layers, wherein the first light shielding groove is arranged at the periphery of the multiple thin film transistors and penetrates the insulating layer; A flat layer is formed on the multiple insulating layers, the flat layer fills the first light-shielding portion groove to form a first light-shielding portion, a first end of the first light-shielding portion is connected to the flat layer, and a second end of the first light-shielding portion extends at least to the active layer of the thin film transistor, the first light-shielding portion includes a rough surface, and the first light-shielding portion is connected to the multiple insulating layers through the rough surface.

10. A display panel, characterized in that: It comprises a display body and an array substrate as claimed in any one of claims 1 to 8, wherein the array substrate and the display body are combined into one body.

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