A chip packaging deep hole interconnection hole filling structure and manufacturing method thereof

Abstract

The present invention discloses a method for manufacturing a hole-filling structure for deep hole interconnection of chip packaging, which comprises depositing a seed layer on the bottom surface of a substrate and extending the seed layer to cover part of the inner wall of a through hole, using a first electroplating process to seal the bottom of the through hole with electroplated metal, and then using a second electroplating process to fill the through hole with the electroplated metal in a bottom-up growth manner. The present invention can be used for through-hole electroplating applications in 2.5D or 3D packaging, can realize interconnection with a high aspect ratio, breaks through the depth-to-diameter ratio range of conventional through-hole electroplating, reaches the level of a blind hole, and has a fast electroplating rate and low equipment requirements.

Description

Technical Field

[0001] This invention belongs to the technical field of chip packaging, specifically relating to a hole-filling structure for deep via interconnection in chip packaging and its fabrication method. Background Technology

[0002] In the field of 3D packaging, through-hole structures on substrates or plates are physical interconnects that enable the transmission of electrical signals on both sides of the substrate. The filling of the metal inside the holes is basically achieved by electroplating, and the in-hole electroplating process is the core of this technology.

[0003] Currently, to achieve 3D interconnects, through-hole plating and blind-hole plating can be used. Through-hole plating requires first creating a bridge structure within the hole, demanding high-quality plating solutions, resulting in long plating times and high costs. Furthermore, due to its technical limitations, the achievable hole depth-to-diameter ratio is generally low, typically not exceeding 4:1. Blind-hole plating is mainly used for blind holes with high aspect ratios, but due to the hole depth, it places high demands on PVD, plating solutions, and plating machines. The average plating rate is usually below 1 ASD, leading to long plating times and high costs. It also requires substrate thinning, making the process complex and costly. These issues hinder the widespread adoption of low-cost 3D packaging. Summary of the Invention

[0004] This invention addresses the problems existing in the prior art by providing a hole-filling structure for deep via interconnection in chip packaging and its fabrication method.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] A method for fabricating a via-filling structure for deep via interconnection in chip packaging includes the following steps:

[0007] 1) A substrate is provided, the substrate having opposing top and bottom surfaces, and a through hole is formed on the substrate through the top and bottom surfaces;

[0008] 2) Deposit diffusion barrier layers on the top and bottom surfaces of the substrate and cover the inner walls of the vias with the diffusion barrier layers;

[0009] 3) A seed layer is deposited on the bottom surface, the seed layer extending from the bottom surface to the inner wall of the portion covering the through hole;

[0010] 4) The bottom of the through hole is sealed by electroplating metal through a first electroplating process;

[0011] 5) The through-hole is filled by a second electroplating process, in which the electroplated metal grows from the bottom up.

[0012] 6) Use a grinding process (such as CMP) to grind down the electroplated metal protruding from the top surface;

[0013] 7) Perform electroplating on the top surface.

[0014] Optionally, the diffusion barrier layer is an inert metal such as Ti, Ta, Cr, W, In, or an oxide or nitride of the metal, with a thickness of 10 nm to 10 μm, more preferably 20 to 100 nm.

[0015] Optionally, in step 3), the first electroplating process uses DC electroplating or AC electroplating with a current density of 1 to 15 ASD.

[0016] Optionally, in step 4), the second electroplating process adopts DC electroplating with a current density of 5 to 20 ASD and a flow rate of 1 to 30 L / min. It can be done by horizontal cup rotation or vertical wall mounting.

[0017] Optionally, the substrate material includes Si, glass, ceramic, SiC, GaN, PP, ABF, and FR4.

[0018] Optionally, the diameter of the through hole is 1 to 1000 μm, and the depth-to-diameter ratio is 3:1 to 100:1.

[0019] Furthermore, the diameter of the through hole is 10-200 μm, and the depth-to-diameter ratio is 10:1 to 30:1.

[0020] Optionally, the electroplated metal includes elemental metals or alloys of Cu, Ni, Au, Ag, and In.

[0021] Optionally, the through hole is a straight hole, an X-shaped hole, or a tapered hole.

[0022] The via-filling structure for deep via interconnection in chip packaging prepared by the above-described method.

[0023] The beneficial effects of this invention are as follows:

[0024] 1) It can be used for through-hole plating applications in 2.5D or 3D packaging, enabling high aspect ratio interconnection, breaking through the depth-to-diameter ratio range of conventional through-hole plating, and reaching the level of blind holes;

[0025] 2) It has low requirements for PVD equipment, electroplating solution and electroplating equipment, and the process is highly operable;

[0026] 3) Increased the electroplating rate;

[0027] 4) Compared with conventional TSV and other technical solutions, the overall cost is lower and it is suitable for practical production applications. Attached Figure Description

[0028] Figures 1 to 7This is a schematic diagram of the structure obtained from each step of the fabrication method of the hole-filling structure for deep via interconnection in chip packaging in Example 1.

[0029] Figure 8 This is a schematic diagram of the shape of the through hole;

[0030] Figure 9 This is a schematic diagram of the through-hole electroplating process for Comparative Example 1.

[0031] Figure 10 This is a schematic diagram of the blind hole electroplating process in Comparative Example 2. Detailed Implementation

[0032] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.

[0033] Example 1

[0034] A method for fabricating a via-filling structure for deep via interconnects in chip packaging, referenced Figure 1 First, a substrate 1 is provided, having a top surface 1a and a bottom surface 1b opposite to each other. A through-hole 11 is formed on the substrate 1, penetrating both the top surface 1a and the bottom surface 1b. The material of the substrate 1 includes, but is not limited to, Si, glass, ceramic, SiC, GaN, PP, ABF, and FR4, and it can be a circular wafer, a rectangular substrate, or a square substrate. The through-hole 11 can be implemented using known etching methods, such as Bosch etching for Si substrates and laser-induced etching for glass. The diameter of the through-hole 11 ranges from 1 to 1000 μm, for example, it can be 10 to 200 μm.

[0035] refer to Figure 2 A diffusion barrier layer 2 is deposited on both the top surface 1a and the bottom surface 1b, covering the inner wall of the through-hole 11. The diffusion barrier layer 2 mainly serves to adhere to the substrate 1 and prevent subsequent electroplated metal from diffusing into the substrate material. It is usually achieved by PVD (physical vapor deposition) or chemical plating. The material used can be an inert metal such as Ti, Ta, Cr, W, In, or an oxide or nitride of a metal, with a thickness of, for example, 20-100 nm.

[0036] refer to Figure 3 A seed layer 3 is deposited on the bottom surface 1b, extending from the bottom surface 1b to cover a portion of the inner wall of the through-hole 11 near the bottom surface 1b. The seed layer 3 can be made of elemental metals or alloys such as Cu, Ni, Au, Ag, and In, and is implemented using a process such as PVD, similar to the subsequent metal electroplating. In this invention, the seed layer 3 only needs to cover a portion of the inner wall of the through-hole 11 because the bottom surface electroplating only requires the hole to be closed and metal growth within the hole is not required. Therefore, PVD, which has a lower filling capacity, can be used, ensuring only the coverage of the metal seed layer at the hole opening. The requirements for step coverage in the PVD equipment are not high.

[0037] refer to Figure 4 The bottom of the through hole 11 is sealed by the electroplated metal 4 through the first electroplating process. The first electroplating process is as follows: the current density is 1 to 15 ASD. Since the electric field is concentrated at the edge of the hole, the metal in the electroplating solution is reduced and deposited at the position where the seed layer 3 is located, which allows the opening to be sealed quickly. Pulsed AC electroplating or DC electroplating can be used. After a short base plating at a small ASD, electroplating at a large ASD can be performed, with an electroplating rate of up to 10 ASD or more.

[0038] refer to Figure 5 The second electroplating process involves filling the through-hole 11 with electroplated metal 4 in a bottom-up growth manner. Specifically, in the bottom-up electroplating stage, the bottom surface 1b can be covered with a fixture or organic adhesive / film, with only the edges connected to the power cathode. Since the metal in the electroplating solution, after reduction, can only be deposited in locations with a seed layer, the electroplated metal formed in the previous step serves as the seed layer, thus growing in a bottom-up manner. The current density can reach 5 ASD or even 10 ASD or higher, achieving high-speed growth. The electroplated metal 4 in both the first and second electroplating processes uses the same metal as the seed layer 3. The electroplating solution does not need to be expensive TSV electroplating solution; instead, a common RDL electroplating solution can be used. The electroplating current density can be higher than 10 ASD, even 15-20 ASD. Direct current electroplating is used, with a flow rate of 1-30 L / min, and can be performed using a horizontal cup rotation method or a vertical wall-mounted method.

[0039] refer to Figure 6 The exposed electroplated metal 4 is ground smooth using CMP (Chemical Metallurgy) so that the surface of the metal is basically consistent with the top surface 1a.

[0040] refer to Figure 7 As needed, perform conventional top surface electroplating to form electroplated layer 5.

[0041] This embodiment can achieve the filling of deep holes with a depth-to-diameter ratio of 10:1 or higher. (Reference) Figure 8 The shape of the through hole can be a straight hole, an X-shaped hole, or a tapered hole.

[0042] Comparative Example 1

[0043] refer to Figure 9 The through-hole electroplating process consists of the following steps: through-hole etching – double-sided barrier layer / seed layer deposition – bridge electroplating – fill electroplating – through-hole electroplating completion.

[0044] Bridge plating can utilize RDL plating solutions, allowing for the use of higher plating rates, such as 1–5 ASD, to achieve closure at the narrowest point of the X-shaped hole. After closure, two relatively deep blind holes are formed, requiring a filling plating method. This deep-hole plating method demands high capabilities, mass transfer, and directional growth. The plating current density is typically below 1 ASD. Due to the low current density, the plating time is long. As a result of these technical and cost considerations, the achievable depth-to-diameter ratio generally does not exceed 4:1.

[0045] Compared with Comparative Example 1, the process of this invention has the following advantages: the hole depth-to-diameter ratio that this invention can achieve exceeds 10:1, far exceeding that of Comparative Example 1; the requirements for the electroplating solution of this invention are lower, while those of the comparative example are higher; the electroplating rate of this invention is higher than that of Comparative Example 1. This invention only requires the use of RDL electroplating solution and a non-blind hole electroplating method, which can greatly improve the electroplating efficiency.

[0046] Comparative Example 2

[0047] refer to Figure 10 The blind via electroplating process consists of the following steps: blind via etching, barrier layer / seed layer deposition, conformal electroplating, filling electroplating, completion of blind via electroplating, substrate thinning, and reverse electroplating.

[0048] Blind via plating can achieve high aspect ratio metal filling, but because the barrier / seed layer deposition needs to cover the inner wall of the blind via, and for deeper vias, high-step PVD and plating equipment are required. Since blind vias require a fill-in plating method, this deep-via plating process demands high capabilities, mass transfer, and directional growth. Currently, the average plating rate of commercially available plating solutions is typically below 1 ASD. Using plating solutions with rates higher than 1 ASD can lead to voids, resulting in longer plating times and higher costs. Furthermore, a substrate thinning step is required, complicating the process and further increasing costs.

[0049] The process of the present invention has the following advantages compared with Comparative Example 2: The present invention has lower requirements for PVD equipment and electroplating equipment, and lower requirements for electroplating solution, and simplifies the process compared with Comparative Example 2.

[0050] The above embodiments are only used to further illustrate the via filling structure and manufacturing method of deep via interconnect for chip packaging according to the present invention. However, the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a hole-filling structure for deep hole interconnection of chip packaging, characterized in that: The following steps are involved: 1) Providing a substrate, wherein the substrate has a top surface and a bottom surface opposite to each other, and forming a through hole penetrating the top surface and the bottom surface on the substrate; the through hole has a diameter of 10-200 um and a depth-to-diameter ratio of 10:1-30:1; 2) depositing a diffusion barrier layer on the top and bottom surfaces of the substrate and making the diffusion barrier layer cover the inner wall of the through hole; the thickness of the diffusion barrier layer is 20-100 nm; 3) depositing a seed layer on the bottom surface of the substrate, wherein the seed layer extends from the bottom surface to cover a portion of the inner wall of the through hole; 4) Using a first electroplating process to seal the bottom of the through hole with electroplated metal; the first electroplating process uses direct current plating or alternating current plating with a current density of 1-15 ASD; 5) Filling the through hole with electroplated metal in a bottom-up growth manner through a second electroplating process; the second electroplating process adopts a direct current electroplating method, including a horizontal cup rotation method or a vertical wall hanging method, with a current density of 10-20ASD and a flow rate of 1-30L / min; the electroplated metals of the first electroplating process and the second electroplating process both adopt the same metal as the seed layer; 6) Use grinding process to grind the electroplated metal on the protruding top surface; 7) Perform top surface electroplating.

2. The method according to claim 1, characterized in that: The diffusion barrier layer is Ti, Ta, Cr, W, In or an oxide or nitride thereof.

3. The method according to claim 1, characterized in that: Materials of the substrate include Si, glass, ceramic, SiC, GaN, PP, ABF and FR4.

4. The method according to claim 1, characterized in that: The electroplating metal includes single metal or alloy of Cu, Ni, Au, Ag, In.

5. The method according to claim 1, characterized in that: The through hole is a straight hole, an X-shaped hole or a tapered hole.

6. A chip packaging deep hole interconnect filling structure prepared by the manufacturing method according to any one of claims 1 to 5.

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