Semiconductor structure

Abstract

The present invention relates to a semiconductor structure, which has a first region, a second region and a third region, wherein the second region is located between the first region and the third region, and the semiconductor structure comprises: a substrate; a shallow trench isolation structure, which is located in the substrate and isolates the substrate into a plurality of active regions, wherein the active region of the first region is used to form a semiconductor device; a dielectric layer, which is located on the substrate; a through-hole structure, which is located in the third region and penetrates the dielectric layer and the substrate; a stress buffer structure, which is located in the second region and comprises a first buffer doping region, wherein the first buffer doping region is located in the active region and is formed by doping the active region with a first buffer impurity, wherein the atomic radius of the first buffer impurity is smaller than the atomic radius of the substrate material. The present application can buffer the expansion stress between the substrate and the connected structure during the manufacturing process of the through-hole structure, thereby effectively protecting the semiconductor device and structure of the first region.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure. Background Art

[0002] Through silicon via (TSV) technology used in three-dimensional packaging can effectively shorten the length of interconnect lines, reduce signal transmission delay and loss, increase signal speed and bandwidth, reduce power consumption and reduce packaging volume, etc. It is one of the effective ways to achieve high-performance and high-reliability semiconductor devices.

[0003] The current TSV manufacturing process usually includes etching a through hole that penetrates the substrate and the dielectric layer on the substrate, and filling the through hole with electroplated copper with good conductivity. After electroplating copper, annealing is usually performed to make the size of the electroplated copper more uniform, thereby reducing its resistivity and improving its anti-electromigration ability.

[0004] During the annealing process, the electroplated copper grains will grow and become larger. However, the thermal expansion coefficients of copper, the substrate, and the dielectric layer are significantly different and mismatched. Therefore, thermal stress will be generated during the TSV manufacturing process. Thermal stress will cause cracks at the interface between the dielectric layer and the silicon substrate, thus affecting the stability of the semiconductor structure. Summary of the invention

[0005] Based on this, it is necessary to provide a semiconductor structure that can buffer thermal expansion stress.

[0006] A semiconductor structure comprises a first region, a second region and a third region, wherein the second region is located between the first region and the third region, and the semiconductor structure comprises:

[0007] substrate;

[0008] A shallow trench isolation structure is located in the substrate and isolates the substrate into a plurality of active regions, wherein the active region of the first region is used to form a semiconductor device;

[0009] A dielectric layer, located on the substrate;

[0010] a through-hole structure, located in the third region and penetrating the dielectric layer and the substrate;

[0011] The stress buffer structure is located in the second area and includes a first buffer doping area. The first buffer doping area is located in the active area and is formed by doping the active area with a first buffer impurity. The atomic radius of the first buffer impurity is smaller than the atomic radius of the substrate material.

[0012] In one embodiment, the substrate material includes silicon, and the first buffer impurities include carbon and / or boron.

[0013] In one embodiment, the first buffer doped region is connected to the through-hole structure.

[0014] In one embodiment, the first buffer doped region surrounds the via structure.

[0015] In one of the embodiments, the stress buffer structure further includes at least one buffer window structure, which is located in the dielectric layer and has a distance between it and the through-hole structure, including a buffer through-hole structure, wherein the buffer through-hole of the buffer through-hole structure is filled with a metal plug.

[0016] In one of the embodiments, the buffer window structure is grounded.

[0017] In one embodiment, the semiconductor structure further includes a grounding metal layer structure, and the first end of the buffer window structure is connected to the grounding metal layer structure.

[0018] In one of the embodiments, a second end of at least one of the buffer window structures is connected to the active region.

[0019] In one of the embodiments, a second end of at least one of the buffer window structures is connected to the first buffer doped region.

[0020] In one of the embodiments, the buffer window structure further includes at least one buffer metal layer structure and an interconnection via structure connecting the buffer metal layer structure, wherein the buffer via structure connects the metal layer structure.

[0021] In one embodiment, the buffer window structure surrounds the through hole structure.

[0022] In one embodiment, the stress buffer structure further includes a second buffer doping region, which is located in the dielectric layer and formed by doping the dielectric layer with second buffer impurities. The dielectric layer is doped with the second buffer impurities to form a porous dielectric material.

[0023] In one embodiment, the dielectric constant of the porous dielectric material is lower than the dielectric constant of the dielectric layer material.

[0024] In one embodiment, the dielectric layer material includes silicon dioxide, and the second buffer impurities include any one or more of boron, phosphorus, boron phosphorus and nitrogen.

[0025] In one embodiment, the second buffer doped region surrounds the through-hole structure.

[0026] In one embodiment, the second buffer doped region completely covers the dielectric layer of the second region.

[0027] In one embodiment, the method for forming the first buffer doping region includes:

[0028] Providing the substrate, and forming the shallow trench isolation structure in the substrate;

[0029] Doping the active regions of the second region and the third region with first buffer impurities to form a first buffer doping initial region;

[0030] When forming the through hole of the through hole structure in the substrate and the dielectric layer located in the third region, the first buffer doped initial region is penetrated by the through hole of the through hole structure to form a first buffer doped region surrounding and connecting the through hole structure.

[0031] The above-mentioned semiconductor structure also includes a stress buffer structure. The atomic radius of the first buffer impurity is smaller than the atomic radius of the substrate material. Therefore, when the atoms of the first buffer impurity are in the replacement position of the substrate material, the lattice will shrink. Local strain will appear around each atom of the first buffer impurity. The atoms of each first buffer impurity cause the local strain to be superimposed. When the doping concentration of the first buffer impurity reaches a certain height, a relatively large overall strain will be generated in the entire first buffer doping area. Under its influence, the undoped area tends to be stretched, that is, subjected to tensile stress. In this way, the expansion stress between the substrate and the connecting structure during the manufacturing process of the through-hole structure can be buffered, thereby effectively protecting the semiconductor devices and structures in the first area. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment;

[0034] Figure 2 Schematic diagram of silicon lattice structure and silicon lattice structure after carbon doping;

[0035] Figure 3 A schematic diagram of a planar structure of a connecting structure and a first buffer doping region provided in an embodiment;

[0036] Figure 4 A schematic diagram of a planar structure of a connecting structure and a first buffer doping region provided in another embodiment;

[0037] Figure 5is a schematic cross-sectional view of a semiconductor structure provided in another embodiment;

[0038] Figure 6 is a cross-sectional schematic diagram of a semiconductor structure provided in yet another embodiment;

[0039] Figure 7 FIG. 4 is a cross-sectional schematic diagram of a semiconductor structure provided in yet another embodiment. DETAILED DESCRIPTION

[0040] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0042] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, etc., these elements, components, regions, layers, etc. should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, a first buffer doping region may be referred to as a second buffer doping region, and similarly, a second buffer doping region may be referred to as a first buffer doping region.

[0043] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0044] When used herein, the singular forms of "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0045] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be intervening layers. In addition, it is also understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or there may be one or more intervening layers. In addition, the same reference numerals always represent the same elements.

[0046] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.

[0047] In one embodiment, see Figure 1 , a semiconductor structure is provided, comprising a first region A1, a second region A2 and a third region A3. The second region A2 is located between the first region A1 and the third region A3.

[0048] The semiconductor structure includes: a substrate 100 , a shallow trench isolation structure 200 , a dielectric layer 300 , a through-hole structure 400 and a stress buffer structure 500 .

[0049] The substrate 100 is a semiconductor substrate, and its material may include but is not limited to silicon.

[0050] The shallow trench isolation structure 200 is located in the substrate 100 and isolates the substrate 100 into a plurality of active regions. The active region of the first region A1 is used to form a semiconductor device (eg, a transistor, etc.).

[0051] The dielectric layer 300 is located on the substrate 100, and its material can be an insulating material such as silicon dioxide. Specifically, the dielectric layer 300 can include multiple film layers. The materials of each film layer can be the same or different. Of course, the dielectric layer 300 can also include one film layer, and the present application has no limitation on this.

[0052] The through hole structure 400 is located in the third area A3 and penetrates the dielectric layer 300 and the substrate 100 .

[0053] As an example, the via structure 400 may include an adhesion layer, a barrier layer, a seed layer, and a metal conductive structure. At this time, the method for forming the via structure 400 may include:

[0054] Step S110, forming a through hole in the substrate 100 and the dielectric layer 300 located in the third area A3;

[0055] Step S120, forming an adhesion layer, a barrier layer and a seed layer in sequence in the through hole;

[0056] Step S130, forming a metal structure on the surface of the seed layer.

[0057] In step S110 , deep reactive ion etching (DRIE) or laser etching may be used to etch blind holes in the substrate 100 and the dielectric layer 300 .

[0058] In step S120, the adhesion layer may be an insulating film layer such as silicon dioxide, the barrier layer may be tantalum or tantalum nitride, etc. The seed layer is a seed film layer of a metal structure, which may be conducive to forming a metal structure of good quality.

[0059] In step S130, the material of the metal structure may be a metal with good electrical conductivity such as copper, and may be formed on the surface of the seed layer by electroplating or the like.

[0060] After the metal structure is formed, it can be annealed to make the grains of the metal structure (such as copper formed by electroplating) larger and more uniform in size, thereby reducing its resistivity and improving its anti-electromigration capability.

[0061] The thermal expansion coefficients of the semiconductor substrate 100, the insulating dielectric layer 300, and the metal structure of the through-hole structure 400 are significantly different. For example, when the material of the substrate 100 is silicon, the material of the dielectric layer 300 is silicon dioxide, and the material of the metal structure of the through-hole structure 400 is copper, the thermal expansion coefficient of silicon is 2.6×10 -6 / ℃, the thermal expansion coefficient of silicon dioxide is 0.4×10 -6 / ℃, the thermal expansion coefficient of copper is 16.5×10 -6 / ℃.

[0062] Since the thermal expansion coefficients of the metal structure of the through-hole structure 400 , the semiconductor substrate 100 , and the insulating dielectric layer 300 are significantly different, a large thermal stress is generated during the manufacturing process of the through-hole structure 400 .

[0063] Meanwhile, in this embodiment, the semiconductor structure further includes a stress buffer structure 500 .

[0064] The stress buffer structure 500 is located in the second area A2 . The second area A2 is located between the first area A1 and the third area A3 . Therefore, the stress buffer structure 500 is located between the semiconductor device formed in the first area A1 and the through-hole structure 400 in the third area A3 .

[0065] The stress buffer structure 500 includes a first buffer doping region 510. The first buffer doping region 510 is located in the active region and is formed by doping the active region with a first buffer impurity. The atomic radius of the first buffer impurity is smaller than the atomic radius of the substrate 100 material.

[0066] As an example, a method for forming the first buffer doping region 510 may include:

[0067] Step S210, providing a substrate 100, and forming a shallow trench isolation structure 200 in the substrate 100, wherein the shallow trench isolation structure 200 isolates the substrate 100 into a plurality of active regions;

[0068] In step S220 , the active region of the second region A2 is doped with the first buffer impurities to form a first buffer doping region 510 doped with the first buffer impurities.

[0069] Specifically, the first buffer impurities may be doped into the active region of the second region A2 by ion implantation or diffusion doping.

[0070] When the first buffer impurity is introduced into the active area of ​​the substrate 100 located in the second area A2, the mechanical properties of the substrate 100 here will change accordingly. The first buffer impurity may replace atoms in the substrate material lattice, and the replaced atoms of the substrate material will parasitize in the lattice, thereby generating defects. First buffer impurities of different atomic sizes will lead to different changes in mechanical properties.

[0071] When the atomic radius of the first buffer impurity is smaller than the atomic radius of the substrate 100 material, the atoms of the first buffer impurity are in the replacement position of the substrate material, which will cause the lattice to shrink. Local strain will appear around each atom of the first buffer impurity. The atoms of each first buffer impurity cause this local strain to be superimposed. When the doping concentration of the first buffer impurity reaches a certain height, a relatively large overall strain will be generated in the entire first buffer doping area 510. Under its influence, the undoped area tends to be stretched, that is, subjected to tensile stress. As a result, the expansion stress between the substrate 100 and the connecting structure 400 during the manufacturing process of the through-hole structure 400 can be buffered, thereby effectively protecting the semiconductor devices and structures of the first area A1.

[0072] In one embodiment, the material of the substrate 100 includes silicon, and the first buffer impurities include carbon and / or boron. That is, the first buffer doping region 510 is doped with carbon and / or boron. In other words, the substrate active region corresponding to the first buffer doping region 510 is doped with carbon and / or boron.

[0073] See also Figure 2 The atomic radius of carbon and boron is smaller than that of silicon atoms. Therefore, when carbon and / or boron are doped in the first buffer doping region 510, the carbon and / or boron atoms are in substitution positions, which will cause lattice contraction. Local strain will be present around each carbon and / or boron atom.

[0074] If the doping concentration reaches a certain height, the local strain is superimposed, resulting in a relatively large overall strain in the entire first buffer doping region 510. Under its influence, the undoped region tends to be stretched, that is, subjected to tensile stress. Thus, the expansion stress generated during the manufacturing process of the through-hole structure 400 can be buffered, thereby effectively protecting the semiconductor devices and structures in the first region A1.

[0075] In one embodiment, see Figure 1 The first buffer doping region 510 is connected to the through-hole structure 400 , so that the first buffer doping region 510 can effectively absorb the thermal stress between the substrate 100 and the through-hole structure 400 , thereby improving the stability of the semiconductor structure.

[0076] As an example, at this time, in the process of manufacturing the semiconductor structure, in the method for forming the first buffer doping region 510, step S220 may include:

[0077] Step S221 , doping the active regions of the second area A2 and the third area A3 with first buffer impurities to form a first buffer doping initial region.

[0078] Afterwards, when forming the via structure 400 , when forming a via in the substrate 100 and the dielectric layer 300 located in the third area A3 , the first buffer doped initial region is penetrated by the via to form the first buffer doped region 510 surrounding and connecting the via structure 400 .

[0079] At this time, a well-doped first buffer doping region 510 may be formed around the via structure 400 .

[0080] Of course, in the aforementioned method for forming the first buffer doped region 510 , step S220 may also be performed by doping the first buffer impurities only in the active region of the second region A2 , and the present application has no limitation thereto.

[0081] Alternatively, in other embodiments, the first buffer doped region 510 may not be connected to the through-hole structure 400 .

[0082] Furthermore, when the first buffer doping region 510 is connected to the through-hole structure 400 , the first buffer impurities doped in the first buffer doping region 510 are selected to be impurities that will not form a conductive region, thereby effectively preventing the transmission of electrical signals in the through-hole structure 400 from being affected.

[0083] In one embodiment, see Figure 3 as well as Figure 4 , the first buffer doping region 510 surrounds the through-hole structure 400. At this time, the first buffer doping region 510 is provided at each location of the periphery of the through-hole structure 400 to buffer the thermal stress between the substrate 100 and the through-hole structure 400, thereby making the semiconductor structure performance more stable.

[0084] At this time, the first buffer doped region 510 may be connected to the through-hole structure 400 or may not be connected to the through-hole structure 400 .

[0085] Furthermore, the present application does not limit the shape of the first buffer doping region 510. It may be in a ring shape (see Figure 4 ), or it can be a square shape (see Figure 3 ), or any other possible shape.

[0086] Of course, in other embodiments, affected by other semiconductor structures or circuit structures, the first buffer doped region 510 may also be disposed only in a partial area around the through-hole structure 400 , and the present application has no limitation thereto.

[0087] In one embodiment, see Figure 5 or Figure 6 or Figure 7The stress buffer structure 500 further includes at least one buffer window structure 520. The buffer window structure 520 is located in the dielectric layer 300. In addition, the buffer window structure 520 includes a buffer through hole structure 521. The buffer through hole of the buffer through hole structure 521 is filled with a metal plug.

[0088] The metal plug can effectively prevent the thermal stress from diffusing when a large thermal stress is generated between the dielectric layer 300 and the through-hole structure 400 during the manufacturing process of the through-hole structure 400 , thereby effectively suppressing the strain generated by the thermal stress.

[0089] At the same time, there is a distance between the buffer window structure 520 and the through-hole structure 400 , so that the buffer window structure 520 does not affect the transmission of the conductive signal in the through-hole structure 400 .

[0090] In one implementation, the buffer window structure is grounded.

[0091] In a three-dimensional integrated circuit, the via structure 400 usually appears in the form of an array. Especially in a high-density via structure 400 array, any via structure 400 will be subject to electromagnetic interference from surrounding via structures 400 or cause noise impact on surrounding components. This will not only cause transmission loss and transmission delay of the via structure 400, but also change the frequency size of surrounding components.

[0092] In this embodiment, the buffer window structure 520 is grounded, so that the buffer window structure 520 can be used for electromagnetic shielding while buffering thermal stress, thereby reducing the electrical impact of the through-hole structure 400 on surrounding components.

[0093] In one embodiment, please refer to Figure 5 The semiconductor structure further includes a grounding metal layer structure 600. The grounding metal layer structure 600 is connected to the circuit ground terminal. The first end (upper end in the figure) of the buffer window structure 520 is connected to the grounding metal layer structure 600, so that the buffer window structure 520 can be conveniently grounded.

[0094] In one embodiment, please refer to Figure 5 , a second end (lower end in the figure) of at least one buffer window structure 520 is connected to the active area.

[0095] Since the difference in thermal expansion coefficients between the semiconductor substrate 100 and the insulating dielectric layer 300 is usually relatively large, the two are also easily affected by thermal stress.

[0096] In this embodiment, the second end of the buffer window structure 520 is connected to the active region of the substrate 100 , thereby effectively suppressing the influence of thermal stress between the substrate 100 and the dielectric layer 300 .

[0097] In one embodiment, please refer to Figure 5 , a second end of at least one buffer window structure 520 is connected to the first buffer doping region 510 .

[0098] At this time, the first buffer doping region 510 and the buffer window structure 520 can continuously suppress the thermal stress around the connecting structure 400 , thereby improving the buffering capacity of the stress buffer structure 500 .

[0099] In one embodiment, see Figure 6 or Figure 7 The buffer window structure 520 further includes at least one buffer metal layer structure 522 and an interconnection via structure 523 connecting the metal layer structure 522. The buffer metal layer structure 522 is used to lead out the signal. At the same time, the interconnection via structure 523 is used to realize the electrical connection between adjacent buffer metal layer structures 522 and between the buffer metal layer structure 522 and other structures (such as the substrate 100).

[0100] The buffer through-hole structure 521 is connected to the buffer metal layer structure 522 , which can effectively increase the stress buffering range of the buffer window structure 520 .

[0101] It is understandable that, in this embodiment, only one buffer metal layer structure 522 and one interconnection through hole structure 523 connected thereto may be included, see Figure 6 , may also include a plurality of buffer metal layer structures 522 and a plurality of interconnection via structures 523, see Figure 7 .

[0102] In one embodiment, the buffer window structure 520 surrounds the through-hole structure 400 .

[0103] At this time, buffer window structures 520 are provided at various locations around the through-hole structure 400 to buffer the thermal stress between the dielectric layer 300 and the connecting structure 400 , thereby making the performance of the semiconductor structure more stable.

[0104] Of course, in other embodiments, affected by other semiconductor structures or circuit structures, the buffer window structure 520 may also be disposed only in a partial area around the through-hole structure 400 , and the present application has no limitation thereto.

[0105] In one embodiment, the stress buffer structure 500 further includes a second buffer doping region 530, see Figure 7 .

[0106] The second buffer doping region 530 is located in the dielectric layer 300 and is formed by doping the dielectric layer 300 with second buffer impurities. The dielectric layer 300 is doped with the second buffer impurities to form a porous dielectric material.

[0107] The porous dielectric material can effectively absorb the thermal stress between the dielectric layer 300 and the interconnecting structure 400. Therefore, this embodiment can effectively alleviate the influence of the thermal stress around the interconnecting structure 400.

[0108] As an example, after the dielectric layer 300 is formed, the dielectric layer 300 in the second area A2 can be doped with buffer impurities on the upper part of the dielectric layer 300 by ion implantation or diffusion doping, thereby forming a second buffer doping area 530. The second buffer doping area 530 can be spaced apart from the through-hole structure 400, or can be connected to the through-hole structure 400, and the present application is not limited thereto.

[0109] In one embodiment, the dielectric constant of the porous dielectric material is lower than the dielectric constant of the dielectric layer 300. At this time, the second buffer doping region 530 can also reduce the parasitic capacitance between the interconnecting structure 400 and the surrounding interconnecting structures 400 and the metal structure, thereby making the performance of the semiconductor structure more stable.

[0110] In one embodiment, the material of the dielectric layer 300 includes silicon dioxide, and the second buffer impurities include any one or more of boron, phosphorus, boron phosphorus and nitrogen.

[0111] When silicon dioxide is doped with boron, boron-doped silicate glass (BSG) can be formed. When silicon dioxide is doped with phosphorus, phosphorus-doped silicate glass (PSG) can be formed. When silicon dioxide is doped with boron-phosphorus, boron-phosphorus-doped silicate glass (BPSG) can be formed. When silicon dioxide is doped with nitrogen, silicon oxynitride can be formed.

[0112] Boron-doped silicate glass (BSG), phosphorus-doped silicate glass (PSG), boron-phosphorus-doped silicate (BPSG) glass, and silicon oxynitride are all porous dielectric materials, and their dielectric constants are lower than that of silicon dioxide.

[0113] Therefore, in this embodiment, not only the influence of thermal stress around the connecting structure 400 can be alleviated, but also the parasitic capacitance between the connecting structure 400 and surrounding connecting structures 400 and metal structures can be reduced.

[0114] In one embodiment, the second buffer doped region 530 surrounds the via structure.

[0115] At this time, buffer window structures 520 are provided at various locations around the through-hole structure 400 to buffer the thermal stress between the dielectric layer 300 and the connecting structure 400 , thereby making the performance of the semiconductor structure more stable.

[0116] Of course, in other embodiments, affected by other semiconductor structures or circuit structures, the buffer window structure 520 may also be disposed only in a partial area around the through-hole structure 400 , and the present application has no limitation thereto.

[0117] In one embodiment, please refer to Figure 7 The second buffer doped region 530 covers the entire dielectric layer 300 of the second region A2, so that the second buffer doped region 530 has a sufficient stress buffering range.

[0118] If the stress buffer structure 500 further includes the aforementioned at least one buffer window structure 520 , the buffer window structure 520 is surrounded by the second buffer doping region 530 , thereby greatly enhancing the stress buffering effect of the stress buffer structure 500 , thereby effectively buffering the thermal stress around the connecting structure 400 .

[0119] Understandably, Figure 7 The embodiment shown is only a reference embodiment. The configuration of the second buffer doping region 530 of the present application is not limited thereto. For example, the second buffer doping region 530 may not be configured simultaneously with the buffer window structure 520. In this case, the stress buffer structure 500 only includes the second buffer doping region 530 and the first buffer doping region 510.

[0120] In addition, it is understood that the specific embodiments of the present application are not limited to the forms listed in the above embodiments, and may also have a variety of transformation forms. For example, in some embodiments, the stress buffer structure 500 may also include only the first buffer doping region 510 and the second buffer impurity region 530. Without departing from the inventive concept of the present application, these transformation forms and the above-listed implementation methods all belong to the protection scope of the present application.

[0121] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0122] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: A semiconductor structure having a first region, a second region and a third region, wherein the second region is located between the first region and the third region, and the semiconductor structure comprises: substrate; A shallow trench isolation structure is located in the substrate and isolates the substrate into a plurality of active regions, wherein the active region of the first region is used to form a semiconductor device; A dielectric layer, located on the substrate; a through-hole structure, located in the third region and penetrating the dielectric layer and the substrate; a stress buffer structure, located in the second region, comprising a first buffer doping region, the first buffer doping region being located in the active region and being formed by doping the active region with a first buffer impurity, the atomic radius of the first buffer impurity being smaller than the atomic radius of the substrate material; Wherein, the stress buffer structure further includes at least one buffer window structure, the buffer window structure is located in the dielectric layer and has a spacing with the through hole structure, and includes a buffer through hole structure, wherein the buffer through hole of the buffer through hole structure is filled with a metal plug; The buffer window structure is grounded, or a second end of at least one of the buffer window structures is connected to the active region, or a second end of at least one of the buffer window structures is connected to the first buffer doped region.

2. The semiconductor structure according to claim 1, characterized in that: The substrate material includes silicon, and the first buffer impurities include carbon and / or boron.

3. The semiconductor structure according to claim 1, characterized in that: The first buffer doped region is connected to the through-hole structure.

4. The semiconductor structure according to any one of claims 1, characterized in that: The first buffer doped region surrounds the through-hole structure.

5. The semiconductor structure according to claim 1, characterized in that The semiconductor structure further includes a grounding metal layer structure, and the first end of the buffer window structure is connected to the grounding metal layer structure.

6. The semiconductor structure according to claim 1, characterized in that The buffer window structure further includes at least one buffer metal layer structure and an interconnection via structure connecting the buffer metal layer structure, wherein the buffer via structure connects the metal layer structures.

7. The semiconductor structure according to claim 1, characterized in that: The buffer window structure surrounds the through hole structure.

8. The semiconductor structure according to claim 1, characterized in that: The stress buffer structure further includes a second buffer doping region, which is located in the dielectric layer and is formed by doping the dielectric layer with second buffer impurities. The dielectric layer is doped with the second buffer impurities to form a porous dielectric material.

9. The semiconductor structure according to claim 8, characterized in that: The dielectric constant of the porous dielectric material is lower than the dielectric constant of the dielectric layer material.

10. The semiconductor structure according to claim 8, characterized in that The dielectric layer material includes silicon dioxide, and the second buffer impurities include any one or more of boron, phosphorus, boron phosphorus and nitrogen.

11. The semiconductor structure according to claim 8, characterized in that: The second buffer doped region surrounds the through-hole structure.

12. The semiconductor structure according to claim 11, characterized in that: The second buffer doped region completely covers the dielectric layer of the second region.

13. The semiconductor structure according to claim 1, characterized in that The method for forming the first buffer doping region comprises: Providing the substrate, and forming the shallow trench isolation structure in the substrate; Doping the active regions of the second region and the third region with first buffer impurities to form a first buffer doping initial region; When forming the through hole of the through hole structure in the substrate and the dielectric layer located in the third region, the first buffer doped initial region is penetrated by the through hole of the through hole structure to form a first buffer doped region surrounding and connecting the through hole structure.

Images