Method for manufacturing resonator and method for manufacturing filter

Abstract

This application provides a method for fabricating a resonator, a method for fabricating a resonator, and a filter. The filter fabrication method includes: providing a substrate; forming a seed layer on one side of the substrate; forming a lower electrode on the side of the seed layer away from the substrate; patterning the lower electrode; wet etching the seed layer, such that the edge of the etched seed layer is recessed within the orthogonal projection of the lower electrode onto the substrate; performing a recessed treatment on the side of the lower electrode so that the orthogonal projection of the lower electrode onto the substrate coincides with the orthogonal projection of the seed layer onto the substrate, or so that the orthogonal projection of the lower electrode onto the substrate falls within the orthogonal projection of the seed layer onto the substrate; forming a piezoelectric layer on the side of the lower electrode away from the seed layer; and forming an upper electrode on the side of the piezoelectric layer away from the lower electrode. The technical solution provided in this application improves the yield of depositing a piezoelectric layer after wet etching of the seed layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a preparation method of a resonator, a resonator, a preparation method of a filter and a filter. BACKGROUND

[0002] As a new type of Micro Electro Mechanical System (MEMS) device in resonators, bulk acoustic wave resonators have the advantages of small size, light weight, low insertion loss, wide frequency band and high quality factor, and are well adapted to the upgrading of wireless communication systems.

[0003] Figure 1 is a structural schematic diagram of a resonator provided by the prior art, which includes a substrate 001, a seed layer 10, a lower electrode 20, a piezoelectric layer 30 and an upper electrode 40 in a laminated structure, wherein the substrate 001 is provided with a cavity structure 1a as an acoustic reflection structure. In the preparation process of the resonator, a pad layer or a seed layer 10 can be formed on the sacrificial layer corresponding to the cavity structure 1a before the lower electrode 20 is formed. The material of the seed layer 10 is the same as or similar to that of the piezoelectric layer 30 to be formed in the future, so as to improve the growth quality of the lower electrode 20.

[0004] Referring to Figure 2 , in the prior art, in the preparation process of the seed layer 10 and the lower electrode 20 of the resonator, the manufacturing method of the lower electrode 20 and the seed layer 10 is generally to first deposit an entire film layer of the seed layer 10 and an entire film layer of the lower electrode 20, then perform photolithography, and then perform dry etching on the lower electrode 20 to form a lower electrode 20 with a preset pattern, and then etch the entire film layer of the seed layer 10.

[0005] Among them, the conventional method for etching the entire film layer of the seed layer 10 includes dry etching and wet etching. Referring to Figure 1 , if dry etching is used, over-etching area 11 will exist on the substrate 001 due to process over-etching, which will increase the step between the lower electrode 20 and the substrate 001, thereby affecting the quality of the subsequent deposition of the piezoelectric layer 30. If the depth of the over-etching area 11 is too deep, it will cause the height difference to be too large when the piezoelectric layer 30 is deposited, thereby causing the piezoelectric layer 30 to break at the height difference. Among them, the size of the lower electrode 20 and the seed layer 10 in the X direction is L0.

[0006] In order to avoid the problem of over-etching of the substrate 001 by dry etching, referring to Figure 3 , Figure 3is a structural schematic diagram of another resonator provided by the prior art. If a wet etching is used, the isotropic etching of the wet process will cause the edge of the seed layer 10 to be over-etched and a hollow structure 12 between the substrate 001 and the lower electrode 20 to be generated. The generation of the hollow structure 12 causes the piezoelectric layer 30 deposited at the edge of the lower electrode 20 to have defects such as crystal phase faults or cracks, and the resonator is prone to failure due to electrostatic breakdown in an electro static discharge (ESD) test, which seriously affects the performance of the resonator. The size of the lower electrode 20 in the X direction is L0, and the size of the seed layer 10 in the X direction is L1. Due to the existence of the hollow structure 12, L1 is less than L0. SUMMARY

[0007] The present application provides a resonator manufacturing method, a resonator, a filter manufacturing method and a filter, to improve the yield of depositing a piezoelectric layer after etching a seed layer by a wet process.

[0008] According to an aspect of the present application, a resonator manufacturing method is provided, comprising:

[0009] providing a substrate;

[0010] forming a seed layer on one side of the substrate;

[0011] forming a lower electrode on the side of the seed layer away from the substrate;

[0012] patterning the lower electrode;

[0013] wet etching the seed layer, and the edge of the etched seed layer is retracted within the orthographic projection of the lower electrode on the substrate;

[0014] performing a retraction treatment on the side surface of the lower electrode, so that the orthographic projection of the lower electrode on the substrate coincides with the orthographic projection of the seed layer on the substrate, or so that the orthographic projection of the lower electrode on the substrate falls within the orthographic projection of the seed layer on the substrate;

[0015] forming a piezoelectric layer on the side of the lower electrode away from the seed layer;

[0016] forming an upper electrode on the side of the piezoelectric layer away from the lower electrode.

[0017] Optionally, the retraction treatment on the side surface of the lower electrode comprises:

[0018] removing the material of a preset surface of the lower electrode at least once by an etching process; wherein the preset surface includes the side surface of the lower electrode.

[0019] Optionally, the pre-set surface further comprises a top surface of the lower electrode, and the material of the pre-set surface of the lower electrode is removed at least once by an etching process, including:

[0020] the material of the side surface of the lower electrode and the material of the top surface of the lower electrode are removed at least once by an etching process.

[0021] Optionally, the material of the pre-set surface of the lower electrode is removed by an etching process, including:

[0022] Optionally, the material of the pre-set surface of the lower electrode is removed by an etching process, including:

[0023] Optionally, the material of the pre-set surface of the lower electrode is removed by an etching process, including:

[0024] Optionally, the material of the pre-set surface of the lower electrode is removed by an etching process, including:

[0025] Optionally, the material of the pre-set surface of the lower electrode is removed by an etching process, including:

[0026] Optionally, the material of the pre-set surface of the lower electrode is removed by an etching process, including:

[0027] Optionally, the material of the pre-set surface of the lower electrode is removed by an etching process, including:

[0028] Optionally, the material of the pre-set surface of the lower electrode and the material of the lower electrode are the same.

[0029] According to another aspect of the present application, there is provided a method for preparing a filter, comprising the method for preparing a resonator according to any one of the present application.

[0030] According to another aspect of the present application, there is provided a resonator prepared by the method for preparing a resonator according to any one of the present application.

[0031] According to another aspect of the present application, there is provided a filter comprising two or more resonators according to any one of the present application.

[0032] The technical scheme provided in the application, in the preparation process of forming the seed layer and the lower electrode, the whole film layer of the seed layer and the whole film layer of the lower electrode are deposited first, then photolithography is performed, and then the seed layer is etched by wet etching, but the isotropic etching of the wet process inevitably causes the edge of the seed layer to be etched too much and a hollow structure between the substrate and the lower electrode is inevitably generated; then, by removing the lower electrode material, the side surface of the lower electrode is inwardly retracted, so that the orthographic projection of the lower electrode on the substrate and the orthographic projection of the seed layer on the substrate coincide or the orthographic projection of the lower electrode on the substrate is within the orthographic projection of the seed layer on the substrate, the generation of the hollow structure is avoided, and then the defects such as crystal phase fault or cracking of the piezoelectric layer deposited at the edge of the lower electrode are avoided, the problem that the deposition quality is poor and the piezoelectric layer is prone to breakage when the piezoelectric layer is deposited after the seed layer is etched by the wet process is solved, the yield of the piezoelectric layer deposited after the seed layer is etched by the wet process is improved, and then the yield of the resonator is improved; and when the ESD test is performed, the probability of failure of the resonator due to electrostatic breakdown is reduced, the protection of the resonator is realized, and the cost is reduced.

[0033] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the application, nor is it used to limit the scope of the application. Other features of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical scheme of the application, the drawings needed in the following embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0035] Figure 1 is a structural schematic diagram of a resonator provided by the prior art;

[0036] Figure 2 is a structural schematic diagram corresponding to the etching of the seed layer before the etching of the seed layer after the patterning of the lower electrode;

[0037] Figure 3 is a structural schematic diagram of another resonator provided by the prior art;

[0038] Figure 4 is a flowchart of a preparation method of a resonator according to the application;

[0039] Figures 5-16 is a structural schematic diagram corresponding to each step of a preparation method of a resonator according to the application;

[0040] Figure 17is a flow chart of another method for manufacturing a resonator according to the present application;

[0041] Figure 18 is Figure 17 is a flow chart of the step of removing the material of the preset surface of the lower electrode in S1601 by an etching process. DETAILED DESCRIPTION

[0042] In order to enable persons skilled in the art to better understand the technical solutions provided by the present application, the technical solutions in the embodiments will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor should fall within the scope of protection of the present application.

[0043] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described accompanying drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or components does not have to be limited to only those steps or components clearly listed, but can include other steps or components that are not clearly listed or inherent to such a process, method, product, or device.

[0044] In order to solve the problem that the deposition quality of the piezoelectric layer is poor and the piezoelectric layer is prone to breakage when depositing the piezoelectric layer after etching the seed layer by the wet process in the prior art, the present application provides the following technical solutions:

[0045] Figure 4 is a flow chart of a method for manufacturing a resonator according to the present application. Referring to Figure 4 , the method for manufacturing a resonator comprises the following steps:

[0046] S110, providing a substrate.

[0047] Referring to Figure 5 , a substrate 001 is provided. For example, the substrate 001 can be selected from materials such as monocrystalline silicon, gallium arsenide, sapphire, and quartz. In order to reduce the loss of the substrate 001 to the acoustic wave, referring to Figure 6A groove can also be formed on the surface of the substrate 001 by an etching process before the seed layer is formed, and a sacrificial layer 01 can be filled in the groove by a coating process. The sacrificial layer 01 can be etched by an etching liquid in a subsequent step to obtain a cavity structure as the acoustic reflection structure. For example, the sacrificial layer 01 can include an oxide of silicon, such as phospho silicate glass (PSG).

[0048] S120, forming a seed layer on one side of the substrate.

[0049] Referring to Figure 7 A seed layer 10 is formed on one side of the substrate 001 by a coating process. When the sacrificial layer 01 is provided on the substrate 001, the seed layer 10 covers the sacrificial layer 01 and the substrate 001. Specifically, the material of the seed layer 10 is the same as or similar to the material of the piezoelectric layer to be formed later, for improving the growth quality of the lower electrode 20 to be formed later. For example, the seed layer 10 can be made of aluminum nitride, zinc oxide, lead zirconate titanate piezoelectric ceramic, lithium niobate, lithium tantalate, and potassium niobate.

[0050] S130, forming a lower electrode on the side of the seed layer away from the substrate.

[0051] Referring to Figure 8 The lower electrode 20 is formed on the side of the seed layer 10 away from the substrate 001 by a coating process.

[0052] S140, patterning the lower electrode.

[0053] Referring to Figure 9 The lower electrode 20 is patterned by a photolithography and etching process, so that the orthographic projection of the lower electrode 20 on the substrate 001 covers the sacrificial layer 01 of the resonator, and the sacrificial layer 01 is released to become a cavity structure. For example, the lower electrode 20 can be made of at least one of molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, and titanium with good electrical conductivity. The lower electrode 20 can be formed on the side of the seed layer 10 away from the substrate 001 by a metal lift-off method.

[0054] S150, wet etching the seed layer, and the edge of the etched seed layer is retracted within the orthographic projection of the lower electrode on the substrate.

[0055] Referring to Figure 10The seed layer 10 is wet-etched to form a seed layer 10 with a preset pattern. The edge of the etched seed layer 10 is recessed within the orthogonal projection of the lower electrode 20 onto the substrate 001. Due to the isotropic etching of the wet process, excessive etching of the edge of the seed layer 10 inevitably creates a void structure 12 between the substrate 001 and the lower electrode 20. The dimension of the lower electrode 20 in the X direction is L0, and the dimension of the seed layer 10 in the X direction is L1. Due to the presence of the void structure 12, L1 is smaller than L0.

[0056] S160. The side of the lower electrode is recessed so that the orthographic projection of the lower electrode on the substrate coincides with the orthographic projection of the seed layer on the substrate, or so that the orthographic projection of the lower electrode on the substrate falls within the orthographic projection of the seed layer on the substrate.

[0057] Optionally, see Figure 11 and Figure 12 The lower electrode 20 is recessed by dry etching or wet etching processes. The figure exemplarily shows a structure where the orthogonal projection of the lower electrode 20 onto the substrate 001 coincides with the orthogonal projection of the seed layer 10 onto the substrate 001. It should be noted that in other embodiments, by controlling the size of the recessed side of the lower electrode 20, a scheme can be achieved where the orthogonal projection of the lower electrode 20 onto the substrate 001 falls within the orthogonal projection of the seed layer 10 onto the substrate 001.

[0058] Optionally, see Figure 13 and Figure 14 The lower electrode 20 is recessed on its side and top surfaces using dry or wet etching processes. The figure exemplarily illustrates a structure where the orthographic projection of the lower electrode 20 onto the substrate 001 coincides with the orthographic projection of the seed layer 10 onto the substrate 001. It should be noted that in other embodiments, by controlling the size of the recessed side surface of the lower electrode 20, a scheme can be achieved where the orthographic projection of the lower electrode 20 onto the substrate 001 falls within the orthographic projection of the seed layer 10 onto the substrate 001.

[0059] It should be noted that, Figure 13 and Figure 14 as well as Figure 11 and Figure 12 Both methods involve removing material from the lower electrode 20 to shrink the side surface of the lower electrode 20. Figure 13 and Figure 14 By simultaneously reducing the inward profile of both the side and top surfaces of the lower electrode 20, there is no need to use a mask to block the top surface of the lower electrode 20, thus saving on the number of masks and reducing manufacturing costs. Typically, a mask to block the top surface of the lower electrode 20 can be fabricated by forming photoresist on the top surface of the lower electrode 20 and then using a photolithography process.

[0060] In this embodiment, the side of the lower electrode 20 is reduced inward by removing the material of the lower electrode 20, thus avoiding the generation of the void structure 12.

[0061] S170, A piezoelectric layer is formed on the side of the lower electrode away from the seed layer.

[0062] See Figure 15 A piezoelectric layer 30 is formed on the side of the lower electrode 20 opposite to the seed layer 10 using a coating process. For example, the piezoelectric layer 30 can be selected from at least one of single-crystal piezoelectric thin film materials such as aluminum nitride, zinc oxide, lead zirconate titanate piezoelectric ceramics, lithium niobate, lithium tantalate, and potassium niobate, as well as polycrystalline piezoelectric thin film materials. A certain proportion of rare earth elements can also be doped into the piezoelectric layer 30 to improve the performance of the piezoelectric material layer.

[0063] S180, An upper electrode is formed on the side of the piezoelectric layer opposite to the lower electrode.

[0064] See Figure 15 and Figure 16 The upper electrode 40 can be formed on the side of the piezoelectric layer 30 away from the lower electrode 20 by a coating process, and then the patterned upper electrode 40 can be formed by photolithography and etching processes. Alternatively, the upper electrode 40 can also be formed on the side of the piezoelectric layer 30 away from the lower electrode 20 by a metal lift-off method. For example, the upper electrode 40 can be selected from at least one of molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper and titanium, which have good conductivity.

[0065] See Figure 16 After the upper electrode 40 is formed, the sacrificial layer 01 is etched with an etchant to obtain the cavity structure 1a, which serves as the acoustic reflection structure. Exemplarily, in this embodiment, the acoustic reflection structure is the cavity structure 1a. It should be noted that in other embodiments, the acoustic reflection structure may further include a Bragg reflector layer formed by alternating stacks of high and low acoustic impedance layers, a groove on the back side of the substrate 001 or the substrate 001, a seed layer, and a support structure located between the substrate 001 and the seed layer, forming a cavity structure.

[0066] In the technical solution provided in this embodiment, during the preparation process of forming the seed layer 10 and the lower electrode 20, the entire film layer of the seed layer 10 and the entire film layer of the lower electrode 20 are first deposited, followed by photolithography, and then wet etching is used to etch the seed layer 10. However, due to the isotropic etching of the wet process, the edges of the seed layer 10 are excessively etched, inevitably resulting in a void structure 12 between the substrate 001 and the lower electrode 20. Subsequently, by removing the material of the lower electrode 20, the side surface of the lower electrode 20 is shrunk, so that the orthographic projection of the lower electrode 20 on the substrate 001 coincides with the orthographic projection of the seed layer 10 on the substrate 001, or the orthographic projection of the lower electrode 20 on the substrate 001 coincides with the orthographic projection of the seed layer 10 on the substrate 001. Within the shadow, the generation of void structure 12 is avoided, thereby preventing defects such as crystal phase fracture or cracking of the piezoelectric layer 30 deposited at the edge of the lower electrode 20. This solves the problem of poor deposition quality and easy breakage of the piezoelectric layer 30 after etching the seed layer 10 using the existing wet process, improving the yield of the piezoelectric layer 30 deposited after etching the seed layer using the wet process, and thus improving the yield of the resonator. Moreover, due to the presence of void structure 12, the resonator is prone to failure due to electrostatic breakdown during ESD testing, which seriously affects the performance of the resonator. The solution of this embodiment eliminates void structure 12, thus reducing the probability of resonator failure due to electrostatic breakdown, realizing protection of the resonator during the testing stage, and helping to reduce testing costs.

[0067] Optionally, see Figure 17 The step of S160 to reduce the side surface of the lower electrode includes:

[0068] S1601, The material of the preset surface of the lower electrode is removed at least once by an etching process.

[0069] By controlling the etching process parameters, the thickness of the material removed from the preset surface of the lower electrode 20 in each etching process is kept within a preset thickness range. By increasing the number of etching processes, the orthographic projection of the lower electrode 20 onto the substrate 001 coincides with the orthographic projection of the seed layer 10 onto the substrate 001, or the orthographic projection of the lower electrode 20 onto the substrate 001 falls within the orthographic projection of the seed layer 10 onto the substrate 001, thus avoiding the formation of void structures 12. Since the material thickness of the preset surface of the lower electrode 20 to be removed each time is relatively thin, the thickness of the material removed from the preset surface of the lower electrode 20 in a single etching process can be accurately controlled. When the preset surface is the side surface of the lower electrode 20, see [reference needed]. Figure 11 and Figure 12 The etching process removes material from the side surface of the lower electrode 20. When the preset surface includes both the side surface and the top surface of the lower electrode 20, see [reference needed]. Figure 13 and Figure 14The material on the side surface and top surface of the lower electrode 20 is removed by etching.

[0070] The material of the preset surface of the lower electrode removed by each etching process can be the same as or different from the material of the lower electrode. For the case where the material of the preset surface of the lower electrode removed by each etching process is different from the material of the lower electrode, this application further proposes the following technical solution:

[0071] Optionally, see Figure 18 The step in S1601 of removing the material from the predetermined surface of the lower electrode by etching includes:

[0072] S16010. The preset surface of the lower electrode is oxidized to form an oxide layer on the preset surface of the lower electrode.

[0073] S16011. Remove the oxide layer on the preset surface of the lower electrode by etching process.

[0074] See Figure 11 and Figure 12 The step of removing the material on the side of the lower electrode 20 by etching includes: first, oxidizing the side of the lower electrode 20, and then removing the oxide layer on the side of the lower electrode 20 by etching, so as to shrink the side of the lower electrode 20 inward. By performing the above steps multiple times, the orthographic projection of the lower electrode 20 on the substrate 001 and the orthographic projection of the seed layer 10 on the substrate 001 coincide, or the orthographic projection of the lower electrode 20 on the substrate 001 falls within the orthographic projection of the seed layer 10 on the substrate 001.

[0075] See Figure 13 and Figure 14 The steps of removing the material from the side and top surfaces of the lower electrode 20 by etching include: first, oxidizing the side and top surfaces of the lower electrode 20, and then removing the oxide layer from the side and top surfaces of the lower electrode 20 by etching, so as to shrink the side and top surfaces of the lower electrode 20 inward. By performing the above steps multiple times, the orthographic projection of the lower electrode 20 on the substrate 001 and the orthographic projection of the seed layer 10 on the substrate 001 coincide, or the orthographic projection of the lower electrode 20 on the substrate 001 falls within the orthographic projection of the seed layer 10 on the substrate 001.

[0076] Specifically, the material removed from the preset surface of the lower electrode 20 by the etching process is an oxide layer. The oxide layer is made of a different material than the lower electrode 20. This avoids etching the lower electrode 20 when removing the oxide layer from the preset surface of the lower electrode 20 by the etching process, thereby improving the accuracy of removing the material from the preset surface of the lower electrode 20 by the etching process.

[0077] In one embodiment, the step of oxidizing the preset surface of the lower electrode in S16010 includes oxidizing the preset surface of the lower electrode 20 with an oxidizing agent solution.

[0078] Specifically, by oxidizing the preset surface of the lower electrode 20 with an oxidant solution, the thickness of the oxide layer formed on the preset surface of the lower electrode 20 can be accurately controlled by selecting the appropriate composition and concentration of the oxidant solution.

[0079] Optionally, the oxidizing agent solution includes at least one of hydrogen peroxide solution, potassium permanganate solution, and nitric acid solution.

[0080] Specifically, at least one of hydrogen peroxide solution, potassium permanganate solution, and nitric acid solution is a highly oxidizing agent solution. By controlling its concentration, an oxide layer can be quickly formed on the preset surface of the lower electrode 20.

[0081] In another embodiment, the step of oxidizing the preset surface of the lower electrode in S16010 includes oxidizing the preset surface of the lower electrode by a dry plasma oxidation process.

[0082] Specifically, by controlling the parameters of the dry plasma oxidation equipment, the plasma equipment is controlled to oxidize only the preset surface of the lower electrode 20 without bombardment, thus avoiding the safety hazards caused by using a highly oxidizing oxidant solution during the oxidation process of the preset surface of the lower electrode 20.

[0083] The above technical solution addresses the situation where the material of the preset surface of the lower electrode removed by the etching process is different from the material of the lower electrode. This application also proposes a technical solution where the material of the preset surface of the lower electrode 20 removed by the etching process is the same as the material of the lower electrode 20.

[0084] By directly etching the lower electrode 20, the preset surface material of the lower electrode 20 is removed. By performing the above steps multiple times, the orthographic projection of the lower electrode 20 on the substrate 001 and the orthographic projection of the seed layer 10 on the substrate 001 coincide, or the orthographic projection of the lower electrode 20 on the substrate 001 falls within the orthographic projection of the seed layer 10 on the substrate 001.

[0085] This application also provides a method for fabricating a filter, which includes any of the above-described methods for fabricating a resonator. Therefore, the filter fabrication method provided by this application also possesses the beneficial effects described in any of the above-described methods for fabricating a resonator, and will not be elaborated further here.

[0086] This application also provides a resonator, which is fabricated using any of the resonator fabrication methods described above. Therefore, the resonator provided by this application also possesses the beneficial effects described in any of the resonator fabrication methods described above, which will not be repeated here.

[0087] This application also provides a filter comprising two or more resonators, wherein the resonators include any of the aforementioned resonators, and the resonators are fabricated using any of the aforementioned resonator fabrication methods. Therefore, the filter provided by this application also possesses the beneficial effects described in the fabrication methods of any of the aforementioned resonators, which will not be elaborated further here.

[0088] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0089] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a resonator, characterized in that, include: Provide substrate; A seed layer is formed on one side of the substrate; A lower electrode is formed on the side of the seed layer opposite to the substrate; The lower electrode is graphically represented; The seed layer is wet-etched, and the edge of the etched seed layer is recessed within the orthogonal projection of the lower electrode onto the substrate. The dimension of the lower electrode in the direction parallel to the substrate is L0, and the dimension of the etched seed layer in the direction parallel to the substrate is L1, where L1 is less than L0. The side of the lower electrode is recessed so that the orthographic projection of the lower electrode on the substrate and the orthographic projection of the seed layer on the substrate coincide, or so that the orthographic projection of the lower electrode on the substrate falls within the orthographic projection of the seed layer on the substrate. A piezoelectric layer is formed on the side of the lower electrode opposite to the seed layer; An upper electrode is formed on the side of the piezoelectric layer opposite to the lower electrode.

2. The method for fabricating a resonator according to claim 1, characterized in that, The inward reduction treatment of the side surface of the lower electrode includes: The material of a predetermined surface of the lower electrode is removed at least once by an etching process; wherein the predetermined surface includes the side surface of the lower electrode.

3. The method for fabricating a resonator according to claim 2, characterized in that, The preset surface also includes the top surface of the lower electrode, and the material of the preset surface of the lower electrode removed at least once by an etching process includes: The material on the side surface of the lower electrode and the material on the top surface of the lower electrode are removed at least once by an etching process.

4. The method for fabricating a resonator according to claim 3, characterized in that, The materials used to remove the preset surface of the lower electrode by etching include: The predetermined surface of the lower electrode is subjected to an oxidation treatment to form an oxide layer on the predetermined surface of the lower electrode; The oxide layer on the predetermined surface of the lower electrode is removed by an etching process.

5. The method for fabricating a resonator according to claim 4, characterized in that, The oxidation treatment of the preset surface of the lower electrode includes: The predetermined surface of the lower electrode is oxidized using an oxidizing agent solution.

6. The method for fabricating a resonator according to claim 4, characterized in that, The oxidation treatment of the preset surface of the lower electrode includes: The preset surface of the lower electrode is oxidized using a dry plasma oxidation process.

7. The method for fabricating a resonator according to claim 2, characterized in that, The material of the preset surface of the lower electrode removed by the etching process is the same as the material of the lower electrode.

8. A method for fabricating a filter, characterized in that, The method for fabricating the resonator according to any one of claims 1-7.

9. A resonator, characterized in that, It is prepared by the method of any one of claims 1-7.

10. A filter, characterized in that, It includes two or more resonators as described in claim 9.

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