Flexible circuit substrate and film flip chip packaging structure

Abstract

The present invention provides a flexible circuit substrate, comprising a flexible film and a patterned circuit layer. The flexible film has a chip bonding area. The patterned circuit layer is arranged on the flexible film. The patterned circuit layer comprises a plurality of pins and at least one circuit located in the chip bonding area, the at least one circuit having at least one bend, wherein at least one circuit comprises a plurality of grooves and concave grooves, the plurality of grooves and concave grooves are at least located at at least one bend, and the concave grooves connect the plurality of grooves. A film-on-chip packaging structure comprising the above-mentioned flexible circuit substrate is also provided.

Description

Technical Field

[0001] The invention relates to a circuit substrate and a packaging structure, and in particular to a flexible circuit substrate and a film-covered chip packaging structure. Background Art

[0002] Chip on Film (COF) packaging structure is a technology that packages chips on flexible circuit substrates. In addition, as the circuit design in the current COF packaging structure becomes increasingly complex, circuits may also be laid out in the chip setting area below the chip. When the circuit in the chip setting area bends and changes its direction, it may hinder the flow of the encapsulation colloid (underfill) filled under the chip through capillary phenomenon. That is, the circuit under the chip with a bend and a change in extension direction will become an interference with the flow of the encapsulation colloid, causing the encapsulation colloid to encapsulate air in the encapsulation colloid due to uneven flow rate, which in turn causes bubbles (void) to exist after the encapsulation colloid is cured, reducing product reliability. This situation is particularly prone to occur at the bend of the circuit that is farther away from the edge of the chip and has denser wiring. Summary of the invention

[0003] The present invention provides a flexible circuit substrate and a film-on-chip packaging structure, which can reduce the probability of bubbles existing after the packaging colloid is solidified, thereby improving product reliability.

[0004] A flexible circuit substrate of the present invention comprises a flexible film and a patterned circuit layer. The flexible film has a chip bonding area. The patterned circuit layer is disposed on the flexible film. The patterned circuit layer comprises a plurality of pins and at least one circuit located in the chip bonding area, the at least one circuit having at least one bend, wherein the at least one circuit comprises a plurality of grooves and concave grooves, the plurality of grooves and concave grooves are at least located at the at least one bend, and the concave grooves are connected to the plurality of grooves.

[0005] In one embodiment of the present invention, the chip bonding area has two opposite long sides and two opposite short sides.

[0006] In an embodiment of the present invention, the at least one circuit includes an oblique line segment, the oblique line segment extends obliquely relative to the two long sides or the two short sides, and at least one of the bent sides includes the oblique line segment.

[0007] In an embodiment of the present invention, the at least one circuit connects a plurality of pins located at the long side and the short side.

[0008] In one embodiment of the present invention, the at least one circuit is connected to a plurality of pins located at two opposite long sides.

[0009] In an embodiment of the present invention, the at least one circuit is connected to a plurality of pins located at one of the two long sides or one of the two short sides.

[0010] In one embodiment of the present invention, the plurality of grooves are circular grooves in a plan view.

[0011] In one embodiment of the present invention, the width of the groove is smaller than the diameter of the plurality of concave grooves.

[0012] In one embodiment of the present invention, the outer contour of the at least one circuit where the plurality of grooves and trenches are formed is similar to the plurality of grooves and trenches.

[0013] In an embodiment of the present invention, the depths of the plurality of grooves and trenches are smaller than the thickness of at least one circuit.

[0014] A film-on-chip packaging structure of the present invention comprises the above-mentioned flexible circuit substrate, a chip and a packaging colloid. The chip is arranged on the flexible circuit substrate and is located in the chip bonding area, wherein the chip is electrically connected to a plurality of pins. The packaging colloid covers the chip bonding area and at least fills between the chip and the flexible film, wherein a portion of the packaging colloid is located in a plurality of grooves and concave trenches.

[0015] Based on the above, since the bends of the circuits in the chip bonding area of ​​the flexible circuit substrate are areas where bubbles are prone to form when the packaging colloid is filled (areas where bubbles are easily formed), the present invention designs multiple connected grooves and concave grooves at the bends of the circuits in the chip bonding area. In this way, when making a thin film chip-on-chip packaging structure, the packaging colloid can be filled into the multiple grooves and concave grooves when flowing through the bends of the aforementioned circuits, thereby increasing the fluidity and flow space of the packaging colloid, thereby reducing the probability of the packaging colloid flow being disturbed by the bends of the aforementioned circuits and generating bubble backpacking, thereby reducing the probability of bubbles existing after the packaging colloid is cured, thereby improving product reliability.

[0016] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A is a partial top view of a chip-on-film packaging structure according to an embodiment of the present invention;

[0018] Figure 1B yes Figure 1A An enlarged schematic diagram of region A;

[0019] Figure 1C yes Figure 1A A partially enlarged top view schematic diagram of a line;

[0020] Figure 1D yes Figure 1A A partially enlarged stereoscopic schematic diagram of the line;

[0021] Figure 2 It is a partially enlarged stereoscopic schematic diagram of a circuit according to another embodiment of the present invention.

[0022] It should be noted that, for the sake of clarity, Figure 1A and Figure 1B The chip, solder mask and packaging colloid are presented in perspective drawing. DETAILED DESCRIPTION

[0023] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0024] The directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings shown and are not intended to imply an absolute orientation.

[0025] The present invention is more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the accompanying drawings may be exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

[0026] Figure 1A FIG. 1 is a partial top view of a chip-on-film packaging structure according to an embodiment of the present invention. Figure 1B yes Figure 1A An enlarged schematic diagram of area A. Figure 1C yes Figure 1A A partial enlarged top view schematic diagram of the circuit. Figure 1D yes Figure 1A Please refer to the enlarged stereoscopic diagram of the circuit. Figures 1A to 1D In this embodiment, the chip-on-film packaging structure 1 includes a flexible circuit substrate 10, a chip 20 and a packaging colloid 30, wherein the flexible circuit substrate 10 includes a flexible film 12 having a chip bonding area 121 and a patterned circuit layer 14 disposed on the flexible film 12, the chip 20 is disposed on the flexible circuit substrate 10 and located in the chip bonding area 121, and the packaging colloid 30 covers the chip bonding area 121 and at least fills between the chip 20 and the flexible film 12. Here, the material of the flexible film 12 is, for example, polyimide (PI), polyethylene terephthalate (PET), polyethersulfone (PES), polycarbonate (PC) or other suitable flexible materials.

[0027] Furthermore, the patterned circuit layer 14 includes a plurality of pins 16 and at least one circuit 18 located in the chip bonding area 121, and the at least one circuit 18 has at least one bend B. The chip 20 is electrically connected to the plurality of pins 16 through a plurality of bumps 22. The encapsulation colloid 30 is applied along the edge of the chip 20 by dispensing, and then flows into the space between the chip 20 and the flexible film 12 by capillary phenomenon. However, the bend B of the circuit 18 located in the chip bonding area 121 is likely to hinder the flow of the encapsulation colloid 30, making the bend B a bubble-prone area (bubble-prone area) when the encapsulation colloid 30 is filled. Therefore, in this embodiment, a plurality of grooves 18a and grooves 18b are designed to be connected in the circuit 18 in the chip bonding area 121 of the flexible circuit substrate 10, and the plurality of grooves 18a and grooves 18b are connected to each other. 8b is at least located at the bend B. In this way, when the thin film flip chip packaging structure 1 is manufactured, the packaging colloid 30 can be filled into the multiple grooves 18a and grooves 18b when flowing through the bend B of the aforementioned circuit 18, so that part of the packaging colloid 30 is located in the multiple grooves 18a and grooves 18b, increasing the fluidity and flow space of the packaging colloid 30, so as to reduce the probability of the packaging colloid 30 being disturbed by the bend B of the circuit 18 and generating the bubble back packing phenomenon, thereby reducing the probability of bubbles existing after the packaging colloid 30 is cured, and improving the product reliability. It should be noted that the present invention does not limit the number of grooves 18a and grooves 18b, and the position of the grooves 18a and grooves 18b in the circuit 18 is not limited to only at the bend B, and can be determined according to the actual design requirements.

[0028] On the other hand, please refer to Figure 1A and Figure 1B , the chip bonding area 121 may have two opposite long sides L1 and two opposite short sides L2. The circuit 18 may include an oblique line segment S, the oblique line segment S extends obliquely relative to the two long sides L1 or the two short sides L2, and one side of the bend B may include the oblique line segment S. In other words, the bend B is formed by the oblique line segment S and other sections of the circuit 18, and the angle between the oblique line segment S and the other sections is not 0 degrees to form the bend B, but the present invention is not limited thereto.

[0029] Furthermore, the circuit 18 may include a circuit 181, a circuit 182, and a circuit 183 connected to different pins 16. For example, Figure 1A As shown, the line 181 can connect the pin 161 located at the long side L1 and the pin 162 located at the short side L2, the line 182 can connect the pin 161a and the pin 161b located at the two opposite long sides L1, and the line 183 can connect the multiple pins 161b located at one of the two long sides L1 or the multiple pins 162a located at one of the two short sides L2. However, the line 181, the line 182 or the line 183 of the present invention are not limited to Figure 1AIn other words, the circuit 18 of this embodiment can be designed in different areas within the chip bonding area 121 according to the needs, and has a wider range of applications. The aforementioned pins 161 and 162, pins 161a and 161b, and multiple pins 161b or multiple pins 162a can form a loop design through the connection of circuits 181, 182, and 183, respectively. In addition, in one embodiment, the pins 161a and 161b located on the two opposite long sides L1 can be input pins and output pins, respectively, but the present invention is not limited to this.

[0030] Please refer to Figure 1C and Figure 1D In one embodiment, the plurality of grooves 18a are circular grooves in a top view. Further, since bubbles of the encapsulating colloid 30 are easily accumulated at the corners of the grooves 18a, which will reduce the ability of the grooves 18a to suppress bubbles, the circular grooves are designed to prevent the formation of corners, thereby preventing bubbles from accumulating in the grooves 18a and improving the ability of the grooves 18a to suppress bubbles. However, the present invention is not limited thereto. In a top view, the plurality of grooves 18a can be any suitable shape.

[0031] In one embodiment, the width W1 of the groove 18b is smaller than the diameter D of the plurality of grooves 18a. In other words, the groove 18b may be an indented section between the plurality of grooves 18a, but the present invention is not limited thereto. In an embodiment not shown, the width W1 of the groove 18b may be approximately equal to the diameter D of the groove 18a.

[0032] In one embodiment, the diameter D of the groove 18a is smaller than the width W2 of the circuit 18, so that the circuit 18 still maintains a side wall to define the outline of the groove 18a. In addition, the depth T1 of the plurality of grooves 18a and the groove 18b is smaller than the thickness T2 of the circuit 18. Further, the plurality of grooves 18a and the groove 18b can be formed by etching the circuit 18, and the etching does not completely eat through the circuit 18, so that the plurality of grooves 18a and the groove 18b only partially penetrate the circuit 18, so that the circuit 18 can still maintain a sufficient cross-sectional area to load the amount of current required to pass through, thereby avoiding affecting the electrical conduction efficiency of the patterned circuit layer 14. Here, the depth T1 of the plurality of grooves 18a and the groove 18b can be substantially the same.

[0033] In one embodiment, in order to prevent the circuit layer from being contaminated and improve the electrical isolation effect between the pins, the chip-on-film packaging structure 1 further includes a solder mask 40. Further, the solder mask 40 can partially cover the pins 16 and expose the chip bonding area 121, but the present invention is not limited thereto.

[0034] It must be noted here that the following embodiments continue to use the component numbers and some contents of the above-mentioned embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the above-mentioned embodiments, and the following embodiments will not be repeated.

[0035] Figure 2 is a three-dimensional schematic diagram of a circuit according to another embodiment of the present invention. Figure 2 In this embodiment, the outer contour of the circuit 18' is similar to the plurality of grooves 18a and the grooves 18b. In other words, the outer contour of the circuit 18' conforms to the shape changes of the plurality of grooves 18a and the grooves 18b to form line segments of non-uniform width.

[0036] In summary, since the bends of the circuits in the chip bonding area of ​​the flexible circuit substrate are areas where bubbles are prone to occur when the packaging colloid is filled (areas where bubbles are easily formed), the present invention designs multiple connected grooves and concave grooves at the bends of the circuits in the chip bonding area. In this way, when making a thin film flip chip packaging structure, the packaging colloid can be filled into the multiple grooves and concave grooves when flowing through the bends of the aforementioned circuits, thereby increasing the fluidity and flow space of the packaging colloid, thereby reducing the probability of the packaging colloid being disturbed by the bends of the aforementioned circuits and generating bubble backpacking, thereby reducing the probability of bubbles existing after the packaging colloid is cured, thereby improving product reliability.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A flexible circuit substrate, characterized in that: include: A flexible film having a chip bonding area; as well as A patterned circuit layer is arranged on the flexible film, and the patterned circuit layer includes a plurality of pins and at least one circuit located in the chip bonding area, and the at least one circuit has at least one bend, wherein the at least one circuit includes a plurality of grooves and trenches, and the plurality of grooves and the trenches are at least located at the at least one bend, and the trenches connect the plurality of grooves.

2. The flexible circuit substrate according to claim 1, characterized in that: The chip bonding area has two opposite long sides and two opposite short sides.

3. The flexible circuit substrate according to claim 2, characterized in that: The at least one line includes an oblique line segment, the oblique line segment extends obliquely relative to the two long sides or the two short sides, and one side of the at least one bend includes the oblique line segment.

4. The flexible circuit substrate according to claim 2, characterized in that: The at least one circuit connects the plurality of pins located at the long side and the short side.

5. The flexible circuit substrate according to claim 2, characterized in that: The at least one circuit connects the plurality of pins located at the two opposite long sides.

6. The flexible circuit substrate according to claim 2, characterized in that: The at least one circuit connects the plurality of pins located at one of the two long sides or one of the two short sides.

7. The flexible circuit substrate according to claim 1, characterized in that: In a top view, the plurality of grooves are circular grooves.

8. The flexible circuit substrate according to claim 7, characterized in that: The width of the groove is smaller than the diameter of the plurality of grooves.

9. The flexible circuit substrate according to claim 1, characterized in that: The outer contour of the at least one circuit conforms to the shape changes of the plurality of grooves and the grooves.

10. The flexible circuit substrate according to claim 1, characterized in that: The depths of the plurality of grooves and the trench are smaller than the thickness of the at least one circuit.

11. A chip-on-film packaging structure, characterized in that: include: The flexible circuit substrate according to any one of claims 1 to 10; A chip, disposed on the flexible circuit substrate and located in the chip bonding area, wherein the chip is electrically connected to the plurality of pins; as well as The packaging colloid covers the chip bonding area and at least fills the space between the chip and the flexible film, wherein a portion of the packaging colloid is located in the plurality of grooves and the trench.

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