Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel, the array substrate comprising: a base substrate, an intermediate layer, a first conductive layer, and an electrostatic resistance barrier layer; the base substrate has a display area and a frame glue area surrounding the display area; the intermediate layer is arranged on the base substrate and located in the frame glue area; the first conductive layer is arranged on a side of the intermediate layer away from the base substrate and located in the frame glue area; the electrostatic resistance barrier layer is arranged on a side of the first conductive layer away from the base substrate and located in the frame glue area. The array substrate is provided with an electrostatic resistance barrier layer to prevent the first conductive layer from being broken down by static electricity and causing a short circuit, thereby improving the yield rate of the product.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Electrostatic discharge (ESD) can occur rapidly with extremely high intensity, breaking down semiconductor devices or generating enough heat to melt semiconductor devices, thereby causing damage and scrapping of some components, resulting in huge economic losses.

[0003] In the prior art liquid crystal display panel, in order to achieve a narrow frame, the frame glue covers part of the GOA (Gate Driver on Array, array substrate row drive technology) signal line. The frame glue is an insulating material, but because it contains impurities, the insulation performance is poor. During the manufacturing, production, assembly, and testing of the display device, static electricity is easily generated on the display device due to friction, or due to electrical connection, external static electricity in the air, human body, or other charged objects will be transferred to the display device. When static electricity accumulates on the surface of the substrate for a long time, electrostatic discharge will occur, generating an instantaneous kilovolt voltage, causing the GOA signal line to short-circuit the common electrode on the surface of the color film substrate, the GOA signal line to be broken down, and the semiconductor device electrically connected to the GOA signal line to be damaged, making the GOA signal abnormal, and the panel cannot be normally lit, resulting in yield loss.

[0004] In summary, how to prevent the GOA signal line from being short-circuited by static electricity and thus causing a decrease in yield is an urgent problem that needs to be solved. Summary of the invention

[0005] The embodiments of the present application provide an array substrate and a display panel, which can prevent the first conductive layer from being broken down by static electricity and causing a short circuit, thereby improving the yield rate of the product.

[0006] On the one hand, an embodiment of the present application provides an array substrate, comprising: a base substrate, an intermediate layer, a first conductive layer, and an electrostatic resistance insulating layer; the base substrate has a display area and a frame glue area surrounding the display area; the intermediate layer is arranged on the base substrate and is located in the frame glue area; the first conductive layer is arranged on a side of the intermediate layer away from the base substrate and is located in the frame glue area; the electrostatic resistance insulating layer is arranged on a side of the first conductive layer away from the base substrate and is located in the frame glue area.

[0007] Optionally, in an embodiment of the present application, the intermediate layer includes a second conductive layer, an insulating layer, a third conductive layer, a flat layer and a via, the second conductive layer is arranged on the base substrate, the insulating layer covers the second conductive layer, the third conductive layer is arranged on a side of the insulating layer away from the base substrate, the flat layer covers the third conductive layer and the insulating layer, and the first conductive layer is arranged on a side of the flat layer away from the base substrate; the via includes a first via and a second via, the first via passes through the flat layer and is arranged corresponding to the third conductive layer, and the first conductive layer is connected to the second conductive layer through the first via; the second via is arranged on a side of the first via close to the display area, the second via passes through the flat layer and the insulating layer and is arranged corresponding to the second conductive layer, and the first conductive layer is connected to the third conductive layer through the second via; the second conductive layer and the third conductive layer are connected to each other through the first conductive layer.

[0008] Optionally, in an embodiment of the present application, the first conductive layer includes a conductive portion, and the conductive portion is arranged in a one-to-one correspondence with the via hole; the static resistance isolation layer includes static resistance isolation bars, and the static resistance isolation bars at least partially cover the conductive portion.

[0009] Optionally, in an embodiment of the present application, the cross-sectional width of the static resistance isolating strip is equal to the cross-sectional width of the conductive portion, and / or the cross-sectional length of the static resistance isolating strip is equal to the cross-sectional length of the conductive portion.

[0010] Optionally, in an embodiment of the present application, the first conductive layer includes a plurality of conductive parts arranged at intervals, and at least some of the conductive parts are provided with static resistance isolation strips.

[0011] Optionally, in an embodiment of the present application, the static resistance isolation strips and the conductive parts are arranged in a one-to-one correspondence.

[0012] Optionally, in the embodiment of the present application, the static electric isolation strip covers a plurality of the conductive parts.

[0013] Optionally, in an embodiment of the present application, the material of the static resistance barrier layer includes polystyrene.

[0014] Optionally, in an embodiment of the present application, the display area is provided with a thin film transistor array, and the thin film transistor array is electrically connected to the third conductive layer.

[0015] On the other hand, the present application also provides a display panel, comprising the array substrate, color film substrate and frame glue as described above, wherein the color film substrate is arranged opposite to the array substrate, and the frame glue is arranged between the array substrate and the color film substrate; an electrostatic resistance isolation layer is provided on the side of the array substrate close to the frame glue; and a common electrode layer is provided on the side of the color film substrate close to the frame glue.

[0016] The embodiment of the present application provides an array substrate and a display panel, the array substrate comprising: a base substrate, an intermediate layer, a first conductive layer, and an electrostatic resistance barrier layer; the base substrate has a display area and a sealant area surrounding the display area; the intermediate layer is arranged on the base substrate and located in the sealant area; the first conductive layer is arranged on a side of the intermediate layer away from the base substrate and located in the sealant area; the electrostatic resistance barrier layer is arranged on a side of the first conductive layer away from the base substrate and located in the sealant area. The array substrate is provided with an electrostatic resistance barrier layer to prevent the first conductive layer from being broken down by static electricity and causing a short circuit, thereby improving the yield rate of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a schematic top view of an array substrate provided in an embodiment of the present application;

[0019] Figure 2 yes Figure 1 A schematic cross-sectional view of the middle array substrate along the AA' direction;

[0020] Figure 3 This is a first schematic top view of the array substrate frame glue area provided in an embodiment of the present application;

[0021] Figure 4 This is a second schematic top view of the array substrate frame glue area provided in an embodiment of the present application;

[0022] Figure 5 This is a third schematic top view of the array substrate frame glue area provided in the embodiment of the present application;

[0023] Figure 6 This is a fourth schematic top view of the array substrate frame glue area provided in the embodiment of the present application;

[0024] Figure 7 This is a fifth schematic top view of the array substrate frame glue area provided in the embodiment of the present application;

[0025] Figure 8 This is a sixth top view schematic diagram of the array substrate frame glue area provided in the embodiment of the present application.

[0026] Fig. 9 It is a cross-sectional schematic diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0028] The embodiments of the present application provide an array substrate and a display panel to reduce the depth of the vias in the array substrate, thereby solving the problem of uneven diffusion of the alignment liquid and improving the display quality. The following are detailed descriptions. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments. In addition, in the description of the present application, the term "including" means "including but not limited to". The terms "first", "second", "third", etc. are used only as labels to distinguish different objects, rather than to describe a specific order.

[0029] See also Figures 1 to 3 , Figure 1 is a schematic top view of an array substrate provided in an embodiment of the present application; Figure 2 yes Figure 1 A schematic cross-sectional view of the middle array substrate along the AA' direction; Figure 3 1 is a first top view schematic diagram of the array substrate frame glue area SA provided in the embodiment of the present application. Figure 1 and Figure 2 As shown, the present application provides an array substrate 100, including: a base substrate 10, an intermediate layer M, a first conductive layer 20, and an electrostatic resistance barrier layer 30, wherein the base substrate 10 has a display area AA and a sealant area SA arranged around the display area AA; the intermediate layer M is arranged on the base substrate 10 and located in the sealant area SA; the first conductive layer 20 is arranged on the intermediate layer M and located in the sealant area SA; the electrostatic resistance barrier layer 30 is arranged on a side of the first conductive layer 20 away from the base substrate 10 and located in the sealant area SA. The intermediate layer M includes a second conductive layer 40, an insulating layer 50, a third conductive layer 60, a planar layer 70, and a via 80.

[0030] The array substrate 100 provided in the present application is provided with an electrostatic resistance barrier layer 30 to prevent the first conductive layer 20, that is, the GOA signal line, from being broken down by static electricity and causing a short circuit, thereby improving the yield rate of the product.

[0031] In the embodiment of the present application, the base substrate 10 can be a glass substrate, wherein the glass substrate is made of uniform material, has high transparency and low reflectivity, and has good thermal stability, so that the properties can remain stable after multiple high-temperature processes. Since a lot of chemicals are used in the semiconductor device manufacturing process, the glass substrate needs to have good chemical resistance. The glass substrate also needs to have sufficient mechanical strength, good precision machining properties, and excellent electrical insulation properties.

[0032] In the embodiment of the present application, the second conductive layer 40 is provided on the base substrate 10, and the second conductive layer 40 may be a metal compound conductive layer formed by multiple layers of metal. The third metal layer is usually made of materials such as aluminum and aluminum alloy, or a metal compound conductive layer formed by stacking an aluminum layer, a tungsten layer, and a chromium layer. It is usually formed by physical vapor deposition technology.

[0033] The insulating layer 50 covers the second conductive layer 40. The insulating layer 50 can be a single layer, which is formed of silicon oxide, silicon nitride or aluminum oxide, and has a thickness of about 150-250nm. Of course, the insulating layer 50 can also be two layers, the first layer is a silicon dioxide film, and in order to improve the quality of the film, a second layer of silicon nitride film is added on the silicon dioxide film.

[0034] The third conductive layer 60 is disposed on the side of the insulating layer 50 away from the base substrate 10. The third conductive layer 60 can be a single metal layer or a multi-layer metal layer. The design of a single metal layer is simple and easy to operate, which is conducive to reducing the thickness of the array substrate; the design of a multi-layer metal layer is conducive to reducing the impedance of the signal line and improving the performance of the array substrate. The material of the third conductive layer 60 can include any metal such as aluminum, copper, silver, gold, molybdenum, indium, tin, or an alloy or compound thereof.

[0035] It should be noted that the frame glue area SA in the present application corresponds to the bus position of GOA, wherein the third conductive layer 60 is provided with a clock signal line, the second conductive layer 40 is provided with a scan line and extends to the display area AA, and the first conductive layer 20 is provided with a clock signal connection line, and the clock signal line and the clock signal connection line are nearly vertically arranged, which are used to connect the clock signal line with the scan line, and multiple clock signal lines and multiple clock signal connection lines transmit the clock signal to the GOA unit (not shown in the figure) located between the frame glue area SA and the display area AA, and multiple GOA units are used to generate corresponding gate drive signals to realize precise control of each scan line of the array substrate. Specifically, the number of clock signals can be adjusted according to the needs of the array substrate, that is, the number of clock signal lines can be adjusted.

[0036] The planar layer 70 covers the third conductive layer 60 and the insulating layer 50. The planar layer 70 mainly plays the role of insulation and planarization. Here, the planar layer 70 can also be set as a passivation layer and an interlayer dielectric layer. However, since the planar layer 70, the passivation layer, and the interlayer dielectric layer all contain impurities, the insulation effect is poor, the high-voltage resistance is weak, and it is easy to conduct electricity under high voltage.

[0037] The via 80 includes a first via 81 and a second via 82. The first via 81 penetrates the planar layer 70 and is arranged corresponding to the third conductive layer 60. The first conductive layer 20 is connected to the second conductive layer 40 through the first via 81. The second via 82 is arranged on the side of the first via 81 close to the display area AA. The second via 82 penetrates the planar layer 70 and the insulating layer 50 and is arranged corresponding to the second conductive layer 40. The first conductive layer 20 is connected to the third conductive layer 60 through the second via 82. The second conductive layer 40 and the third conductive layer 60 are connected to each other through the first conductive layer 20.

[0038] The first conductive layer 20 is disposed on a side of the flat layer 70 away from the base substrate 10, and the first conductive layer 20 includes a conductive portion 21, and the conductive portion 21 is disposed in a one-to-one correspondence with the via hole 80. Specifically, the conductive portion 21 may be in a block shape, and each conductive portion 21 is a clock signal connection line, and the clock signal is transmitted through the first via hole 81 and the second via hole 82. The material of the first conductive layer 20 may be indium tin oxide.

[0039] In the embodiments of the present application, Figure 3 As shown, the static resistance barrier layer 30 includes static resistance barrier strips 31, and the static resistance barrier strips 31 at least partially cover the conductive portion 21. The cross-sectional width of the static resistance barrier strips 31 is greater than the cross-sectional width of the conductive portion 21, and the cross-sectional length of the static resistance barrier strips 31 is less than the cross-sectional length of the conductive portion 21. Figure 1 As shown, the cross-sectional width refers to the length extending along the length direction X of the array substrate, and the cross-sectional length refers to the length extending along the width direction Y of the array substrate. Specifically, the first conductive layer 20 may be provided with a plurality of conductive portions 21 arranged at intervals. Figure 3 exemplarily shows a conductive portion 21 covered with two static resistance isolating bars 31 , wherein the number of static resistance isolating bars 31 can be adjusted as needed, and the present application does not make any specific limitation thereto.

[0040] The strip design of the static resistance isolating strip 31 in the present application is conducive to controlling the thickness of the static resistance isolating layer 30. The static resistance isolating layer 30 includes a plurality of static resistance isolating strips 31 arranged at intervals. Compared with the whole layer arrangement, the strip arrangement is more conducive to controlling the thickness of the static resistance isolating layer 30 while ensuring the influence of static electricity on the conductive part 21 is blocked. In addition, the height of the frame glue area SA is controlled to avoid the frame glue area SA being too bright due to the height of the frame glue area SA being too high while the height of the display area AA is too low, thereby affecting the display quality.

[0041] In the embodiment of the present application, the material of the static resistance barrier layer 30 includes polystyrene, especially polystyrene plastic, which has good insulation, high mechanical strength, good thermal stability, good solvent resistance, and scratch resistance.

[0042] In the embodiment of the present application, the display area AA is provided with a thin film transistor array, and the thin film transistor array is electrically connected to the third conductive layer 60. The display area AA is also provided with a pixel electrode and a common electrode, and the thin film transistor is used to control whether the pixel electrode in the corresponding sub-pixel is passed through a current, and after the current is passed through, a potential difference is formed between the pixel electrode and the common electrode, thereby controlling the liquid crystal deflection of the corresponding sub-pixel area, and further realizing the grayscale control of the corresponding sub-pixel.

[0043] By providing the static isolation bar 31 , the conductive part 21 is prevented from being broken down by static electricity and causing a short circuit, thereby improving the product yield.

[0044] As a specific implementation of this application, please refer to Figure 4 and Figure 2 , Figure 4 1 is a second top view schematic diagram of the array substrate frame glue area SA provided in the embodiment of the present application. Figure 2 , Figure 4 As shown, the present application provides an array substrate 200 , which differs from the array substrate 100 in that the first conductive layer 20 includes a plurality of conductive portions 21 arranged at intervals, and at least some of the conductive portions 21 are provided with static resistance isolation strips 31 .

[0045] The first conductive layer 20 in the array substrate 200 is arranged on the side of the flat layer 70 away from the base substrate 10; the via 80 includes a first via 81 and a second via 82. The conductive portion 21 is arranged in a one-to-one correspondence with the via 80. Specifically, the conductive portion 21 may be in a block shape, and each conductive portion 21 is a clock signal connection line, through which the clock signal is transmitted. The material of the first conductive layer 20 may be indium tin oxide.

[0046] In the embodiment of the present application, the static resistance barrier layer 30 includes a plurality of static resistance barrier strips 31, and the static resistance barrier strips 31 cover the conductive portion 21. The cross-sectional width of the static resistance barrier strips 31 is greater than the cross-sectional width of the conductive portion 21, and the cross-sectional length of the static resistance barrier strips 31 is less than the cross-sectional length of the conductive portion 21. The static resistance barrier strips 31 are only provided on part of the conductive portion 21, and the proportion of the conductive portion 21 not provided with the static resistance barrier strips 31 to the total number of the conductive portions 21 does not exceed 10%.

[0047] The strip design of the static resistance isolating strip 31 in the present application is conducive to controlling the thickness of the static resistance isolating layer 30. The static resistance isolating layer 30 includes a plurality of static resistance isolating strips 31 arranged at intervals. Compared with the whole layer arrangement, the strip arrangement ensures that the influence of static electricity on the conductive part 21 is blocked, and it is more conducive to controlling the thickness of the static resistance isolating layer 30, thereby controlling the height of the frame glue area SA, and avoiding the frame glue area SA being too bright due to the height of the frame glue area SA being too high while the height of the display area AA is too low, and the height difference causes the frame glue area SA to be too bright, affecting the display quality. At the same time, the number of conductive parts 21 not covered with static resistance isolating strips 31 is controlled to be less than 10% of the total number of conductive parts 21, which is conducive to ensuring the anti-static effect of the array substrate.

[0048] As a specific implementation of this application, please refer to Figure 5 and Figure 2 , Figure 5 FIG. 3 is a third top view schematic diagram of the array substrate frame glue area SA provided in the embodiment of the present application. Figure 2 , Figure 5 As shown, the present application provides an array substrate 300 , and the difference between the array substrate 300 and the array substrate 100 is that the static resistance isolation bars 31 and the conductive parts 21 are arranged in a one-to-one correspondence.

[0049] The first conductive layer 20 in the array substrate 300 is arranged on the side of the flat layer 70 away from the base substrate 10; the via 80 includes a first via 81 and a second via 82. The first conductive layer 20 includes a plurality of conductive portions 21 arranged at intervals, and the conductive portions 21 are arranged one-to-one with the vias 80. Specifically, the conductive portion 21 may be in a block shape, and each conductive portion 21 is a clock signal connection line, and the clock signal is transmitted through the first via 81 and the second via 82. The material of the first conductive layer 20 may be indium tin oxide.

[0050] In the embodiment of the present application, the static resistance barrier layer 30 includes a plurality of static resistance barrier strips 31, and the static resistance barrier strips 31 cover the conductive portion 21, wherein the cross-sectional width of the static resistance barrier strips 31 is greater than the cross-sectional width of the conductive portion 21, and the cross-sectional length of the static resistance barrier strips 31 is greater than the cross-sectional length of the conductive portion 21. Furthermore, the static resistance barrier strips 31 are arranged one-to-one with the conductive portion 21.

[0051] The strip design of the static resistance isolating strip 31 in the present application is conducive to controlling the thickness of the static resistance isolating layer 30. The static resistance isolating layer 30 includes a plurality of static resistance isolating strips 31 arranged at intervals. Compared with the whole layer arrangement, the strip arrangement ensures that the influence of static electricity on the conductive part 21 is blocked, and at the same time, it is more conducive to controlling the thickness of the static resistance isolating layer 30, thereby controlling the height of the frame glue area SA, and avoiding the frame glue area SA being too bright due to the height of the frame glue area SA being too high and the height of the display area AA being too low, thereby affecting the display quality. By arranging the static resistance isolating strip 31 to correspond to the conductive part 21 one by one and the cross-sectional area of ​​the static resistance isolating strip 31 being larger than the cross-sectional area of ​​the conductive part 21, the risk of the conductive part 21 being short-circuited by static electricity is greatly reduced, thereby improving the product yield.

[0052] As a specific implementation of this application, please refer to Figure 6 and Figure 2 , Figure 6 FIG. 4 is a fourth top view schematic diagram of the array substrate frame glue area SA provided in the embodiment of the present application. Figure 2 , Figure 6 As shown, the present application provides an array substrate 400, the difference between the array substrate 400 and the array substrate 100 is that the cross-sectional width of the static resistance spacer 31 is equal to the cross-sectional width of the conductive portion 21, and / or the cross-sectional length of the static resistance spacer 31 is equal to the cross-sectional length of the conductive portion 21.

[0053] The first conductive layer 20 in the array substrate 400 is arranged on the side of the flat layer 70 away from the base substrate 10; the via 80 includes a first via 81 and a second via 82. The first conductive layer 20 includes a plurality of conductive portions 21 arranged at intervals, and the conductive portions 21 are arranged one-to-one with the vias 80. Specifically, the conductive portion 21 may be in a block shape, and each conductive portion 21 is a clock signal connection line, and the clock signal is transmitted through the first via 81 and the second via 82. The material of the first conductive layer 20 may be indium tin oxide.

[0054] In the embodiment of the present application, the static resistance barrier layer 30 includes a plurality of static resistance barrier strips 31, and the static resistance barrier strips 31 cover the conductive portion 21, wherein the cross-sectional width of the static resistance barrier strips 31 is equal to the cross-sectional width of the conductive portion 21, and the cross-sectional length of the static resistance barrier strips 31 is equal to the cross-sectional length of the conductive portion 21. Furthermore, the static resistance barrier strips 31 are arranged one-to-one with the conductive portion 21.

[0055] It should be noted that Figure 6It is only schematically shown that the cross-sectional width of the static resistance barrier strip 31 is equal to the cross-sectional width of the conductive part 21, and the cross-sectional length of the static resistance barrier strip 31 is equal to the cross-sectional length of the conductive part 21. Specifically, the cross-sectional width of the static resistance barrier strip 31 may be equal to the cross-sectional width of the conductive part 21, and the cross-sectional length of the static resistance barrier strip 31 may be unequal to the cross-sectional length of the conductive part 21, or the cross-sectional width of the static resistance barrier strip 31 may be unequal to the cross-sectional width of the conductive part 21, and the cross-sectional length of the static resistance barrier strip 31 may be equal to the cross-sectional length of the conductive part 21. Specifically, it can be adjusted according to actual needs, and this application does not make specific limitations here.

[0056] The strip design of the static resistance isolating strip 31 in the present application is conducive to controlling the thickness of the static resistance isolating layer 30. The static resistance isolating layer 30 includes a plurality of static resistance isolating strips 31 arranged at intervals. Compared with the whole layer arrangement, the strip arrangement ensures that the influence of static electricity on the conductive part 21 is blocked, and at the same time, it is more conducive to controlling the thickness of the static resistance isolating layer 30, thereby controlling the height of the frame glue area SA, and avoiding the frame glue area SA being too bright due to the height of the frame glue area SA being too high while the height of the display area AA is too low, and the height difference affects the display quality. By setting the static resistance isolating strip 31 to correspond to the conductive part 21 one by one and the cross-sectional area of ​​the static resistance isolating strip 31 is greater than or equal to the cross-sectional area of ​​the conductive part 21, the risk of the conductive part 21 being short-circuited by static electricity is greatly reduced, thereby improving the product yield.

[0057] As a specific implementation of this application, please refer to Figure 7 , Figure 8 and Figure 2 , Figure 7 This is a fifth schematic top view of the array substrate sealant area SA provided in the embodiment of the present application; Figure 8 6 is a schematic top view of the array substrate sealant area SA provided in the embodiment of the present application. Figure 2 , Figure 7 As shown, the present application provides an array substrate 500 . The difference between the array substrate 500 and the array substrate 100 is that the static resistance isolation strips 31 cover the multiple conductive parts 21 .

[0058] The first conductive layer 20 in the array substrate 500 is arranged on the side of the flat layer 70 away from the base substrate 10; the via 80 includes a first via 81 and a second via 82. The first conductive layer 20 includes a plurality of conductive portions 21 arranged at intervals, and the conductive portions 21 are arranged one-to-one with the vias 80. Specifically, the conductive portion 21 may be in a block shape, and each conductive portion 21 is a clock signal connection line, and the clock signal is transmitted through the first via 81 and the second via 82. The material of the first conductive layer 20 may be indium tin oxide.

[0059] In an embodiment of the present application, the static resistance insulation layer 30 includes a plurality of static resistance insulation strips 31, which cover the conductive portion 21, wherein the cross-sectional width of the static resistance insulation strips 31 is greater than or equal to the cross-sectional width of the conductive portion 21, and the cross-sectional length of the static resistance insulation strips 31 is greater than the cross-sectional length of the conductive portion 21, so that the static resistance insulation strips 31 can cover a plurality of conductive portions 21.

[0060] In the embodiments of the present application, Figure 8 As shown, the static resistance barrier layer 30 includes a plurality of static resistance barrier strips 31, each of which covers a portion of a plurality of conductive portions 21, wherein a cross-sectional width of the static resistance barrier strips 31 is smaller than a cross-sectional width of the conductive portion 21, and a cross-sectional length of the static resistance barrier strips 31 is greater than a cross-sectional length of the conductive portion 21, so that the static resistance barrier strips 31 can cover a portion of the plurality of conductive portions 21, and at least two static resistance barrier strips 31 are disposed on one conductive portion 21.

[0061] It should be noted that the figure only schematically shows the vias arranged at intervals along the width direction of the array substrate. In the actual production process, based on the number of clock signal lines set in the third conductive layer and the connection positions with the scanning lines in the second conductive layer, the arrangement of the vias is not necessarily regular. The present application does not limit the specific arrangement of the multiple vias. It is only necessary to set multiple electrostatic isolation strips on the multiple conductive parts corresponding to the multiple vias to avoid the conductive parts from being broken down by static electricity, thereby improving the product yield.

[0062] The strip design of the static resistance isolating strip 31 in the present application is conducive to controlling the thickness of the static resistance isolating layer 30. The static resistance isolating layer 30 includes a plurality of static resistance isolating strips 31 arranged at intervals. Compared with the whole layer arrangement, the strip arrangement is more conducive to controlling the thickness of the static resistance isolating layer 30 while ensuring the blocking of the influence of static electricity on the conductive part 21, thereby controlling the height of the frame glue area SA, and avoiding the frame glue area SA being too bright due to the height difference of the display area AA being too high, thereby affecting the display quality. By setting static resistance isolating strips 31 and each static resistance isolating strip 31 covering a plurality of conductive parts 21, the risk of the conductive part 21 being short-circuited by static electricity is reduced, while the difficulty of process operation is reduced, the production efficiency of the product is improved, and the product yield is improved.

[0063] On the other hand, see Fig. 9 , Fig. 9 is a cross-sectional schematic diagram of a display panel provided in an embodiment of the present application. Fig. 9As shown, the present application also provides a display panel 600, including the array substrate 100 / 200 / 300 / 400 / 500, the color film substrate 610 and the frame glue 620 as above, the color film substrate 610 and the array substrate 100 / 200 / 300 / 400 / 500 are arranged relative to each other, the frame glue 620 is arranged between the array substrate 100 and the color film substrate 610, and is used to bond the array substrate 100 and the color film substrate 610 into a box, and an electrostatic resistance isolation layer 30 is provided on the side of the array substrate 100 close to the frame glue 620; a common electrode layer 612 is provided on the side of the color film substrate 610 close to the frame glue 620.

[0064] Specifically, the color filter substrate 610 includes a base substrate 611 and a common electrode layer 612 disposed on the base substrate 611 and close to a side of the sealant 620 .

[0065] The array substrate 100 includes: a base substrate 10, an intermediate layer M, a first conductive layer 20, and an electrostatic barrier layer 30, wherein the intermediate layer M includes a second conductive layer 40, an insulating layer 50, a third conductive layer 60, a flat layer 70, and a via hole 80, wherein the base substrate 10 has a display area AA and a frame glue area SA arranged around the display area AA, and the via hole includes a first via hole 81 and a second via hole 82. The specific structure is consistent with the above array substrate 100, so it is not repeated here.

[0066] It should be noted that a non-display sub-area NA is also included between the sealant area SA and the display area AA, and a GOA unit (not shown in the figure) is disposed in the non-display sub-area NA.

[0067] The embodiment of the present application provides an array substrate and a display panel, the array substrate comprising: a base substrate 10, a first conductive layer 20, and an electrostatic resistance barrier layer 30; the base substrate 10 has a display area AA and a sealant area SA arranged around the display area AA; the first conductive layer 20 is arranged on the base substrate 10 and located in the sealant area SA; the electrostatic resistance barrier layer 30 is arranged on a side of the first conductive layer 20 away from the base substrate 10 and located in the sealant area SA. The array substrate is provided with the electrostatic resistance barrier layer 30 to prevent the first conductive layer 20 from being broken down by static electricity and causing a short circuit, thereby improving the yield rate of the product.

[0068] The above is a detailed introduction to an array substrate and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: A base substrate, wherein the base substrate has a display area and a frame glue area surrounding the display area; An intermediate layer, the intermediate layer is arranged on the base substrate and located in the sealant area; A first conductive layer, the first conductive layer is arranged on a side of the intermediate layer away from the base substrate and located in the sealant area, and the first conductive layer includes a plurality of conductive parts arranged at intervals; An electrostatic resistance isolating layer, the electrostatic resistance isolating layer is arranged on a side of the first conductive layer away from the base substrate and located in the sealant area, and the electrostatic resistance isolating layer includes a plurality of electrostatic resistance isolating strips; Wherein, at least part of the conductive part is provided with the static resistance isolation strip; The cross-sectional width of the static resistance spacer is greater than or equal to the cross-sectional width of the conductive portion, and the cross-sectional length of the static resistance spacer is greater than or equal to the cross-sectional length of the conductive portion, the cross-sectional width is the length extending along the length direction of the array substrate, and the cross-sectional length is the length extending along the width direction of the array substrate; The middle layer includes a second conductive layer, an insulating layer, a third conductive layer, a planar layer and a via, the second conductive layer is arranged on the base substrate, the insulating layer covers the second conductive layer, the third conductive layer is arranged on a side of the insulating layer away from the base substrate, the planar layer covers the third conductive layer and the insulating layer, and the first conductive layer is arranged on a side of the planar layer away from the base substrate; The via hole comprises a first via hole and a second via hole, the first via hole penetrates the planar layer and is arranged corresponding to the third conductive layer, and the first conductive layer is conductively connected to the second conductive layer through the first via hole; The second via hole is disposed on a side of the first via hole close to the display area, the second via hole penetrates the planar layer and the insulating layer and is disposed corresponding to the second conductive layer, and the first conductive layer is conductively connected to the third conductive layer through the second via hole; The second conductive layer and the third conductive layer are electrically connected to each other through the first conductive layer; The conductive parts are arranged in one-to-one correspondence with the via holes.

2. The array substrate according to claim 1, characterized in that: The static resistance isolating strips are arranged in one-to-one correspondence with the conductive parts.

3. The array substrate according to claim 1, characterized in that: The static electricity isolating strip covers the plurality of conductive parts.

4. The array substrate according to claim 1, characterized in that: The material of the static resistance barrier layer includes polystyrene.

5. The array substrate according to claim 1, characterized in that: The display area is provided with a thin film transistor array, and the thin film transistor array is electrically connected to the third conductive layer.

6. A display panel, characterized in that: It comprises an array substrate, a color film substrate and a frame glue as described in any one of claims 1 to 5, wherein the color film substrate is arranged opposite to the array substrate, and the frame glue is arranged between the array substrate and the color film substrate; an electrostatic resistance isolation layer is arranged on the side of the array substrate close to the frame glue; and a common electrode layer is arranged on the side of the color film substrate close to the frame glue.

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