Method for Eliminating False Pulses of Secondary-Side Synchronous Rectification Signals in Bidirectional CLLC Resonant Converters

Abstract

The present invention relates to the field of DC / DC converters, and aims to provide a method for eliminating false pulses of secondary-side synchronous rectification signals in bidirectional CLLC resonant converters. The method is implemented based on a synchronous rectification control circuit: it includes a current detection circuit, a first current polarity comparator, a false pulse elimination circuit and a synchronous rectification signal generation circuit that are electrically connected in sequence; wherein the false pulse elimination circuit is composed of three parts arranged in sequence: a rising edge delay filter circuit, a falling edge PMOS instant trigger circuit and a signal shaping circuit; the method includes: obtaining a polarity signal of a secondary-side resonant current; delaying the rising edge of the secondary-side resonant current polarity signal; instant triggering of the falling edge of the secondary-side resonant current polarity signal; and eliminating a synchronous rectification drive signal after the false pulse. The present invention can be electrically connected after the secondary-side resonant current polarity comparator of a traditional bidirectional CLLC resonant circuit; it can eliminate the influence of parasitic parameters in the current, and achieve efficiency improvement under the premise of ensuring the normal operation of the circuit.

Description

Technical Field

[0001] The present invention relates to the field of DC / DC converters, and in particular to a method for eliminating erroneous pulses of a secondary-side synchronous rectification signal in a bidirectional CLLC resonant converter, which is applied to multiple occasions such as microgrid operation, electric vehicle charging and discharging, and energy storage systems. Background Art

[0002] The bidirectional CLLC resonant converter (circuit) is a common bidirectional isolated DC / DC conversion topology. Due to its excellent characteristics of full-power soft switching, small turn-off current at the switching action moment, and small primary bridge arm circulating current, it meets people's demand for high efficiency and high power density of power converters, and is widely used in scenarios such as new energy power generation and power storage, bidirectional charging and discharging of electric vehicles, and microgrids. However, the traditional bidirectional CLLC resonant circuit controls the output power of the converter by adjusting the switching frequency, that is, applying a square wave drive signal with a duty cycle of 0.5 to the primary switch tube, and there is no drive signal to the secondary switch tube, and its body diode is used for uncontrolled rectification. However, the bidirectional CLLC resonant circuit generally uses MOSFET as the switch tube, and its body diode has a large conduction voltage drop. When a large current passes through, the body diode produces a large loss, which reduces the converter efficiency and causes heat dissipation problems.

[0003] Synchronous rectification technology is a common method to solve the problem of MOSFET body diode rectification loss, and has been applied in various circuits. Synchronous rectification technology is to transfer the current that originally passes through the MOSFET body diode to the channel. Under high current conditions, the conduction loss caused by the channel resistance is less than the body diode conduction loss, thereby improving the circuit working efficiency. Since the conduction of the channel requires applying a drive signal to the MOSFET, the key to the implementation of synchronous rectification technology is to use a drive signal to turn on the MOSFET channel when the body diode needs to be turned on. The wrong drive signal will affect the normal operation of the circuit, and the occurrence of errors needs to be avoided.

[0004] Compared with other DC / DC converters that use PWM duty cycle and phase shift control, in the bidirectional CLLC resonant circuit, the timing relationship between the turn-on and turn-off moments of the secondary body diode and the drive signal of the primary MOSFET is relatively complex. In order to obtain accurate secondary synchronous rectification turn-on and turn-off signals, the traditional solution is to sample the secondary resonant current, compare the parts greater than 0 and less than 0, and use them as the drive signals for the upper and lower tubes of the secondary rectifier bridge respectively. However, the bidirectional CLLC resonant circuit operates in the sub-resonant mode, that is, when the switching frequency is less than the resonant frequency, under ideal conditions, there is a discontinuous situation where the secondary resonant cavity does not participate in the primary resonance, and the secondary resonant current is zero at this time. Due to the passive parameters such as resonant inductance, resonant capacitance, parasitic capacitance of MOSFET, and interlayer capacitance between the primary and secondary sides of the transformer on the secondary side of the bidirectional CLLC resonant circuit, when not participating in the primary resonance, the secondary side will generate current oscillations near zero. The detection circuit will be affected by the oscillation and will generate erroneous drive signal pulses, resulting in multiple turns on of the secondary rectifier MOSFET in one switching cycle, causing additional switching losses.

[0005] It can be seen that in the bidirectional CLLC resonant converter, the traditional synchronous rectification generation scheme based on current detection is affected by the passive parameters in the circuit and it is difficult to achieve the same efficiency improvement effect as other traditional circuits. Therefore, it is necessary to improve the existing synchronous rectification technology. Summary of the invention

[0006] The technical problem to be solved by the present invention is to overcome the deficiencies in the prior art and provide a method for eliminating erroneous pulses of a secondary-side synchronous rectification signal in a bidirectional CLLC resonant converter.

[0007] To solve the technical problem, the solution of the present invention is:

[0008] Firstly, a synchronous rectification control circuit for eliminating false pulses of a secondary-side synchronous rectification signal in a bidirectional CLLC resonant converter is provided, comprising a current detection circuit, a first current polarity comparator, a false pulse elimination circuit and a synchronous rectification signal generating circuit electrically connected in sequence; wherein the false pulse elimination circuit is composed of three parts arranged in sequence: a rising edge delay filter circuit, a falling edge PMOS instant trigger circuit and a signal shaping circuit.

[0009] As a preferred solution of the present invention, the false pulse elimination circuit specifically includes:

[0010] A first branch, one end of which is connected to the output end of the first current polarity comparator, and the other end of which is connected to the input end of the second current polarity comparator, and a resistor R is provided on the first branch;

[0011] A second branch, one end of which is connected to the output end of the first current polarity comparator, and the other end is connected to the G pole in the PMOS tube; the PMOS tube includes its body diode, the S pole and the cathode of the diode are both connected to the input end of the second current polarity comparator, and the D pole and the anode of the diode are both grounded; or, one end of the second branch is connected to the output end of the first current polarity comparator, and the other end is connected to the B pole in the PNP transistor; the PNP transistor is connected in parallel with a diode, the E pole and the cathode of the diode are both connected to the input end of the second current polarity comparator, and the C pole and the anode of the diode are both grounded;

[0012] The capacitor C has one end connected to the input end of the second current polarity comparator and the other end connected to the ground.

[0013] Secondly, the present invention provides a bidirectional CLLC resonant converter capable of eliminating false pulses of secondary-side synchronous rectification signals, comprising a power circuit part consisting of a primary-side bridge, a secondary-side bridge and a CLLC resonant cavity, and a synchronous rectification control circuit for sampling the secondary-side resonant current and providing a secondary-side bridge switch tube drive signal; characterized in that the specific circuit structure of the synchronous rectification control circuit is as described above.

[0014] Furthermore, the present invention provides a method for eliminating the secondary side synchronous rectification signal error pulse in the bidirectional CLLC resonant converter based on the aforementioned synchronous rectification control circuit, comprising the following steps:

[0015] (1) Obtaining the polarity signal of the secondary resonant current

[0016] The secondary resonant current i is detected by using the current detection circuit connected to the secondary side of the bidirectional CLLC resonant converter. Lrs The scaled signal i s ; Using the first current polarity comparator, the scaled signal i s After comparing with the first threshold, the polarity signal i of the secondary resonant current is generated. Pol ; The polarity signal i Pol It includes correct driving signal and error pulse signal;

[0017] (2) Delay in rising edge of secondary resonant current polarity signal

[0018] When the secondary resonant current ratio signal i s When the current is greater than the first threshold, the first current polarity comparator outputs a high-level signal; the high-level signal is transmitted to the G pole of the PMOS, and the PMOS tube is turned off; the S-pole voltage of the PMOS tube is charged to the capacitor C through the resistor R by the output high-level signal of the first current polarity comparator, and the rising edge rate of the polarity signal is delayed through the charging process;

[0019] (3) Instant triggering on the falling edge of the secondary resonant current polarity signal

[0020] When the secondary resonant current ratio signal i s When the current is less than the first threshold, the first current polarity comparator outputs a low-level signal; the low-level signal is transmitted to the G pole of the PMOS, and the PMOS tube is turned on; the PMOS tube discharges the charge accumulated on the capacitor C, and the level of the S pole immediately drops to 0;

[0021] After steps (2) and (3), the S-pole voltage V PMOS Compared with the original secondary resonant current polarity signal i Pol In comparison, the rising edge is shaped into a slowly rising state, and the falling edge is basically the same as the original signal;

[0022] (4) Synchronous rectification drive signal after eliminating false pulses

[0023] The second current polarity comparator is used to convert the output voltage V PMOS Compared with the second threshold; due to V PMOS The rising edge is slow, and the delay time t of the error pulse on the rising edge d It cannot rise from 0 to the second threshold value, and cannot trigger the second current polarity comparator to generate a high level and is filtered out; the second current polarity comparator outputs a level signal as a synchronous rectification drive signal for the switch tube on the corresponding bridge arm in the secondary bridge of the bidirectional CLLC resonant converter, thereby eliminating the erroneous pulses in the secondary synchronous rectification signal.

[0024] As a preferred embodiment of the present invention, in the bidirectional CLLC resonant converter, the secondary resonant inductor currents required by the synchronous rectification drive signals of the upper and lower tubes of the secondary rectifier bridge have opposite polarities and the control methods are the same.

[0025] As a preferred solution of the present invention, in step (1), the current detection circuit uses a current transformer or a Rogowski coil for detection.

[0026] As a preferred embodiment of the present invention, in step (1), the secondary side resonant current i Lrs The reduction ratio is determined by the component parameters of the current detection circuit, and the reduction ratio signal i s The maximum value does not exceed the maximum operating voltage V of the first current polarity comparator max The specific value of the maximum operating voltage is determined by the comparator model and the supply voltage.

[0027] As a preferred solution of the present invention, in step (1), the theoretical value of the first threshold is 0, and in an actual circuit it is generally set to a value slightly greater than 0 (a typical value is 0.1).

[0028] As a preferred embodiment of the present invention, in step (2), the value of the capacitor C is determined by the load capacity of the first current polarity comparator, and the typical value is 1nF; the value of the resistor R is determined by the required rising edge delay time t d Determine, R = t d / 3C;t d It is also the maximum error pulse width that can be eliminated by the error pulse elimination circuit. Its typical value is the switching period T s 5%.

[0029] As a preferred solution of the present invention, in step (4), the value of the second threshold is the maximum operating voltage V of the second current polarity comparator. max 95% of.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. In the prior art, the bidirectional CLLC resonant circuit using primary side frequency conversion control, its secondary side resonant inductor and parasitic parameters in the actual circuit will cause resonant current oscillation. The traditional synchronous rectification scheme based on high-frequency secondary side resonant current detection will generate an erroneous synchronous rectification drive signal, affecting the normal operation of the circuit. The secondary side synchronous rectification signal error pulse elimination circuit proposed in the present invention can eliminate the influence of parasitic parameters in the current.

[0032] 2. The present invention starts from the secondary resonant circuit of the bidirectional CLLC resonant circuit, and after signal processing by the high-frequency resonant current detection circuit, the synchronous rectification signal trigger circuit and the synchronous rectification malfunction elimination circuit, an accurate synchronous rectification signal is delivered to the secondary MOSFET of the bidirectional CLLC resonant circuit, thereby achieving efficiency improvement while ensuring the normal operation of the circuit.

[0033] 3. The present invention can be connected after the secondary resonant current polarity comparator of the traditional bidirectional CLLC resonant circuit in a simple electrical connection manner. On the rising edge, the delay filter circuit is used to delay the rising edge rising rate of the output signal of the secondary resonant current polarity comparator. The delay filter circuit has the same delay effect on the falling edge falling rate of the square wave output by the secondary resonant current polarity comparator, and the falling edge PMOS instant trigger circuit is used to eliminate this effect. The signal shaping circuit is used to reshape the signal with a slow rising edge into a square wave signal that is easily recognized by the subsequent driver chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a typical traditional bidirectional CLLC resonant converter synchronous rectification circuit diagram based on resonant current detection;

[0035] Figure 2 It is a bidirectional CLLC resonant converter synchronous rectification circuit diagram with a false pulse elimination function based on resonant current detection proposed in the present invention;

[0036] Figure 3 It is the working waveform of the secondary side synchronous rectification signal error pulse elimination circuit applied to the bidirectional CLLC resonant circuit proposed in the present invention. DETAILED DESCRIPTION

[0037] The present invention is further described below in conjunction with specific embodiments, but the protection scope of the present invention is not limited thereto.

[0038] The typical circuit diagram of the traditional bidirectional CLLC resonant converter based on resonant current detection is as follows: Figure 1 As shown in the figure, it is divided into a power circuit part and a synchronous rectification control circuit part. The power circuit part consists of a primary bridge, a secondary bridge and a CLLC resonant cavity. The power transmission direction from left to right is positive, V p and C p is the primary input voltage and input bus capacitance, V s and C s is the secondary output voltage and output bus capacitance. Switch tubes S1~S4 form the primary bridge, S1 is the upper tube of the first bridge arm of the primary bridge, S2 is the lower tube of the first bridge arm of the primary bridge, S3 is the upper tube of the second bridge arm of the primary bridge, and S4 is the lower tube of the second bridge arm of the primary bridge. Switch tubes S5~S8 form the secondary bridge, S5 is the upper tube of the first bridge arm of the secondary bridge, S6 is the lower tube of the first bridge arm of the secondary bridge, S7 is the upper tube of the second bridge arm of the secondary bridge, and S8 is the lower tube of the second bridge arm of the secondary bridge. MOSFET is usually used as a switch tube in the CLLC circuit. Primary resonant inductor L rp , primary resonant capacitor C rp , secondary side resonant inductor L rs , secondary side resonant capacitor C rs and transformer form a CLLC resonant cavity, where L m is the equivalent primary excitation inductance of the transformer. The synchronous rectification control circuit includes three parts: current detection circuit, current polarity comparator and synchronous rectification signal generation circuit.

[0039] Taking the forward power transmission mode as an example, the controller controls the primary bridge S1~S4 according to the current circuit state and circuit working target. The control signal is a square wave signal with a duty cycle of 50%. The operating frequency is determined by the current circuit state and circuit working target. The drive signals of S1 and S4 are the same, the drive signals of S2 and S3 are the same, and the drive signals of S1 and S2 are complementary. The primary drive signal controls the switch tubes of the primary bridge to conduct in order, generating a maximum value of the input voltage V between points A and B. p The square wave voltage V AB . Square wave voltage V ABAs an excitation, a load-related current is generated on the resonant cavity and the secondary bridge, that is, the energy of the primary side is transferred to the secondary side. When synchronous rectification control is not used to improve the working efficiency of the circuit, the secondary current passes through the body diodes of the secondary rectifier bridge S5~S8, where the body diodes of S5 and S8 are turned on at the same time, the body diodes of S6 and S7 are turned on at the same time, and the body diodes of S5 and S6 are turned on alternately. When synchronous rectification control is used, when the body diodes of S5~S8 need to be turned on, the channels of S5~S8 replace the body diodes to turn on by giving S5~S8 appropriate drive signals.

[0040] exist Figure 1 In the scheme shown, the current is passed through the secondary resonant inductor L rs The secondary resonant current i Lrs Perform current detection and then convert the secondary resonant current i Lrs The current polarity signal is obtained by comparing with the given threshold, and the current polarity signal is the synchronous rectification signal. However, due to the resonant inductance on the secondary side of the bidirectional CLLC resonant converter, the secondary resonant inductance will oscillate with the parasitic capacitance of the secondary switch tubes S5 to S8. Especially when the circuit works in the under-resonance mode, that is, the switching frequency f s Less than the resonant frequency f r When the secondary resonant current oscillates around zero, the oscillation will output an erroneous drive signal after passing through the comparator. The erroneous drive signal will cause the secondary switch to operate multiple times in one switching cycle, resulting in additional switching losses and affecting the energy conversion efficiency.

[0041] Figure 2 The present invention is a bidirectional CLLC resonant converter synchronous rectification circuit diagram with a false pulse elimination function based on resonant current detection. Figure 1 Compared with the traditional scheme in, a false pulse elimination circuit is added between the first current polarity comparator and the synchronous rectification signal generating circuit. The output of the first current polarity comparator is divided into two branches. The first branch passes through the rising edge charging delay circuit composed of resistor R and capacitor C, so that the voltage on capacitor C rises slowly; the second branch is used to transmit the G pole drive signal of the PMOS tube, which is turned on when it is at a low level, so that the voltage on capacitor C is quickly discharged through the PMOS tube. The voltage signal on capacitor C is compared with the second threshold value through the second current polarity comparator. The output waveform of the second current polarity comparator is a reliable synchronous rectification drive signal after eliminating the false pulse, and then the drive signal for driving the switch tube can be obtained through the synchronous rectification signal generating circuit.

[0042] Figure 3 It is the working waveform of the secondary side synchronous rectification signal error pulse elimination circuit applied to the bidirectional CLLC resonant converter proposed in the present invention. 14is the driving signal of the primary switch tubes S1 and S4, i s is the scaled signal of the secondary resonant current, i Pol The secondary resonant current polarity signal containing an error pulse is generated by comparing the secondary resonant current scaled signal with the first threshold through the first current polarity comparator. PMOS It is the voltage waveform of the S pole of PMOS. 58 is the synchronous rectification drive signal of the secondary side switches S5 and S8, G 67 is the synchronous rectification drive signal of the secondary switch tubes S6 and S7. Time t1 is the opening time of the primary switch tube drive signal, time t2 is the opening time of the secondary switch tube synchronous rectification drive signal, and the time interval t1 to t2 is d It is the rising edge delay time composed of the resistor R and the capacitor C. Time t3 is the time when the synchronous rectification drive signal of the secondary side switch tube is turned off. Time t4 is the time when the primary side switch tube drive signal is turned off. The time interval from t3 to t4 is the time period when there is obvious parasitic oscillation in the circuit and error pulses are generated.

[0043] The specific false pulse elimination method proposed by the present invention is:

[0044] Step 1: Get the polarity signal of the secondary resonant current.

[0045] The secondary resonant current i is obtained by connecting the current detection circuit on the secondary side of the bidirectional CLLC resonant converter. Lrs The scaled signal i s , the scaled signal i of the secondary resonant current s The polarity signal i of the secondary resonant current is generated by comparing the first current polarity comparator with the first threshold. Pol , polarity signal i Pol The secondary resonant current i Lrs The scaling ratio is determined by the component parameters of the current detection circuit, and the scaled signal i s The maximum value does not exceed the maximum operating voltage V max The maximum operating voltage of the comparator is determined by the comparator model and the supply voltage. The theoretical value of the first threshold is 0. In actual circuits, it is generally set to a value slightly greater than 0, with a typical value of 0.1.

[0046] Step 2: Delay the rising edge of the secondary side resonant current polarity signal.

[0047] When the secondary resonant current ratio signal i sWhen it is greater than the first threshold, the first current polarity comparator outputs a high-level signal. The output high-level signal is connected to the G pole of the PMOS. At this time, the PMOS is turned off, and the S-pole voltage of the PMOS is charged to the capacitor C through the resistor R by the output high-level signal of the first current polarity comparator. This charging process delays the rising edge rate of the polarity signal. The value of the capacitor C is determined by the load capacity of the first current polarity comparator, and the typical value is 1nF. The value of the resistor R is determined by the required rising edge delay time t d Determine, R = t d / 3C.t d It is also the maximum error pulse width that can be eliminated by the error pulse elimination circuit. Its typical value is the switching period T s 5%.

[0048] Step 3: The falling edge of the secondary resonant current polarity signal is triggered instantly.

[0049] When the secondary resonant current ratio signal i s When the current is less than the first threshold, the first current polarity comparator outputs a low level signal. The output low level signal is connected to the G pole of the PMOS. At this time, the PMOS is turned on, and the PMOS discharges the charge accumulated on the capacitor C, and the level of the S pole immediately drops to 0.

[0050] After step 2 and step 3, the S-pole voltage V PMOS Compared with the original secondary resonant current polarity signal i Pol In comparison, the rising edge is shaped into a slowly rising state, and the falling edge is basically the same as the original signal.

[0051] Step 4: Synchronous rectification drive signal after eliminating the false pulse.

[0052] The PMOS output voltage V PMOS The second current polarity comparator compares the current with the second threshold, the typical value of which is the maximum operating voltage V max 95%. Since V PMOS The rising edge of the second current polarity comparator is slow, and the error pulse cannot rise from 0 to the second threshold within the rising edge delay time td. These error pulses cannot trigger the second current polarity comparator to generate a high level and are filtered out. The reliable synchronous rectification polarity signal G output by the second current polarity comparator 58 The rising edge is relative to the original secondary resonant current polarity signal i Pol Delayed by time t d , the falling edge remains basically unchanged. G 58 is the synchronous rectification drive signal of switch tubes S5 and S8, G 67 is the synchronous rectification drive signal of switch tubes S6 and S7, G 67 The method of obtaining G 58Similarly, only the polarity comparison logic is opposite, which will not be repeated here.

[0053] Based on the above content, it can be seen that the circuit of the present invention is composed of three parts in sequence: a rising edge delay filter circuit, a falling edge PMOS instant trigger circuit, and a signal shaping circuit; together with a traditional bidirectional CLLC resonant circuit, a traditional high-frequency resonant current detection circuit, and a traditional synchronous rectification signal trigger circuit, the accurate synchronous rectification function of the optimized bidirectional CLLC resonant circuit is realized. The present invention is used in a bidirectional CLLC resonant circuit, which can eliminate the influence of synchronous rectification false pulses caused by current oscillation in an actual circuit, improve the power conversion efficiency, and ensure stable operation of the circuit.

[0054] The circuit and method for eliminating the error pulse of the secondary-side synchronous rectification signal applied to the bidirectional CLLC resonant converter proposed in the present invention can eliminate the error pulse of the synchronous rectification signal without relying on a central digital controller, thereby obtaining a reliable synchronous rectification control signal, thereby effectively improving the conversion efficiency of the circuit.

[0055] Finally, it should be noted that the above are only several specific embodiments of the present invention. Obviously, the present invention is not limited to the above embodiments, and there may be many variations and replacements of similar components. For example, the present invention uses PMOS as a falling edge instant trigger control element, and PMOS can be replaced by a PNP transistor with similar performance. All variations that can be directly derived or associated with the content disclosed by ordinary technicians in this field should be considered to be within the scope of protection of the present invention.

Claims

1. A synchronous rectification control circuit for eliminating erroneous pulses of a secondary-side synchronous rectification signal in a bidirectional CLLC resonant converter, characterized in that: It includes a current detection circuit, a first current polarity comparator, a false pulse elimination circuit and a synchronous rectification signal generation circuit which are electrically connected in sequence; wherein the false pulse elimination circuit is composed of three parts which are arranged in sequence: a rising edge delay filter circuit, a falling edge PMOS instant trigger circuit and a signal shaping circuit; The false pulse elimination circuit specifically comprises: a first branch, one end of which is connected to the output end of the first current polarity comparator, and the other end is connected to the input end of the second current polarity comparator, and a resistor R is arranged on the first branch; a second branch, one end of which is connected to the output end of the first current polarity comparator, and the other end is connected to the G pole in the PMOS tube; the PMOS tube includes a body diode, the S pole and the cathode of the diode are both connected to the input end of the second current polarity comparator, and the D pole and the anode of the diode are both grounded; a capacitor C, one end of which is connected to the input end of the second current polarity comparator, and the other end is grounded; The resistor R and the capacitor C constitute a rising edge delay filter circuit, the PMOS tube constitutes a falling edge PMOS instant trigger circuit, and the second current polarity comparator constitutes a signal shaping circuit.

2. A bidirectional CLLC resonant converter capable of eliminating erroneous pulses of a secondary-side synchronous rectification signal, comprising a power circuit portion consisting of a primary-side bridge, a secondary-side bridge and a CLLC resonant cavity, and a synchronous rectification control circuit for sampling a secondary-side resonant current and providing a secondary-side bridge switch tube drive signal; characterized in that: The specific circuit structure of the synchronous rectification control circuit is as described in claim 1.

3. A method for eliminating erroneous pulses of secondary-side synchronous rectification signals in a bidirectional CLLC resonant converter based on the synchronous rectification control circuit of claim 1, characterized in that: The following steps are involved: (1) Obtaining the polarity signal of the secondary resonant current The secondary resonant current i is detected by using the current detection circuit connected to the secondary side of the bidirectional CLLC resonant converter. Lrs The scaled signal i s ; The first current polarity comparator is used to convert the scaled signal i s After comparing with the first threshold, the polarity signal i of the secondary resonant current is generated. Pol ; The polarity signal i Pol It includes correct driving signal and error pulse signal; (2) Delay in rising edge of secondary resonant current polarity signal When the secondary resonant current ratio signal i s When the current is greater than the first threshold, the first current polarity comparator outputs a high-level signal; the high-level signal is transmitted to the G pole of the PMOS, and the PMOS tube is turned off; the S-pole voltage of the PMOS tube is charged to the capacitor C through the resistor R by the output high-level signal of the first current polarity comparator, and the rising edge rate of the polarity signal is delayed through the charging process; (3) Instant triggering of the falling edge of the secondary resonant current polarity signal When the secondary resonant current ratio signal i s When the current is less than the first threshold, the first current polarity comparator outputs a low-level signal; the low-level signal is transmitted to the G pole of the PMOS, and the PMOS tube is turned on; the PMOS tube discharges the charge accumulated on the capacitor C, and the level of the S pole immediately drops to 0; After steps (2) and (3), the S-pole voltage V PMOS Compared with the original secondary resonant current polarity signal i Pol In comparison, the rising edge is shaped into a slowly rising state, and the falling edge is basically the same as the original signal; (4) Synchronous rectification drive signal after eliminating false pulses The second current polarity comparator is used to convert the output voltage V PMOS Compared with the second threshold; due to V PMOS The rising edge is slow, and the delay time t of the error pulse on the rising edge d It cannot rise from 0 to the second threshold value, and cannot trigger the second current polarity comparator to generate a high level and is filtered out; the second current polarity comparator outputs a level signal as a synchronous rectification drive signal for the switch tube on the corresponding bridge arm in the secondary bridge of the bidirectional CLLC resonant converter, thereby eliminating the erroneous pulses in the secondary synchronous rectification signal.

4. The method according to claim 3, characterized in that In the bidirectional CLLC resonant converter, the polarities of the secondary resonant inductor currents required by the synchronous rectification drive signals of the upper and lower tubes of the secondary rectifier bridge are opposite, and the control methods are the same.

5. The method according to claim 3, characterized in that: In step (1), the current detection circuit uses a current transformer or a Rogowski coil for detection.

6. The method according to claim 3, characterized in that: In step (1), the secondary resonant current i Lrs The reduction ratio is determined by the component parameters of the current detection circuit, and the reduction ratio signal i s The maximum value does not exceed the maximum operating voltage V of the first current polarity comparator max The specific value of the maximum operating voltage is determined by the comparator model and the supply voltage.

7. The method according to claim 3, characterized in that In step (1), the theoretical value of the first threshold is 0, and is set to a value slightly greater than 0 in an actual circuit.

8. The method according to claim 3, characterized in that In step (2), the value of capacitor C is determined by the load capacity of the first current polarity comparator and is 1 nF; the value of resistor R is determined by the required rising edge delay time t d Decision, R=t d / 3C;t d It is also the maximum error pulse width that can be eliminated by the error pulse elimination circuit, and its value is the switching period T s 5% of the total.

9. The method according to claim 3, characterized in that: In step (4), the value of the second threshold is the maximum operating voltage V max 95% of.

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